bnx2x: Comments and prints

Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
author: Eilon Greenstein <eilong@broadcom.com> 2009-02-12 03:38:30 -0500
committer: David S. Miller <davem@davemloft.net> 2009-02-16 02:31:57 -0500
commit: f53722514242da8346cbed2223bcea9eed744ebd (patch)
tree: fd2e9b7842c29427b57ba5266d63b3cf8386c197 /drivers/net/bnx2x_init.h
parent: 9898f86d3927bf3526aef433c8ced0b51178c35c (diff)
1 files changed, 47 insertions, 47 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 6fcd1dc51d97..ba370f713b2d 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -429,57 +429,57 @@ struct arb_line {
 /* derived configuration for each read queue for each max request size */
 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
-        {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
+/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-        {{4 , 8 , 4},   {4 , 8 , 4},    {4 , 8 , 4},    {4 , 8 , 4} },
+        { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
-        {{4 , 3 , 3},   {4 , 3 , 3},    {4 , 3 , 3},    {4 , 3 , 3} },
+        { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {16 , 3 , 11},  {16 , 3 , 11} },
+        { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
-        {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
+        { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {64 , 3 , 41} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {64 , 3 , 41} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {64 , 3 , 41} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {64 , 3 , 41} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+/* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+/* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 3 , 6},   {16 , 3 , 11},  {32 , 3 , 21},  {32 , 3 , 21} },
+        { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
-        {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }
+        { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
 };
 /* derived configuration for each write queue for each max request size */
 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
-        {{4 , 6 , 3},   {4 , 6 , 3},    {4 , 6 , 3} },
+/* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
-        {{4 , 2 , 3},   {4 , 2 , 3},    {4 , 2 , 3} },
+        { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {16 , 2 , 11} },
+        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {32 , 2 , 21} },
+        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {32 , 2 , 21} },
+        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {32 , 2 , 21} },
+        { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
-        {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },
+        { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {16 , 2 , 11} },
+        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-        {{8 , 2 , 6},   {16 , 2 , 11},  {16 , 2 , 11} },
+        { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
-        {{8 , 9 , 6},   {16 , 9 , 11},  {32 , 9 , 21} },
+/* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
-        {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },
+        { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
-        {{8 , 9 , 6},   {16 , 9 , 11},  {16 , 9 , 11} },
+        { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
-        {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
+        { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
 };
 /* register addresses for read queues */
 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
-        {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
                PXP2_REG_RQ_BW_RD_UBOUND0},
        {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
                PXP2_REG_PSWRQ_BW_UB1},
@@ -497,7 +497,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
                PXP2_REG_PSWRQ_BW_UB7},
        {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
                PXP2_REG_PSWRQ_BW_UB8},
-        {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
                PXP2_REG_PSWRQ_BW_UB9},
        {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
                PXP2_REG_PSWRQ_BW_UB10},
@@ -517,7 +517,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
                PXP2_REG_RQ_BW_RD_UBOUND17},
        {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
                PXP2_REG_RQ_BW_RD_UBOUND18},
-        {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
                PXP2_REG_RQ_BW_RD_UBOUND19},
        {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
                PXP2_REG_RQ_BW_RD_UBOUND20},
@@ -539,7 +539,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
 /* register addresses for write queues */
 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
-        {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
                PXP2_REG_PSWRQ_BW_UB1},
        {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
                PXP2_REG_PSWRQ_BW_UB2},
@@ -557,7 +557,7 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
                PXP2_REG_PSWRQ_BW_UB10},
        {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
                PXP2_REG_PSWRQ_BW_UB11},
-        {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
                PXP2_REG_PSWRQ_BW_UB28},
        {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
                PXP2_REG_RQ_BW_WR_UBOUND29},
author	Eilon Greenstein <eilong@broadcom.com>	2009-02-12 03:38:30 -0500
committer	David S. Miller <davem@davemloft.net>	2009-02-16 02:31:57 -0500
commit	f53722514242da8346cbed2223bcea9eed744ebd (patch)
tree	fd2e9b7842c29427b57ba5266d63b3cf8386c197 /drivers/net/bnx2x_init.h
parent	9898f86d3927bf3526aef433c8ced0b51178c35c (diff)

diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 6fcd1dc51d97..ba370f713b2d 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h
@@ -429,57 +429,57 @@ struct arb_line {
429		429
430	/* derived configuration for each read queue for each max request size */	430	/* derived configuration for each read queue for each max request size */
431	static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {	431	static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
432	{{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },	432	/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
433	{{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} },	433	{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
434	{{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} },	434	{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
435	{{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} },	435	{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
436	{{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },	436	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
437	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },	437	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
438	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },	438	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
439	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },	439	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
440	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },	440	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
441	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	441	/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
442	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	442	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
443	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	443	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
444	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	444	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
445	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	445	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
446	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	446	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
447	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	447	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
448	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	448	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
449	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	449	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
450	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	450	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
451	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	451	/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
452	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	452	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
453	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	453	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
454	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	454	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
455	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	455	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
456	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	456	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
457	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	457	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
458	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	458	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
459	{{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },	459	{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
460	{{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }	460	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
461	};	461	};
462		462
463	/* derived configuration for each write queue for each max request size */	463	/* derived configuration for each write queue for each max request size */
464	static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {	464	static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
465	{{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} },	465	/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
466	{{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} },	466	{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
467	{{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },	467	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
468	{{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },	468	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
469	{{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },	469	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
470	{{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },	470	{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
471	{{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },	471	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
472	{{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },	472	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
473	{{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },	473	{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
474	{{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} },	474	/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
475	{{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },	475	{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
476	{{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} },	476	{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
477	{{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }	477	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
478	};	478	};
479		479
480	/* register addresses for read queues */	480	/* register addresses for read queues */
481	static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {	481	static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
482	{PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,	482	/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
483	PXP2_REG_RQ_BW_RD_UBOUND0},	483	PXP2_REG_RQ_BW_RD_UBOUND0},
484	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,	484	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
485	PXP2_REG_PSWRQ_BW_UB1},	485	PXP2_REG_PSWRQ_BW_UB1},
@@ -497,7 +497,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
497	PXP2_REG_PSWRQ_BW_UB7},	497	PXP2_REG_PSWRQ_BW_UB7},
498	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,	498	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
499	PXP2_REG_PSWRQ_BW_UB8},	499	PXP2_REG_PSWRQ_BW_UB8},
500	{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,	500	/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
501	PXP2_REG_PSWRQ_BW_UB9},	501	PXP2_REG_PSWRQ_BW_UB9},
502	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,	502	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
503	PXP2_REG_PSWRQ_BW_UB10},	503	PXP2_REG_PSWRQ_BW_UB10},
@@ -517,7 +517,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
517	PXP2_REG_RQ_BW_RD_UBOUND17},	517	PXP2_REG_RQ_BW_RD_UBOUND17},
518	{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,	518	{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
519	PXP2_REG_RQ_BW_RD_UBOUND18},	519	PXP2_REG_RQ_BW_RD_UBOUND18},
520	{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,	520	/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
521	PXP2_REG_RQ_BW_RD_UBOUND19},	521	PXP2_REG_RQ_BW_RD_UBOUND19},
522	{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,	522	{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
523	PXP2_REG_RQ_BW_RD_UBOUND20},	523	PXP2_REG_RQ_BW_RD_UBOUND20},
@@ -539,7 +539,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
539		539
540	/* register addresses for write queues */	540	/* register addresses for write queues */
541	static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {	541	static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
542	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,	542	/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
543	PXP2_REG_PSWRQ_BW_UB1},	543	PXP2_REG_PSWRQ_BW_UB1},
544	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,	544	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
545	PXP2_REG_PSWRQ_BW_UB2},	545	PXP2_REG_PSWRQ_BW_UB2},
@@ -557,7 +557,7 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
557	PXP2_REG_PSWRQ_BW_UB10},	557	PXP2_REG_PSWRQ_BW_UB10},
558	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,	558	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
559	PXP2_REG_PSWRQ_BW_UB11},	559	PXP2_REG_PSWRQ_BW_UB11},
560	{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,	560	/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
561	PXP2_REG_PSWRQ_BW_UB28},	561	PXP2_REG_PSWRQ_BW_UB28},
562	{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,	562	{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
563	PXP2_REG_RQ_BW_WR_UBOUND29},	563	PXP2_REG_RQ_BW_WR_UBOUND29},