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authorEilon Greenstein <eilong@broadcom.com>2008-06-23 23:33:01 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-23 23:33:01 -0400
commit34f80b04f325078ff21123579343d99756ad8d0e (patch)
treeb24ef6256970da8cfad6124dc698a9e351d46eb1 /drivers/net/bnx2x_hsi.h
parente523287e8edad79b4e5753f98dcf8f75cabd3963 (diff)
bnx2x: Add support for BCM57711 HW
Supporting the 57711 and 57711E - refers to in the code as E1H. The 57710 is referred to as E1. To support the new members in the family, the bnx2x structure was divided to 3 parts: common, port and function. These changes caused some rearrangement in the bnx2x.h file. A set of accessories macros were added to make access to the bnx2x structure more readable Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_hsi.h')
-rw-r--r--drivers/net/bnx2x_hsi.h708
1 files changed, 501 insertions, 207 deletions
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index 96208ace1466..e515d68ea20f 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -132,6 +132,12 @@ struct shared_hw_cfg { /* NVRAM Offset */
132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009 133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a 134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
135#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
135 141
136#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 142#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
137#define SHARED_HW_CFG_BOARD_VER_SHIFT 16 143#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
@@ -313,6 +319,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
313 319
314 u32 config; /* 0x450 */ 320 u32 config; /* 0x450 */
315#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 321#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
322#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
316 323
317}; 324};
318 325
@@ -502,20 +509,20 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
502}; 509};
503 510
504 511
505/***************************************************************************** 512/****************************************************************************
506 * Device Information * 513 * Device Information *
507 *****************************************************************************/ 514 ****************************************************************************/
508struct dev_info { /* size */ 515struct dev_info { /* size */
509 516
510 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 517 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
511 518
512 struct shared_hw_cfg shared_hw_config; /* 40 */ 519 struct shared_hw_cfg shared_hw_config; /* 40 */
513 520
514 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 521 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
515 522
516 struct shared_feat_cfg shared_feature_config; /* 4 */ 523 struct shared_feat_cfg shared_feature_config; /* 4 */
517 524
518 struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */ 525 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
519 526
520}; 527};
521 528
@@ -632,7 +639,9 @@ struct drv_port_mb {
632#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 639#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
633#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 640#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
634 641
635 u32 reserved[3]; 642 u32 port_stx;
643
644 u32 reserved[2];
636 645
637}; 646};
638 647
@@ -655,6 +664,11 @@ struct drv_func_mb {
655#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 664#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
656#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 665#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
657 666
667#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
668#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
669#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
670#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
671
658#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 672#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
659 673
660 u32 drv_mb_param; 674 u32 drv_mb_param;
@@ -684,6 +698,11 @@ struct drv_func_mb {
684#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 698#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
685#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 699#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
686 700
701#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
702#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
703#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
704#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
705
687#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 706#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
688 707
689 u32 fw_mb_param; 708 u32 fw_mb_param;
@@ -709,7 +728,13 @@ struct drv_func_mb {
709 u32 iscsi_boot_signature; 728 u32 iscsi_boot_signature;
710 u32 iscsi_boot_block_offset; 729 u32 iscsi_boot_block_offset;
711 730
712 u32 reserved[3]; 731 u32 drv_status;
732#define DRV_STATUS_PMF 0x00000001
733
734 u32 virt_mac_upper;
735#define VIRT_MAC_SIGN_MASK 0xffff0000
736#define VIRT_MAC_SIGNATURE 0x564d0000
737 u32 virt_mac_lower;
713 738
714}; 739};
715 740
@@ -726,6 +751,92 @@ struct mgmtfw_state {
726 751
727 752
728/**************************************************************************** 753/****************************************************************************
754 * Multi-Function configuration *
755 ****************************************************************************/
756struct shared_mf_cfg {
757
758 u32 clp_mb;
759#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
760 /* set by CLP */
761#define SHARED_MF_CLP_EXIT 0x00000001
762 /* set by MCP */
763#define SHARED_MF_CLP_EXIT_DONE 0x00010000
764
765};
766
767struct port_mf_cfg {
768
769 u32 dynamic_cfg; /* device control channel */
770#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
771#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
772#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
773#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
774
775 u32 reserved[3];
776
777};
778
779struct func_mf_cfg {
780
781 u32 config;
782 /* E/R/I/D */
783 /* function 0 of each port cannot be hidden */
784#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
785
786#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
787#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
788#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
789#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
790#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
791 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
792
793#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
794
795 /* PRI */
796 /* 0 - low priority, 3 - high priority */
797#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
798#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
799#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
800
801 /* MINBW, MAXBW */
802 /* value range - 0..100, increments in 100Mbps */
803#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
804#define FUNC_MF_CFG_MIN_BW_SHIFT 16
805#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
806#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
807#define FUNC_MF_CFG_MAX_BW_SHIFT 24
808#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
809
810 u32 mac_upper; /* MAC */
811#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
812#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
813#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
814 u32 mac_lower;
815#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
816
817 u32 e1hov_tag; /* VNI */
818#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
819#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
820#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
821
822 u32 reserved[2];
823
824};
825
826struct mf_cfg {
827
828 struct shared_mf_cfg shared_mf_config;
829 struct port_mf_cfg port_mf_config[PORT_MAX];
830#if defined(b710)
831 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
832#else
833 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
834#endif
835
836};
837
838
839/****************************************************************************
729 * Shared Memory Region * 840 * Shared Memory Region *
730 ****************************************************************************/ 841 ****************************************************************************/
731struct shmem_region { /* SharedMem Offset (size) */ 842struct shmem_region { /* SharedMem Offset (size) */
@@ -760,18 +871,18 @@ struct shmem_region { /* SharedMem Offset (size) */
760 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 871 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
761 872
762 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 873 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
763#if defined(b710)
764 struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */
765#else
766 struct drv_func_mb func_mb[E1H_FUNC_MAX]; 874 struct drv_func_mb func_mb[E1H_FUNC_MAX];
767#endif 875
876 struct mf_cfg mf_cfg;
768 877
769}; /* 0x6dc */ 878}; /* 0x6dc */
770 879
771 880
881
882
772#define BCM_5710_FW_MAJOR_VERSION 4 883#define BCM_5710_FW_MAJOR_VERSION 4
773#define BCM_5710_FW_MINOR_VERSION 0 884#define BCM_5710_FW_MINOR_VERSION 5
774#define BCM_5710_FW_REVISION_VERSION 14 885#define BCM_5710_FW_REVISION_VERSION 1
775#define BCM_5710_FW_COMPILE_FLAGS 1 886#define BCM_5710_FW_COMPILE_FLAGS 1
776 887
777 888
@@ -810,7 +921,7 @@ struct doorbell_hdr {
810}; 921};
811 922
812/* 923/*
813 * doorbell message send to the chip 924 * doorbell message sent to the chip
814 */ 925 */
815struct doorbell { 926struct doorbell {
816#if defined(__BIG_ENDIAN) 927#if defined(__BIG_ENDIAN)
@@ -866,8 +977,10 @@ struct parsing_flags {
866 u16 flags; 977 u16 flags;
867#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 978#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
868#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 979#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
869#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1) 980#define PARSING_FLAGS_VLAN (0x1<<1)
870#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1 981#define PARSING_FLAGS_VLAN_SHIFT 1
982#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
983#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
871#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 984#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
872#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 985#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
873#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 986#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
@@ -891,6 +1004,12 @@ struct parsing_flags {
891}; 1004};
892 1005
893 1006
1007struct regpair {
1008 u32 lo;
1009 u32 hi;
1010};
1011
1012
894/* 1013/*
895 * dmae command structure 1014 * dmae command structure
896 */ 1015 */
@@ -971,72 +1090,107 @@ struct double_regpair {
971 1090
972 1091
973/* 1092/*
974 * The eth Rx Buffer Descriptor 1093 * The eth storm context of Ustorm (configuration part)
975 */ 1094 */
976struct eth_rx_bd { 1095struct ustorm_eth_st_context_config {
977 u32 addr_lo;
978 u32 addr_hi;
979};
980
981/*
982 * The eth storm context of Ustorm
983 */
984struct ustorm_eth_st_context {
985#if defined(__BIG_ENDIAN) 1096#if defined(__BIG_ENDIAN)
986 u8 sb_index_number; 1097 u8 flags;
1098#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1099#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1100#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1101#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1102#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1103#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1104#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1105#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1106#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1107#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
987 u8 status_block_id; 1108 u8 status_block_id;
988 u8 __local_rx_bd_cons; 1109 u8 clientId;
989 u8 __local_rx_bd_prod; 1110 u8 sb_index_numbers;
1111#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1112#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1113#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1114#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
990#elif defined(__LITTLE_ENDIAN) 1115#elif defined(__LITTLE_ENDIAN)
991 u8 __local_rx_bd_prod; 1116 u8 sb_index_numbers;
992 u8 __local_rx_bd_cons; 1117#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1118#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1119#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1120#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1121 u8 clientId;
993 u8 status_block_id; 1122 u8 status_block_id;
994 u8 sb_index_number; 1123 u8 flags;
1124#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1125#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1126#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1127#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1128#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1129#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1130#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1131#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1132#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1133#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
995#endif 1134#endif
996#if defined(__BIG_ENDIAN) 1135#if defined(__BIG_ENDIAN)
997 u16 rcq_cons; 1136 u16 bd_buff_size;
998 u16 rx_bd_cons; 1137 u16 mc_alignment_size;
999#elif defined(__LITTLE_ENDIAN) 1138#elif defined(__LITTLE_ENDIAN)
1000 u16 rx_bd_cons; 1139 u16 mc_alignment_size;
1001 u16 rcq_cons; 1140 u16 bd_buff_size;
1002#endif 1141#endif
1003 u32 rx_bd_page_base_lo;
1004 u32 rx_bd_page_base_hi;
1005 u32 rcq_base_address_lo;
1006 u32 rcq_base_address_hi;
1007#if defined(__BIG_ENDIAN) 1142#if defined(__BIG_ENDIAN)
1008 u16 __num_of_returned_cqes; 1143 u8 __local_sge_prod;
1009 u8 num_rss; 1144 u8 __local_bd_prod;
1010 u8 flags; 1145 u16 sge_buff_size;
1011#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
1012#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
1013#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
1014#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
1015#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
1016#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
1017#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
1018#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1019#elif defined(__LITTLE_ENDIAN) 1146#elif defined(__LITTLE_ENDIAN)
1020 u8 flags; 1147 u16 sge_buff_size;
1021#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0) 1148 u8 __local_bd_prod;
1022#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0 1149 u8 __local_sge_prod;
1023#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
1024#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
1025#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
1026#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
1027#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
1028#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1029 u8 num_rss;
1030 u16 __num_of_returned_cqes;
1031#endif 1150#endif
1032#if defined(__BIG_ENDIAN) 1151#if defined(__BIG_ENDIAN)
1033 u16 mc_alignment_size; 1152 u16 __bd_cons;
1034 u16 agg_threshold; 1153 u16 __sge_cons;
1035#elif defined(__LITTLE_ENDIAN) 1154#elif defined(__LITTLE_ENDIAN)
1036 u16 agg_threshold; 1155 u16 __sge_cons;
1037 u16 mc_alignment_size; 1156 u16 __bd_cons;
1038#endif 1157#endif
1158 u32 bd_page_base_lo;
1159 u32 bd_page_base_hi;
1160 u32 sge_page_base_lo;
1161 u32 sge_page_base_hi;
1162};
1163
1164/*
1165 * The eth Rx Buffer Descriptor
1166 */
1167struct eth_rx_bd {
1168 u32 addr_lo;
1169 u32 addr_hi;
1170};
1171
1172/*
1173 * The eth Rx SGE Descriptor
1174 */
1175struct eth_rx_sge {
1176 u32 addr_lo;
1177 u32 addr_hi;
1178};
1179
1180/*
1181 * Local BDs and SGEs rings (in ETH)
1182 */
1183struct eth_local_rx_rings {
1039 struct eth_rx_bd __local_bd_ring[16]; 1184 struct eth_rx_bd __local_bd_ring[16];
1185 struct eth_rx_sge __local_sge_ring[12];
1186};
1187
1188/*
1189 * The eth storm context of Ustorm
1190 */
1191struct ustorm_eth_st_context {
1192 struct ustorm_eth_st_context_config common;
1193 struct eth_local_rx_rings __rings;
1040}; 1194};
1041 1195
1042/* 1196/*
@@ -1107,9 +1261,9 @@ struct xstorm_eth_extra_ag_context_section {
1107#if defined(__BIG_ENDIAN) 1261#if defined(__BIG_ENDIAN)
1108 u16 __reserved3; 1262 u16 __reserved3;
1109 u8 __reserved2; 1263 u8 __reserved2;
1110 u8 __agg_misc7; 1264 u8 __da_only_cnt;
1111#elif defined(__LITTLE_ENDIAN) 1265#elif defined(__LITTLE_ENDIAN)
1112 u8 __agg_misc7; 1266 u8 __da_only_cnt;
1113 u8 __reserved2; 1267 u8 __reserved2;
1114 u16 __reserved3; 1268 u16 __reserved3;
1115#endif 1269#endif
@@ -1387,7 +1541,13 @@ struct timers_block_context {
1387 u32 __reserved_0; 1541 u32 __reserved_0;
1388 u32 __reserved_1; 1542 u32 __reserved_1;
1389 u32 __reserved_2; 1543 u32 __reserved_2;
1390 u32 __reserved_flags; 1544 u32 flags;
1545#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1546#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1547#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1548#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1549#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1550#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1391}; 1551};
1392 1552
1393/* 1553/*
@@ -1497,11 +1657,19 @@ struct xstorm_eth_st_context {
1497 u32 tx_bd_page_base_hi; 1657 u32 tx_bd_page_base_hi;
1498#if defined(__BIG_ENDIAN) 1658#if defined(__BIG_ENDIAN)
1499 u16 tx_bd_cons; 1659 u16 tx_bd_cons;
1500 u8 __reserved0; 1660 u8 statistics_data;
1661#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1662#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1663#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1664#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1501 u8 __local_tx_bd_prod; 1665 u8 __local_tx_bd_prod;
1502#elif defined(__LITTLE_ENDIAN) 1666#elif defined(__LITTLE_ENDIAN)
1503 u8 __local_tx_bd_prod; 1667 u8 __local_tx_bd_prod;
1504 u8 __reserved0; 1668 u8 statistics_data;
1669#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1670#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1671#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1672#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1505 u16 tx_bd_cons; 1673 u16 tx_bd_cons;
1506#endif 1674#endif
1507 u32 db_data_addr_lo; 1675 u32 db_data_addr_lo;
@@ -1578,7 +1746,7 @@ struct eth_tx_doorbell {
1578struct ustorm_def_status_block { 1746struct ustorm_def_status_block {
1579 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; 1747 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1580 u16 status_block_index; 1748 u16 status_block_index;
1581 u8 reserved0; 1749 u8 func;
1582 u8 status_block_id; 1750 u8 status_block_id;
1583 u32 __flags; 1751 u32 __flags;
1584}; 1752};
@@ -1589,7 +1757,7 @@ struct ustorm_def_status_block {
1589struct cstorm_def_status_block { 1757struct cstorm_def_status_block {
1590 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; 1758 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1591 u16 status_block_index; 1759 u16 status_block_index;
1592 u8 reserved0; 1760 u8 func;
1593 u8 status_block_id; 1761 u8 status_block_id;
1594 u32 __flags; 1762 u32 __flags;
1595}; 1763};
@@ -1600,7 +1768,7 @@ struct cstorm_def_status_block {
1600struct xstorm_def_status_block { 1768struct xstorm_def_status_block {
1601 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; 1769 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1602 u16 status_block_index; 1770 u16 status_block_index;
1603 u8 reserved0; 1771 u8 func;
1604 u8 status_block_id; 1772 u8 status_block_id;
1605 u32 __flags; 1773 u32 __flags;
1606}; 1774};
@@ -1611,7 +1779,7 @@ struct xstorm_def_status_block {
1611struct tstorm_def_status_block { 1779struct tstorm_def_status_block {
1612 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; 1780 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1613 u16 status_block_index; 1781 u16 status_block_index;
1614 u8 reserved0; 1782 u8 func;
1615 u8 status_block_id; 1783 u8 status_block_id;
1616 u32 __flags; 1784 u32 __flags;
1617}; 1785};
@@ -1634,7 +1802,7 @@ struct host_def_status_block {
1634struct ustorm_status_block { 1802struct ustorm_status_block {
1635 u16 index_values[HC_USTORM_SB_NUM_INDICES]; 1803 u16 index_values[HC_USTORM_SB_NUM_INDICES];
1636 u16 status_block_index; 1804 u16 status_block_index;
1637 u8 reserved0; 1805 u8 func;
1638 u8 status_block_id; 1806 u8 status_block_id;
1639 u32 __flags; 1807 u32 __flags;
1640}; 1808};
@@ -1645,7 +1813,7 @@ struct ustorm_status_block {
1645struct cstorm_status_block { 1813struct cstorm_status_block {
1646 u16 index_values[HC_CSTORM_SB_NUM_INDICES]; 1814 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1647 u16 status_block_index; 1815 u16 status_block_index;
1648 u8 reserved0; 1816 u8 func;
1649 u8 status_block_id; 1817 u8 status_block_id;
1650 u32 __flags; 1818 u32 __flags;
1651}; 1819};
@@ -1683,20 +1851,21 @@ struct eth_dynamic_hc_config {
1683 * regular eth FP CQE parameters struct 1851 * regular eth FP CQE parameters struct
1684 */ 1852 */
1685struct eth_fast_path_rx_cqe { 1853struct eth_fast_path_rx_cqe {
1686 u8 type; 1854 u8 type_error_flags;
1687 u8 error_type_flags; 1855#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
1688#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0) 1856#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
1689#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0 1857#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
1690#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1) 1858#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
1691#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1 1859#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
1692#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2) 1860#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
1693#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2 1861#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
1694#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3) 1862#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
1695#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3 1863#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
1696#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4) 1864#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
1697#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4 1865#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
1698#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5) 1866#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
1699#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5 1867#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
1868#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
1700 u8 status_flags; 1869 u8 status_flags;
1701#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 1870#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1702#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 1871#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
@@ -1711,11 +1880,13 @@ struct eth_fast_path_rx_cqe {
1711#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 1880#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1712#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 1881#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1713 u8 placement_offset; 1882 u8 placement_offset;
1883 u8 queue_index;
1714 u32 rss_hash_result; 1884 u32 rss_hash_result;
1715 u16 vlan_tag; 1885 u16 vlan_tag;
1716 u16 pkt_len; 1886 u16 pkt_len;
1717 u16 queue_index; 1887 u16 len_on_bd;
1718 struct parsing_flags pars_flags; 1888 struct parsing_flags pars_flags;
1889 u16 sgl[8];
1719}; 1890};
1720 1891
1721 1892
@@ -1729,6 +1900,23 @@ struct eth_halt_ramrod_data {
1729 1900
1730 1901
1731/* 1902/*
1903 * The data for statistics query ramrod
1904 */
1905struct eth_query_ramrod_data {
1906#if defined(__BIG_ENDIAN)
1907 u8 reserved0;
1908 u8 collect_port_1b;
1909 u16 drv_counter;
1910#elif defined(__LITTLE_ENDIAN)
1911 u16 drv_counter;
1912 u8 collect_port_1b;
1913 u8 reserved0;
1914#endif
1915 u32 ctr_id_vector;
1916};
1917
1918
1919/*
1732 * Place holder for ramrods protocol specific data 1920 * Place holder for ramrods protocol specific data
1733 */ 1921 */
1734struct ramrod_data { 1922struct ramrod_data {
@@ -1758,15 +1946,20 @@ struct eth_rx_bd_next_page {
1758 * Eth Rx Cqe structure- general structure for ramrods 1946 * Eth Rx Cqe structure- general structure for ramrods
1759 */ 1947 */
1760struct common_ramrod_eth_rx_cqe { 1948struct common_ramrod_eth_rx_cqe {
1761 u8 type; 1949 u8 ramrod_type;
1950#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
1951#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
1952#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
1953#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
1762 u8 conn_type_3b; 1954 u8 conn_type_3b;
1763 u16 reserved; 1955 u16 reserved1;
1764 u32 conn_and_cmd_data; 1956 u32 conn_and_cmd_data;
1765#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 1957#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1766#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 1958#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1767#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 1959#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1768#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 1960#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1769 struct ramrod_data protocol_data; 1961 struct ramrod_data protocol_data;
1962 u32 reserved2[4];
1770}; 1963};
1771 1964
1772/* 1965/*
@@ -1775,8 +1968,7 @@ struct common_ramrod_eth_rx_cqe {
1775struct eth_rx_cqe_next_page { 1968struct eth_rx_cqe_next_page {
1776 u32 addr_lo; 1969 u32 addr_lo;
1777 u32 addr_hi; 1970 u32 addr_hi;
1778 u32 reserved0; 1971 u32 reserved[6];
1779 u32 reserved1;
1780}; 1972};
1781 1973
1782/* 1974/*
@@ -1806,11 +1998,6 @@ struct spe_hdr {
1806 u16 reserved; 1998 u16 reserved;
1807}; 1999};
1808 2000
1809struct regpair {
1810 u32 lo;
1811 u32 hi;
1812};
1813
1814/* 2001/*
1815 * ethernet slow path element 2002 * ethernet slow path element
1816 */ 2003 */
@@ -1821,6 +2008,7 @@ union eth_specific_data {
1821 struct eth_halt_ramrod_data halt_ramrod_data; 2008 struct eth_halt_ramrod_data halt_ramrod_data;
1822 struct regpair leading_cqe_addr; 2009 struct regpair leading_cqe_addr;
1823 struct regpair update_data_addr; 2010 struct regpair update_data_addr;
2011 struct eth_query_ramrod_data query_ramrod_data;
1824}; 2012};
1825 2013
1826/* 2014/*
@@ -1843,10 +2031,13 @@ struct eth_tx_db_data {
1843 2031
1844 2032
1845/* 2033/*
1846 * Common configuration parameters per port in Tstorm 2034 * Common configuration parameters per function in Tstorm
1847 */ 2035 */
1848struct tstorm_eth_function_common_config { 2036struct tstorm_eth_function_common_config {
1849 u32 config_flags; 2037#if defined(__BIG_ENDIAN)
2038 u8 leading_client_id;
2039 u8 rss_result_mask;
2040 u16 config_flags;
1850#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 2041#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
1851#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 2042#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
1852#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 2043#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
@@ -1859,17 +2050,32 @@ struct tstorm_eth_function_common_config {
1859#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4 2050#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
1860#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5) 2051#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
1861#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5 2052#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
1862#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6) 2053#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
1863#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6 2054#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
1864#if defined(__BIG_ENDIAN) 2055#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
1865 u16 __secondary_vlan_id; 2056#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
1866 u8 leading_client_id;
1867 u8 rss_result_mask;
1868#elif defined(__LITTLE_ENDIAN) 2057#elif defined(__LITTLE_ENDIAN)
2058 u16 config_flags;
2059#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2060#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2061#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2062#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2063#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2064#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2065#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2066#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2067#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2068#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2069#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2070#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
2071#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2072#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2073#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2074#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
1869 u8 rss_result_mask; 2075 u8 rss_result_mask;
1870 u8 leading_client_id; 2076 u8 leading_client_id;
1871 u16 __secondary_vlan_id;
1872#endif 2077#endif
2078 u16 vlan_id[2];
1873}; 2079};
1874 2080
1875/* 2081/*
@@ -1887,7 +2093,7 @@ struct eth_update_ramrod_data {
1887struct mac_configuration_hdr { 2093struct mac_configuration_hdr {
1888 u8 length_6b; 2094 u8 length_6b;
1889 u8 offset; 2095 u8 offset;
1890 u16 reserved0; 2096 u16 client_id;
1891 u32 reserved1; 2097 u32 reserved1;
1892}; 2098};
1893 2099
@@ -1944,15 +2150,55 @@ struct mac_configuration_cmd {
1944 2150
1945 2151
1946/* 2152/*
2153 * MAC address in list for ramrod
2154 */
2155struct mac_configuration_entry_e1h {
2156 u16 lsb_mac_addr;
2157 u16 middle_mac_addr;
2158 u16 msb_mac_addr;
2159 u16 vlan_id;
2160 u16 e1hov_id;
2161 u8 client_id;
2162 u8 flags;
2163#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2164#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2165#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2166#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2167#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2168#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2169#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2170#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2171};
2172
2173/*
2174 * MAC filtering configuration command
2175 */
2176struct mac_configuration_cmd_e1h {
2177 struct mac_configuration_hdr hdr;
2178 struct mac_configuration_entry_e1h config_table[32];
2179};
2180
2181
2182/*
2183 * approximate-match multicast filtering for E1H per function in Tstorm
2184 */
2185struct tstorm_eth_approximate_match_multicast_filtering {
2186 u32 mcast_add_hash_bit_array[8];
2187};
2188
2189
2190/*
1947 * Configuration parameters per client in Tstorm 2191 * Configuration parameters per client in Tstorm
1948 */ 2192 */
1949struct tstorm_eth_client_config { 2193struct tstorm_eth_client_config {
1950#if defined(__BIG_ENDIAN) 2194#if defined(__BIG_ENDIAN)
1951 u16 statistics_counter_id; 2195 u8 max_sges_for_packet;
2196 u8 statistics_counter_id;
1952 u16 mtu; 2197 u16 mtu;
1953#elif defined(__LITTLE_ENDIAN) 2198#elif defined(__LITTLE_ENDIAN)
1954 u16 mtu; 2199 u16 mtu;
1955 u16 statistics_counter_id; 2200 u8 statistics_counter_id;
2201 u8 max_sges_for_packet;
1956#endif 2202#endif
1957#if defined(__BIG_ENDIAN) 2203#if defined(__BIG_ENDIAN)
1958 u16 drop_flags; 2204 u16 drop_flags;
@@ -1960,42 +2206,42 @@ struct tstorm_eth_client_config {
1960#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 2206#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1961#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) 2207#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1962#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 2208#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1963#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) 2209#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
1964#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 2210#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
1965#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) 2211#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
1966#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 2212#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
1967#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) 2213#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
1968#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 2214#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
1969#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1970#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1971 u16 config_flags; 2215 u16 config_flags;
1972#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) 2216#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1973#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 2217#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1974#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) 2218#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1975#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 2219#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1976#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) 2220#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
1977#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 2221#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2222#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2223#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
1978#elif defined(__LITTLE_ENDIAN) 2224#elif defined(__LITTLE_ENDIAN)
1979 u16 config_flags; 2225 u16 config_flags;
1980#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0) 2226#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1981#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0 2227#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1982#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1) 2228#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1983#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1 2229#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1984#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2) 2230#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
1985#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2 2231#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2232#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2233#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
1986 u16 drop_flags; 2234 u16 drop_flags;
1987#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) 2235#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1988#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 2236#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1989#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) 2237#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1990#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 2238#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1991#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2) 2239#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
1992#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2 2240#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
1993#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3) 2241#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
1994#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3 2242#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
1995#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4) 2243#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
1996#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4 2244#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
1997#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1998#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1999#endif 2245#endif
2000}; 2246};
2001 2247
@@ -2011,96 +2257,112 @@ struct tstorm_eth_mac_filter_config {
2011 u32 bcast_drop_all; 2257 u32 bcast_drop_all;
2012 u32 bcast_accept_all; 2258 u32 bcast_accept_all;
2013 u32 strict_vlan; 2259 u32 strict_vlan;
2014 u32 __secondary_vlan_clients; 2260 u32 vlan_filter[2];
2261 u32 reserved;
2015}; 2262};
2016 2263
2017 2264
2018struct rate_shaping_per_protocol { 2265/*
2266 * Three RX producers for ETH
2267 */
2268struct tstorm_eth_rx_producers {
2019#if defined(__BIG_ENDIAN) 2269#if defined(__BIG_ENDIAN)
2020 u16 reserved0; 2270 u16 bd_prod;
2021 u16 protocol_rate; 2271 u16 cqe_prod;
2022#elif defined(__LITTLE_ENDIAN) 2272#elif defined(__LITTLE_ENDIAN)
2023 u16 protocol_rate; 2273 u16 cqe_prod;
2024 u16 reserved0; 2274 u16 bd_prod;
2025#endif 2275#endif
2026 u32 protocol_quota;
2027 s32 current_credit;
2028 u32 reserved;
2029};
2030
2031struct rate_shaping_vars {
2032 struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2033 u32 pause_mask;
2034 u32 periodic_stop;
2035 u32 rs_periodic_timeout;
2036 u32 rs_threshold;
2037 u32 last_periodic_time;
2038 u32 reserved;
2039};
2040
2041struct fairness_per_protocol {
2042 u32 credit_delta;
2043 s32 fair_credit;
2044#if defined(__BIG_ENDIAN) 2276#if defined(__BIG_ENDIAN)
2045 u16 reserved0; 2277 u16 reserved;
2046 u8 state; 2278 u16 sge_prod;
2047 u8 weight;
2048#elif defined(__LITTLE_ENDIAN) 2279#elif defined(__LITTLE_ENDIAN)
2049 u8 weight; 2280 u16 sge_prod;
2050 u8 state; 2281 u16 reserved;
2051 u16 reserved0;
2052#endif 2282#endif
2053 u32 reserved1;
2054}; 2283};
2055 2284
2056struct fairness_vars {
2057 struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2058 u32 upper_bound;
2059 u32 port_rate;
2060 u32 pause_mask;
2061 u32 fair_threshold;
2062};
2063 2285
2064struct safc_struct { 2286/*
2065 u32 cur_pause_mask; 2287 * common flag to indicate existance of TPA.
2066 u32 expire_time; 2288 */
2289struct tstorm_eth_tpa_exist {
2067#if defined(__BIG_ENDIAN) 2290#if defined(__BIG_ENDIAN)
2068 u16 reserved0; 2291 u16 reserved1;
2069 u8 cur_cos_types; 2292 u8 reserved0;
2070 u8 safc_timeout_usec; 2293 u8 tpa_exist;
2071#elif defined(__LITTLE_ENDIAN) 2294#elif defined(__LITTLE_ENDIAN)
2072 u8 safc_timeout_usec; 2295 u8 tpa_exist;
2073 u8 cur_cos_types; 2296 u8 reserved0;
2074 u16 reserved0; 2297 u16 reserved1;
2075#endif 2298#endif
2076 u32 reserved1; 2299 u32 reserved2;
2077}; 2300};
2078 2301
2079struct demo_struct { 2302
2303/*
2304 * per-port SAFC demo variables
2305 */
2306struct cmng_flags_per_port {
2080 u8 con_number[NUM_OF_PROTOCOLS]; 2307 u8 con_number[NUM_OF_PROTOCOLS];
2081#if defined(__BIG_ENDIAN) 2308#if defined(__BIG_ENDIAN)
2082 u8 reserved1;
2083 u8 fairness_enable; 2309 u8 fairness_enable;
2084 u8 rate_shaping_enable; 2310 u8 rate_shaping_enable;
2085 u8 cmng_enable; 2311 u8 cmng_protocol_enable;
2312 u8 cmng_vn_enable;
2086#elif defined(__LITTLE_ENDIAN) 2313#elif defined(__LITTLE_ENDIAN)
2087 u8 cmng_enable; 2314 u8 cmng_vn_enable;
2315 u8 cmng_protocol_enable;
2088 u8 rate_shaping_enable; 2316 u8 rate_shaping_enable;
2089 u8 fairness_enable; 2317 u8 fairness_enable;
2090 u8 reserved1;
2091#endif 2318#endif
2092}; 2319};
2093 2320
2094struct cmng_struct { 2321
2095 struct rate_shaping_vars rs_vars; 2322/*
2096 struct fairness_vars fair_vars; 2323 * per-port rate shaping variables
2097 struct safc_struct safc_vars; 2324 */
2098 struct demo_struct demo_vars; 2325struct rate_shaping_vars_per_port {
2326 u32 rs_periodic_timeout;
2327 u32 rs_threshold;
2328};
2329
2330
2331/*
2332 * per-port fairness variables
2333 */
2334struct fairness_vars_per_port {
2335 u32 upper_bound;
2336 u32 fair_threshold;
2337 u32 fairness_timeout;
2338};
2339
2340
2341/*
2342 * per-port SAFC variables
2343 */
2344struct safc_struct_per_port {
2345#if defined(__BIG_ENDIAN)
2346 u16 __reserved0;
2347 u8 cur_cos_types;
2348 u8 safc_timeout_usec;
2349#elif defined(__LITTLE_ENDIAN)
2350 u8 safc_timeout_usec;
2351 u8 cur_cos_types;
2352 u16 __reserved0;
2353#endif
2354 u8 cos_to_protocol[MAX_COS_NUMBER];
2099}; 2355};
2100 2356
2101 2357
2102struct cos_to_protocol { 2358/*
2103 u8 mask[MAX_COS_NUMBER]; 2359 * Per-port congestion management variables
2360 */
2361struct cmng_struct_per_port {
2362 struct rate_shaping_vars_per_port rs_vars;
2363 struct fairness_vars_per_port fair_vars;
2364 struct safc_struct_per_port safc_vars;
2365 struct cmng_flags_per_port flags;
2104}; 2366};
2105 2367
2106 2368
@@ -2162,6 +2424,16 @@ struct eth_stats_query {
2162 2424
2163 2425
2164/* 2426/*
2427 * per-vnic fairness variables
2428 */
2429struct fairness_vars_per_vn {
2430 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2431 u32 vn_credit_delta;
2432 u32 __reserved0;
2433};
2434
2435
2436/*
2165 * FW version stored in the Xstorm RAM 2437 * FW version stored in the Xstorm RAM
2166 */ 2438 */
2167struct fw_version { 2439struct fw_version {
@@ -2179,8 +2451,10 @@ struct fw_version {
2179#define FW_VERSION_OPTIMIZED_SHIFT 0 2451#define FW_VERSION_OPTIMIZED_SHIFT 0
2180#define FW_VERSION_BIG_ENDIEN (0x1<<1) 2452#define FW_VERSION_BIG_ENDIEN (0x1<<1)
2181#define FW_VERSION_BIG_ENDIEN_SHIFT 1 2453#define FW_VERSION_BIG_ENDIEN_SHIFT 1
2182#define __FW_VERSION_RESERVED (0x3FFFFFFF<<2) 2454#define FW_VERSION_CHIP_VERSION (0x3<<2)
2183#define __FW_VERSION_RESERVED_SHIFT 2 2455#define FW_VERSION_CHIP_VERSION_SHIFT 2
2456#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2457#define __FW_VERSION_RESERVED_SHIFT 4
2184}; 2458};
2185 2459
2186 2460
@@ -2188,15 +2462,9 @@ struct fw_version {
2188 * FW version stored in first line of pram 2462 * FW version stored in first line of pram
2189 */ 2463 */
2190struct pram_fw_version { 2464struct pram_fw_version {
2191#if defined(__BIG_ENDIAN)
2192 u16 patch;
2193 u8 primary;
2194 u8 client;
2195#elif defined(__LITTLE_ENDIAN)
2196 u8 client; 2465 u8 client;
2197 u8 primary; 2466 u8 primary;
2198 u16 patch; 2467 u16 patch;
2199#endif
2200 u8 flags; 2468 u8 flags;
2201#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 2469#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2202#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 2470#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
@@ -2204,8 +2472,34 @@ struct pram_fw_version {
2204#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 2472#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2205#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 2473#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2206#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 2474#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2207#define __PRAM_FW_VERSION_RESERVED0 (0xF<<4) 2475#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2208#define __PRAM_FW_VERSION_RESERVED0_SHIFT 4 2476#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2477#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2478#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2479};
2480
2481
2482/*
2483 * a single rate shaping counter. can be used as protocol or vnic counter
2484 */
2485struct rate_shaping_counter {
2486 u32 quota;
2487#if defined(__BIG_ENDIAN)
2488 u16 __reserved0;
2489 u16 rate;
2490#elif defined(__LITTLE_ENDIAN)
2491 u16 rate;
2492 u16 __reserved0;
2493#endif
2494};
2495
2496
2497/*
2498 * per-vnic rate shaping variables
2499 */
2500struct rate_shaping_vars_per_vn {
2501 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2502 struct rate_shaping_counter vn_counter;
2209}; 2503};
2210 2504
2211 2505