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authorYaniv Rosner <yaniv.rosner@broadcom.com>2010-09-01 05:51:25 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-01 13:44:33 -0400
commitac4d944910d4d4e9cc520f304f2fa2eb54e9677c (patch)
treeebd3e56561ed273cf156545105426b72d7a607b1 /drivers/net/bnx2x
parent54c2fb785965a666a3e79dda16896801dfcf34e9 (diff)
bnx2x: Change BCM848xx configuration according to IEEE
Change BCM848xx behavior to fit IEEE such that setting 10Mb/100Mb will use force speed, and setting 1Gb/10Gb will use auto-negotiation with the specific speed advertised Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c288
-rw-r--r--drivers/net/bnx2x/bnx2x_reg.h3
2 files changed, 127 insertions, 164 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index cbacf8a7c65f..7a8df7a2f4da 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -4354,197 +4354,159 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4354 } 4354 }
4355 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 4355 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4356 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 4356 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
4357 {
4357 /* This phy uses the NIG latch mechanism since link 4358 /* This phy uses the NIG latch mechanism since link
4358 indication arrives through its LED4 and not via 4359 indication arrives through its LED4 and not via
4359 its LASI signal, so we get steady signal 4360 its LASI signal, so we get steady signal
4360 instead of clear on read */ 4361 instead of clear on read */
4362 u16 autoneg_val, an_1000_val, an_10_100_val;
4361 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 4363 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4362 1 << NIG_LATCH_BC_ENABLE_MI_INT); 4364 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4363 4365
4364 bnx2x_cl45_write(bp, params->port, 4366 bnx2x_cl45_write(bp, params->port,
4365 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 4367 ext_phy_type,
4366 ext_phy_addr, 4368 ext_phy_addr,
4367 MDIO_PMA_DEVAD, 4369 MDIO_PMA_DEVAD,
4368 MDIO_PMA_REG_CTRL, 0x0000); 4370 MDIO_PMA_REG_CTRL, 0x0000);
4369 4371
4370 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); 4372 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4371 if (params->req_line_speed == SPEED_AUTO_NEG) {
4372 4373
4373 u16 autoneg_val, an_1000_val, an_10_100_val; 4374 bnx2x_cl45_read(bp, params->port,
4374 /* set 1000 speed advertisement */ 4375 ext_phy_type,
4375 bnx2x_cl45_read(bp, params->port, 4376 ext_phy_addr,
4376 ext_phy_type, 4377 MDIO_AN_DEVAD,
4377 ext_phy_addr, 4378 MDIO_AN_REG_8481_1000T_CTRL,
4378 MDIO_AN_DEVAD, 4379 &an_1000_val);
4379 MDIO_AN_REG_8481_1000T_CTRL, 4380 bnx2x_ext_phy_set_pause(params, vars);
4380 &an_1000_val); 4381 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4381 4382 ext_phy_addr, MDIO_AN_DEVAD,
4382 if (params->speed_cap_mask & 4383 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4383 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) { 4384 &an_10_100_val);
4384 an_1000_val |= (1<<8); 4385 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4385 if (params->req_duplex == DUPLEX_FULL) 4386 ext_phy_addr, MDIO_AN_DEVAD,
4386 an_1000_val |= (1<<9); 4387 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4387 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 4388 &autoneg_val);
4388 } else 4389 /* Disable forced speed */
4389 an_1000_val &= ~((1<<8) | (1<<9)); 4390 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) |
4390 4391 (1<<13));
4391 bnx2x_cl45_write(bp, params->port, 4392 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
4392 ext_phy_type, 4393
4393 ext_phy_addr, 4394 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
4394 MDIO_AN_DEVAD, 4395 (params->speed_cap_mask &
4395 MDIO_AN_REG_8481_1000T_CTRL, 4396 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4396 an_1000_val); 4397 (params->req_line_speed == SPEED_1000)) {
4397 4398 an_1000_val |= (1<<8);
4398 /* set 100 speed advertisement */ 4399 autoneg_val |= (1<<9 | 1<<12);
4399 bnx2x_cl45_read(bp, params->port, 4400 if (params->req_duplex == DUPLEX_FULL)
4400 ext_phy_type, 4401 an_1000_val |= (1<<9);
4401 ext_phy_addr, 4402 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4402 MDIO_AN_DEVAD, 4403 } else
4403 MDIO_AN_REG_8481_LEGACY_AN_ADV, 4404 an_1000_val &= ~((1<<8) | (1<<9));
4404 &an_10_100_val);
4405
4406 if (params->speed_cap_mask &
4407 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4408 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4409 an_10_100_val |= (1<<7);
4410 if (params->req_duplex == DUPLEX_FULL)
4411 an_10_100_val |= (1<<8);
4412 DP(NETIF_MSG_LINK,
4413 "Advertising 100M\n");
4414 } else
4415 an_10_100_val &= ~((1<<7) | (1<<8));
4416
4417 /* set 10 speed advertisement */
4418 if (params->speed_cap_mask &
4419 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4420 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4421 an_10_100_val |= (1<<5);
4422 if (params->req_duplex == DUPLEX_FULL)
4423 an_10_100_val |= (1<<6);
4424 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4425 }
4426 else
4427 an_10_100_val &= ~((1<<5) | (1<<6));
4428
4429 bnx2x_cl45_write(bp, params->port,
4430 ext_phy_type,
4431 ext_phy_addr,
4432 MDIO_AN_DEVAD,
4433 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4434 an_10_100_val);
4435
4436 bnx2x_cl45_read(bp, params->port,
4437 ext_phy_type,
4438 ext_phy_addr,
4439 MDIO_AN_DEVAD,
4440 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4441 &autoneg_val);
4442
4443 /* Disable forced speed */
4444 autoneg_val &= ~(1<<6|1<<13);
4445 4405
4446 /* Enable autoneg and restart autoneg 4406 bnx2x_cl45_write(bp, params->port,
4447 for legacy speeds */ 4407 ext_phy_type,
4448 autoneg_val |= (1<<9|1<<12); 4408 ext_phy_addr,
4409 MDIO_AN_DEVAD,
4410 MDIO_AN_REG_8481_1000T_CTRL,
4411 an_1000_val);
4412
4413 /* set 10 speed advertisement */
4414 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
4415 (params->speed_cap_mask &
4416 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4417 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
4418 an_10_100_val |= (1<<7);
4419 /*
4420 * Enable autoneg and restart autoneg for
4421 * legacy speeds
4422 */
4423 autoneg_val |= (1<<9 | 1<<12);
4449 4424
4450 if (params->req_duplex == DUPLEX_FULL) 4425 if (params->req_duplex == DUPLEX_FULL)
4451 autoneg_val |= (1<<8); 4426 an_10_100_val |= (1<<8);
4452 else 4427 DP(NETIF_MSG_LINK, "Advertising 100M\n");
4453 autoneg_val &= ~(1<<8); 4428 }
4429 /* set 10 speed advertisement */
4430 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
4431 (params->speed_cap_mask &
4432 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4433 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
4434 an_10_100_val |= (1<<5);
4435 autoneg_val |= (1<<9 | 1<<12);
4436 if (params->req_duplex == DUPLEX_FULL)
4437 an_10_100_val |= (1<<6);
4438 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4439 }
4454 4440
4441 /* Only 10/100 are allowed to work in FORCE mode */
4442 if (params->req_line_speed == SPEED_100) {
4443 autoneg_val |= (1<<13);
4444 /* Enabled AUTO-MDIX when autoneg is disabled */
4455 bnx2x_cl45_write(bp, params->port, 4445 bnx2x_cl45_write(bp, params->port,
4456 ext_phy_type, 4446 ext_phy_type,
4457 ext_phy_addr, 4447 ext_phy_addr,
4458 MDIO_AN_DEVAD, 4448 MDIO_AN_DEVAD,
4459 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 4449 MDIO_AN_REG_8481_AUX_CTRL,
4460 autoneg_val); 4450 (1<<15 | 1<<9 | 7<<0));
4461 4451 DP(NETIF_MSG_LINK, "Setting 100M force\n");
4462 if (params->speed_cap_mask & 4452 }
4463 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 4453 if (params->req_line_speed == SPEED_10) {
4464 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 4454 /* Enabled AUTO-MDIX when autoneg is disabled */
4465 /* Restart autoneg for 10G*/ 4455 bnx2x_cl45_write(bp, params->port,
4456 ext_phy_type,
4457 ext_phy_addr,
4458 MDIO_AN_DEVAD,
4459 MDIO_AN_REG_8481_AUX_CTRL,
4460 (1<<15 | 1<<9 | 7<<0));
4461 DP(NETIF_MSG_LINK, "Setting 10M force\n");
4462 }
4466 4463
4467 bnx2x_cl45_write(bp, params->port, 4464 bnx2x_cl45_write(bp, params->port,
4468 ext_phy_type, 4465 ext_phy_type,
4469 ext_phy_addr, 4466 ext_phy_addr,
4470 MDIO_AN_DEVAD, 4467 MDIO_AN_DEVAD,
4471 MDIO_AN_REG_CTRL, 0x3200); 4468 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4472 } 4469 an_10_100_val);
4473 } else {
4474 /* Force speed */
4475 u16 autoneg_ctrl, pma_ctrl;
4476 bnx2x_cl45_read(bp, params->port,
4477 ext_phy_type,
4478 ext_phy_addr,
4479 MDIO_AN_DEVAD,
4480 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4481 &autoneg_ctrl);
4482 4470
4483 /* Disable autoneg */ 4471 if (params->req_duplex == DUPLEX_FULL)
4484 autoneg_ctrl &= ~(1<<12); 4472 autoneg_val |= (1<<8);
4485 4473
4486 /* Set 1000 force */ 4474 bnx2x_cl45_write(bp, params->port,
4487 switch (params->req_line_speed) { 4475 ext_phy_type,
4488 case SPEED_10000: 4476 ext_phy_addr,
4489 DP(NETIF_MSG_LINK, 4477 MDIO_AN_DEVAD,
4490 "Unable to set 10G force !\n"); 4478 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4491 break; 4479 autoneg_val);
4492 case SPEED_1000:
4493 bnx2x_cl45_read(bp, params->port,
4494 ext_phy_type,
4495 ext_phy_addr,
4496 MDIO_PMA_DEVAD,
4497 MDIO_PMA_REG_CTRL,
4498 &pma_ctrl);
4499 autoneg_ctrl &= ~(1<<13);
4500 autoneg_ctrl |= (1<<6);
4501 pma_ctrl &= ~(1<<13);
4502 pma_ctrl |= (1<<6);
4503 DP(NETIF_MSG_LINK,
4504 "Setting 1000M force\n");
4505 bnx2x_cl45_write(bp, params->port,
4506 ext_phy_type,
4507 ext_phy_addr,
4508 MDIO_PMA_DEVAD,
4509 MDIO_PMA_REG_CTRL,
4510 pma_ctrl);
4511 break;
4512 case SPEED_100:
4513 autoneg_ctrl |= (1<<13);
4514 autoneg_ctrl &= ~(1<<6);
4515 DP(NETIF_MSG_LINK,
4516 "Setting 100M force\n");
4517 break;
4518 case SPEED_10:
4519 autoneg_ctrl &= ~(1<<13);
4520 autoneg_ctrl &= ~(1<<6);
4521 DP(NETIF_MSG_LINK,
4522 "Setting 10M force\n");
4523 break;
4524 }
4525 4480
4526 /* Duplex mode */ 4481 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
4527 if (params->req_duplex == DUPLEX_FULL) { 4482 (params->speed_cap_mask &
4528 autoneg_ctrl |= (1<<8); 4483 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4529 DP(NETIF_MSG_LINK, 4484 (params->req_line_speed == SPEED_10000)) {
4530 "Setting full duplex\n"); 4485 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4531 } else 4486 /* Restart autoneg for 10G*/
4532 autoneg_ctrl &= ~(1<<8);
4533 4487
4534 /* Update autoneg ctrl and pma ctrl */
4535 bnx2x_cl45_write(bp, params->port, 4488 bnx2x_cl45_write(bp, params->port,
4536 ext_phy_type, 4489 ext_phy_type,
4537 ext_phy_addr, 4490 ext_phy_addr,
4538 MDIO_AN_DEVAD, 4491 MDIO_AN_DEVAD,
4539 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 4492 MDIO_AN_REG_CTRL,
4540 autoneg_ctrl); 4493 0x3200);
4541 } 4494
4495 } else if (params->req_line_speed != SPEED_10 &&
4496 params->req_line_speed != SPEED_100)
4497 bnx2x_cl45_write(bp, params->port,
4498 ext_phy_type,
4499 ext_phy_addr,
4500 MDIO_AN_DEVAD,
4501 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
4502 1);
4542 4503
4543 /* Save spirom version */ 4504 /* Save spirom version */
4544 bnx2x_save_8481_spirom_version(bp, params->port, 4505 bnx2x_save_8481_spirom_version(bp, params->port,
4545 ext_phy_addr, 4506 ext_phy_addr,
4546 params->shmem_base); 4507 params->shmem_base);
4547 break; 4508 break;
4509 }
4548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 4510 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4549 DP(NETIF_MSG_LINK, 4511 DP(NETIF_MSG_LINK,
4550 "XGXS PHY Failure detected 0x%x\n", 4512 "XGXS PHY Failure detected 0x%x\n",
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index c82e261020e2..398961772bb5 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -5212,12 +5212,13 @@ Theotherbitsarereservedandshouldbezero*/
5212#define MDIO_AN_REG_8073_2_5G 0x8329 5212#define MDIO_AN_REG_8073_2_5G 0x8329
5213 5213
5214#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 5214#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
5215 5215#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
5216#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 5216#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
5217#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 5217#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
5218#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 5218#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
5219#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 5219#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
5220#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 5220#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
5221#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
5221#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 5222#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
5222 5223
5223#define IGU_FUNC_BASE 0x0400 5224#define IGU_FUNC_BASE 0x0400
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 15:04:17 -0500