diff options
author | Dmitry Kravkov <dmitry@broadcom.com> | 2010-10-05 23:28:26 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-10-06 17:10:37 -0400 |
commit | f2e0899f0f275cc3f5e9c9726178d7d0ac19b2db (patch) | |
tree | 436144046a751427bdd2e3fd284688582d2efe61 /drivers/net/bnx2x/bnx2x_stats.c | |
parent | 8fe23fbd94af5a4c117fd0eb2f1c3f492f79efe8 (diff) |
bnx2x: Add 57712 support
57712 HW supported with same set of features as for 57710/57711
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_stats.c')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_stats.c | 262 |
1 files changed, 125 insertions, 137 deletions
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c index 32b6b1033a3b..ad7aa55efb63 100644 --- a/drivers/net/bnx2x/bnx2x_stats.c +++ b/drivers/net/bnx2x/bnx2x_stats.c | |||
@@ -185,20 +185,12 @@ static void bnx2x_hw_stats_post(struct bnx2x *bp) | |||
185 | /* loader */ | 185 | /* loader */ |
186 | if (bp->executer_idx) { | 186 | if (bp->executer_idx) { |
187 | int loader_idx = PMF_DMAE_C(bp); | 187 | int loader_idx = PMF_DMAE_C(bp); |
188 | u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, | ||
189 | true, DMAE_COMP_GRC); | ||
190 | opcode = bnx2x_dmae_opcode_clr_src_reset(opcode); | ||
188 | 191 | ||
189 | memset(dmae, 0, sizeof(struct dmae_command)); | 192 | memset(dmae, 0, sizeof(struct dmae_command)); |
190 | 193 | dmae->opcode = opcode; | |
191 | dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | | ||
192 | DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE | | ||
193 | DMAE_CMD_DST_RESET | | ||
194 | #ifdef __BIG_ENDIAN | ||
195 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
196 | #else | ||
197 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
198 | #endif | ||
199 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : | ||
200 | DMAE_CMD_PORT_0) | | ||
201 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
202 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0])); | 194 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0])); |
203 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0])); | 195 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0])); |
204 | dmae->dst_addr_lo = (DMAE_REG_CMD_MEM + | 196 | dmae->dst_addr_lo = (DMAE_REG_CMD_MEM + |
@@ -257,19 +249,10 @@ static void bnx2x_stats_pmf_update(struct bnx2x *bp) | |||
257 | 249 | ||
258 | bp->executer_idx = 0; | 250 | bp->executer_idx = 0; |
259 | 251 | ||
260 | opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | | 252 | opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0); |
261 | DMAE_CMD_C_ENABLE | | ||
262 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
263 | #ifdef __BIG_ENDIAN | ||
264 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
265 | #else | ||
266 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
267 | #endif | ||
268 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
269 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
270 | 253 | ||
271 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 254 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
272 | dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC); | 255 | dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC); |
273 | dmae->src_addr_lo = bp->port.port_stx >> 2; | 256 | dmae->src_addr_lo = bp->port.port_stx >> 2; |
274 | dmae->src_addr_hi = 0; | 257 | dmae->src_addr_hi = 0; |
275 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); | 258 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); |
@@ -280,7 +263,7 @@ static void bnx2x_stats_pmf_update(struct bnx2x *bp) | |||
280 | dmae->comp_val = 1; | 263 | dmae->comp_val = 1; |
281 | 264 | ||
282 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 265 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
283 | dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI); | 266 | dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI); |
284 | dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX; | 267 | dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX; |
285 | dmae->src_addr_hi = 0; | 268 | dmae->src_addr_hi = 0; |
286 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) + | 269 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) + |
@@ -301,7 +284,6 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
301 | { | 284 | { |
302 | struct dmae_command *dmae; | 285 | struct dmae_command *dmae; |
303 | int port = BP_PORT(bp); | 286 | int port = BP_PORT(bp); |
304 | int vn = BP_E1HVN(bp); | ||
305 | u32 opcode; | 287 | u32 opcode; |
306 | int loader_idx = PMF_DMAE_C(bp); | 288 | int loader_idx = PMF_DMAE_C(bp); |
307 | u32 mac_addr; | 289 | u32 mac_addr; |
@@ -316,16 +298,8 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
316 | bp->executer_idx = 0; | 298 | bp->executer_idx = 0; |
317 | 299 | ||
318 | /* MCP */ | 300 | /* MCP */ |
319 | opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | | 301 | opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, |
320 | DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE | | 302 | true, DMAE_COMP_GRC); |
321 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
322 | #ifdef __BIG_ENDIAN | ||
323 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
324 | #else | ||
325 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
326 | #endif | ||
327 | (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
328 | (vn << DMAE_CMD_E1HVN_SHIFT)); | ||
329 | 303 | ||
330 | if (bp->port.port_stx) { | 304 | if (bp->port.port_stx) { |
331 | 305 | ||
@@ -356,16 +330,8 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
356 | } | 330 | } |
357 | 331 | ||
358 | /* MAC */ | 332 | /* MAC */ |
359 | opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | | 333 | opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, |
360 | DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE | | 334 | true, DMAE_COMP_GRC); |
361 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
362 | #ifdef __BIG_ENDIAN | ||
363 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
364 | #else | ||
365 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
366 | #endif | ||
367 | (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
368 | (vn << DMAE_CMD_E1HVN_SHIFT)); | ||
369 | 335 | ||
370 | if (bp->link_vars.mac_type == MAC_TYPE_BMAC) { | 336 | if (bp->link_vars.mac_type == MAC_TYPE_BMAC) { |
371 | 337 | ||
@@ -376,13 +342,21 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
376 | BIGMAC_REGISTER_TX_STAT_GTBYT */ | 342 | BIGMAC_REGISTER_TX_STAT_GTBYT */ |
377 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 343 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
378 | dmae->opcode = opcode; | 344 | dmae->opcode = opcode; |
379 | dmae->src_addr_lo = (mac_addr + | 345 | if (CHIP_IS_E1x(bp)) { |
346 | dmae->src_addr_lo = (mac_addr + | ||
380 | BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2; | 347 | BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2; |
348 | dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT - | ||
349 | BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2; | ||
350 | } else { | ||
351 | dmae->src_addr_lo = (mac_addr + | ||
352 | BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2; | ||
353 | dmae->len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT - | ||
354 | BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2; | ||
355 | } | ||
356 | |||
381 | dmae->src_addr_hi = 0; | 357 | dmae->src_addr_hi = 0; |
382 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats)); | 358 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats)); |
383 | dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats)); | 359 | dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats)); |
384 | dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT - | ||
385 | BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2; | ||
386 | dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; | 360 | dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; |
387 | dmae->comp_addr_hi = 0; | 361 | dmae->comp_addr_hi = 0; |
388 | dmae->comp_val = 1; | 362 | dmae->comp_val = 1; |
@@ -391,15 +365,31 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
391 | BIGMAC_REGISTER_RX_STAT_GRIPJ */ | 365 | BIGMAC_REGISTER_RX_STAT_GRIPJ */ |
392 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 366 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
393 | dmae->opcode = opcode; | 367 | dmae->opcode = opcode; |
394 | dmae->src_addr_lo = (mac_addr + | ||
395 | BIGMAC_REGISTER_RX_STAT_GR64) >> 2; | ||
396 | dmae->src_addr_hi = 0; | 368 | dmae->src_addr_hi = 0; |
397 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) + | 369 | if (CHIP_IS_E1x(bp)) { |
370 | dmae->src_addr_lo = (mac_addr + | ||
371 | BIGMAC_REGISTER_RX_STAT_GR64) >> 2; | ||
372 | dmae->dst_addr_lo = | ||
373 | U64_LO(bnx2x_sp_mapping(bp, mac_stats) + | ||
398 | offsetof(struct bmac1_stats, rx_stat_gr64_lo)); | 374 | offsetof(struct bmac1_stats, rx_stat_gr64_lo)); |
399 | dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) + | 375 | dmae->dst_addr_hi = |
376 | U64_HI(bnx2x_sp_mapping(bp, mac_stats) + | ||
400 | offsetof(struct bmac1_stats, rx_stat_gr64_lo)); | 377 | offsetof(struct bmac1_stats, rx_stat_gr64_lo)); |
401 | dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ - | 378 | dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ - |
402 | BIGMAC_REGISTER_RX_STAT_GR64) >> 2; | 379 | BIGMAC_REGISTER_RX_STAT_GR64) >> 2; |
380 | } else { | ||
381 | dmae->src_addr_lo = | ||
382 | (mac_addr + BIGMAC2_REGISTER_RX_STAT_GR64) >> 2; | ||
383 | dmae->dst_addr_lo = | ||
384 | U64_LO(bnx2x_sp_mapping(bp, mac_stats) + | ||
385 | offsetof(struct bmac2_stats, rx_stat_gr64_lo)); | ||
386 | dmae->dst_addr_hi = | ||
387 | U64_HI(bnx2x_sp_mapping(bp, mac_stats) + | ||
388 | offsetof(struct bmac2_stats, rx_stat_gr64_lo)); | ||
389 | dmae->len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ - | ||
390 | BIGMAC2_REGISTER_RX_STAT_GR64) >> 2; | ||
391 | } | ||
392 | |||
403 | dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; | 393 | dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; |
404 | dmae->comp_addr_hi = 0; | 394 | dmae->comp_addr_hi = 0; |
405 | dmae->comp_val = 1; | 395 | dmae->comp_val = 1; |
@@ -480,16 +470,8 @@ static void bnx2x_port_stats_init(struct bnx2x *bp) | |||
480 | dmae->comp_val = 1; | 470 | dmae->comp_val = 1; |
481 | 471 | ||
482 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 472 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
483 | dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | | 473 | dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, |
484 | DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | | 474 | true, DMAE_COMP_PCI); |
485 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
486 | #ifdef __BIG_ENDIAN | ||
487 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
488 | #else | ||
489 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
490 | #endif | ||
491 | (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
492 | (vn << DMAE_CMD_E1HVN_SHIFT)); | ||
493 | dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 : | 475 | dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 : |
494 | NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2; | 476 | NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2; |
495 | dmae->src_addr_hi = 0; | 477 | dmae->src_addr_hi = 0; |
@@ -519,16 +501,8 @@ static void bnx2x_func_stats_init(struct bnx2x *bp) | |||
519 | bp->executer_idx = 0; | 501 | bp->executer_idx = 0; |
520 | memset(dmae, 0, sizeof(struct dmae_command)); | 502 | memset(dmae, 0, sizeof(struct dmae_command)); |
521 | 503 | ||
522 | dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | | 504 | dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, |
523 | DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | | 505 | true, DMAE_COMP_PCI); |
524 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
525 | #ifdef __BIG_ENDIAN | ||
526 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
527 | #else | ||
528 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
529 | #endif | ||
530 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
531 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
532 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats)); | 506 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats)); |
533 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats)); | 507 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats)); |
534 | dmae->dst_addr_lo = bp->func_stx >> 2; | 508 | dmae->dst_addr_lo = bp->func_stx >> 2; |
@@ -568,7 +542,6 @@ static void bnx2x_stats_restart(struct bnx2x *bp) | |||
568 | 542 | ||
569 | static void bnx2x_bmac_stats_update(struct bnx2x *bp) | 543 | static void bnx2x_bmac_stats_update(struct bnx2x *bp) |
570 | { | 544 | { |
571 | struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats); | ||
572 | struct host_port_stats *pstats = bnx2x_sp(bp, port_stats); | 545 | struct host_port_stats *pstats = bnx2x_sp(bp, port_stats); |
573 | struct bnx2x_eth_stats *estats = &bp->eth_stats; | 546 | struct bnx2x_eth_stats *estats = &bp->eth_stats; |
574 | struct { | 547 | struct { |
@@ -576,35 +549,74 @@ static void bnx2x_bmac_stats_update(struct bnx2x *bp) | |||
576 | u32 hi; | 549 | u32 hi; |
577 | } diff; | 550 | } diff; |
578 | 551 | ||
579 | UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets); | 552 | if (CHIP_IS_E1x(bp)) { |
580 | UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors); | 553 | struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats); |
581 | UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts); | 554 | |
582 | UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); | 555 | /* the macros below will use "bmac1_stats" type */ |
583 | UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); | 556 | UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets); |
584 | UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); | 557 | UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors); |
585 | UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived); | 558 | UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts); |
586 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); | 559 | UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); |
587 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); | 560 | UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); |
588 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); | 561 | UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); |
589 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone); | 562 | UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived); |
590 | UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets); | 563 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); |
591 | UPDATE_STAT64(tx_stat_gt127, | 564 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); |
565 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); | ||
566 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone); | ||
567 | UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets); | ||
568 | UPDATE_STAT64(tx_stat_gt127, | ||
592 | tx_stat_etherstatspkts65octetsto127octets); | 569 | tx_stat_etherstatspkts65octetsto127octets); |
593 | UPDATE_STAT64(tx_stat_gt255, | 570 | UPDATE_STAT64(tx_stat_gt255, |
594 | tx_stat_etherstatspkts128octetsto255octets); | 571 | tx_stat_etherstatspkts128octetsto255octets); |
595 | UPDATE_STAT64(tx_stat_gt511, | 572 | UPDATE_STAT64(tx_stat_gt511, |
596 | tx_stat_etherstatspkts256octetsto511octets); | 573 | tx_stat_etherstatspkts256octetsto511octets); |
597 | UPDATE_STAT64(tx_stat_gt1023, | 574 | UPDATE_STAT64(tx_stat_gt1023, |
598 | tx_stat_etherstatspkts512octetsto1023octets); | 575 | tx_stat_etherstatspkts512octetsto1023octets); |
599 | UPDATE_STAT64(tx_stat_gt1518, | 576 | UPDATE_STAT64(tx_stat_gt1518, |
600 | tx_stat_etherstatspkts1024octetsto1522octets); | 577 | tx_stat_etherstatspkts1024octetsto1522octets); |
601 | UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047); | 578 | UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047); |
602 | UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095); | 579 | UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095); |
603 | UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216); | 580 | UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216); |
604 | UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383); | 581 | UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383); |
605 | UPDATE_STAT64(tx_stat_gterr, | 582 | UPDATE_STAT64(tx_stat_gterr, |
606 | tx_stat_dot3statsinternalmactransmiterrors); | 583 | tx_stat_dot3statsinternalmactransmiterrors); |
607 | UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl); | 584 | UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl); |
585 | |||
586 | } else { | ||
587 | struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats); | ||
588 | |||
589 | /* the macros below will use "bmac2_stats" type */ | ||
590 | UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets); | ||
591 | UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors); | ||
592 | UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts); | ||
593 | UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); | ||
594 | UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); | ||
595 | UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); | ||
596 | UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived); | ||
597 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); | ||
598 | UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); | ||
599 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); | ||
600 | UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone); | ||
601 | UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets); | ||
602 | UPDATE_STAT64(tx_stat_gt127, | ||
603 | tx_stat_etherstatspkts65octetsto127octets); | ||
604 | UPDATE_STAT64(tx_stat_gt255, | ||
605 | tx_stat_etherstatspkts128octetsto255octets); | ||
606 | UPDATE_STAT64(tx_stat_gt511, | ||
607 | tx_stat_etherstatspkts256octetsto511octets); | ||
608 | UPDATE_STAT64(tx_stat_gt1023, | ||
609 | tx_stat_etherstatspkts512octetsto1023octets); | ||
610 | UPDATE_STAT64(tx_stat_gt1518, | ||
611 | tx_stat_etherstatspkts1024octetsto1522octets); | ||
612 | UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047); | ||
613 | UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095); | ||
614 | UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216); | ||
615 | UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383); | ||
616 | UPDATE_STAT64(tx_stat_gterr, | ||
617 | tx_stat_dot3statsinternalmactransmiterrors); | ||
618 | UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl); | ||
619 | } | ||
608 | 620 | ||
609 | estats->pause_frames_received_hi = | 621 | estats->pause_frames_received_hi = |
610 | pstats->mac_stx[1].rx_stat_bmac_xpf_hi; | 622 | pstats->mac_stx[1].rx_stat_bmac_xpf_hi; |
@@ -1121,24 +1133,17 @@ static void bnx2x_port_stats_stop(struct bnx2x *bp) | |||
1121 | 1133 | ||
1122 | bp->executer_idx = 0; | 1134 | bp->executer_idx = 0; |
1123 | 1135 | ||
1124 | opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | | 1136 | opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0); |
1125 | DMAE_CMD_C_ENABLE | | ||
1126 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
1127 | #ifdef __BIG_ENDIAN | ||
1128 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
1129 | #else | ||
1130 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
1131 | #endif | ||
1132 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
1133 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
1134 | 1137 | ||
1135 | if (bp->port.port_stx) { | 1138 | if (bp->port.port_stx) { |
1136 | 1139 | ||
1137 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 1140 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
1138 | if (bp->func_stx) | 1141 | if (bp->func_stx) |
1139 | dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC); | 1142 | dmae->opcode = bnx2x_dmae_opcode_add_comp( |
1143 | opcode, DMAE_COMP_GRC); | ||
1140 | else | 1144 | else |
1141 | dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI); | 1145 | dmae->opcode = bnx2x_dmae_opcode_add_comp( |
1146 | opcode, DMAE_COMP_PCI); | ||
1142 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); | 1147 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); |
1143 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); | 1148 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); |
1144 | dmae->dst_addr_lo = bp->port.port_stx >> 2; | 1149 | dmae->dst_addr_lo = bp->port.port_stx >> 2; |
@@ -1162,7 +1167,8 @@ static void bnx2x_port_stats_stop(struct bnx2x *bp) | |||
1162 | if (bp->func_stx) { | 1167 | if (bp->func_stx) { |
1163 | 1168 | ||
1164 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 1169 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
1165 | dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI); | 1170 | dmae->opcode = |
1171 | bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI); | ||
1166 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats)); | 1172 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats)); |
1167 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats)); | 1173 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats)); |
1168 | dmae->dst_addr_lo = bp->func_stx >> 2; | 1174 | dmae->dst_addr_lo = bp->func_stx >> 2; |
@@ -1255,16 +1261,8 @@ static void bnx2x_port_stats_base_init(struct bnx2x *bp) | |||
1255 | bp->executer_idx = 0; | 1261 | bp->executer_idx = 0; |
1256 | 1262 | ||
1257 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); | 1263 | dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); |
1258 | dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | | 1264 | dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, |
1259 | DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | | 1265 | true, DMAE_COMP_PCI); |
1260 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
1261 | #ifdef __BIG_ENDIAN | ||
1262 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
1263 | #else | ||
1264 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
1265 | #endif | ||
1266 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
1267 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
1268 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); | 1266 | dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); |
1269 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); | 1267 | dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); |
1270 | dmae->dst_addr_lo = bp->port.port_stx >> 2; | 1268 | dmae->dst_addr_lo = bp->port.port_stx >> 2; |
@@ -1282,8 +1280,6 @@ static void bnx2x_port_stats_base_init(struct bnx2x *bp) | |||
1282 | static void bnx2x_func_stats_base_init(struct bnx2x *bp) | 1280 | static void bnx2x_func_stats_base_init(struct bnx2x *bp) |
1283 | { | 1281 | { |
1284 | int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX; | 1282 | int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX; |
1285 | int port = BP_PORT(bp); | ||
1286 | int func; | ||
1287 | u32 func_stx; | 1283 | u32 func_stx; |
1288 | 1284 | ||
1289 | /* sanity */ | 1285 | /* sanity */ |
@@ -1296,9 +1292,9 @@ static void bnx2x_func_stats_base_init(struct bnx2x *bp) | |||
1296 | func_stx = bp->func_stx; | 1292 | func_stx = bp->func_stx; |
1297 | 1293 | ||
1298 | for (vn = VN_0; vn < vn_max; vn++) { | 1294 | for (vn = VN_0; vn < vn_max; vn++) { |
1299 | func = 2*vn + port; | 1295 | int mb_idx = !CHIP_IS_E2(bp) ? 2*vn + BP_PORT(bp) : vn; |
1300 | 1296 | ||
1301 | bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param); | 1297 | bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param); |
1302 | bnx2x_func_stats_init(bp); | 1298 | bnx2x_func_stats_init(bp); |
1303 | bnx2x_hw_stats_post(bp); | 1299 | bnx2x_hw_stats_post(bp); |
1304 | bnx2x_stats_comp(bp); | 1300 | bnx2x_stats_comp(bp); |
@@ -1322,16 +1318,8 @@ static void bnx2x_func_stats_base_update(struct bnx2x *bp) | |||
1322 | bp->executer_idx = 0; | 1318 | bp->executer_idx = 0; |
1323 | memset(dmae, 0, sizeof(struct dmae_command)); | 1319 | memset(dmae, 0, sizeof(struct dmae_command)); |
1324 | 1320 | ||
1325 | dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | | 1321 | dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, |
1326 | DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE | | 1322 | true, DMAE_COMP_PCI); |
1327 | DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET | | ||
1328 | #ifdef __BIG_ENDIAN | ||
1329 | DMAE_CMD_ENDIANITY_B_DW_SWAP | | ||
1330 | #else | ||
1331 | DMAE_CMD_ENDIANITY_DW_SWAP | | ||
1332 | #endif | ||
1333 | (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | | ||
1334 | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); | ||
1335 | dmae->src_addr_lo = bp->func_stx >> 2; | 1323 | dmae->src_addr_lo = bp->func_stx >> 2; |
1336 | dmae->src_addr_hi = 0; | 1324 | dmae->src_addr_hi = 0; |
1337 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base)); | 1325 | dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base)); |
@@ -1349,7 +1337,7 @@ static void bnx2x_func_stats_base_update(struct bnx2x *bp) | |||
1349 | void bnx2x_stats_init(struct bnx2x *bp) | 1337 | void bnx2x_stats_init(struct bnx2x *bp) |
1350 | { | 1338 | { |
1351 | int port = BP_PORT(bp); | 1339 | int port = BP_PORT(bp); |
1352 | int func = BP_FUNC(bp); | 1340 | int mb_idx = BP_FW_MB_IDX(bp); |
1353 | int i; | 1341 | int i; |
1354 | 1342 | ||
1355 | bp->stats_pending = 0; | 1343 | bp->stats_pending = 0; |
@@ -1359,7 +1347,7 @@ void bnx2x_stats_init(struct bnx2x *bp) | |||
1359 | /* port and func stats for management */ | 1347 | /* port and func stats for management */ |
1360 | if (!BP_NOMCP(bp)) { | 1348 | if (!BP_NOMCP(bp)) { |
1361 | bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx); | 1349 | bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx); |
1362 | bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param); | 1350 | bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param); |
1363 | 1351 | ||
1364 | } else { | 1352 | } else { |
1365 | bp->port.port_stx = 0; | 1353 | bp->port.port_stx = 0; |