aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/bnx2x/bnx2x_main.c
diff options
context:
space:
mode:
authorYaniv Rosner <yaniv.rosner@broadcom.com>2010-09-07 07:40:54 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-07 16:13:36 -0400
commitb7737c9be9d3e894d1a4375c52f5f47789475f26 (patch)
treebbc561c7f7104aa14638503948fbcb3ad6546225 /drivers/net/bnx2x/bnx2x_main.c
parente10bc84d0e96adff7569161e7d825074a119be36 (diff)
bnx2x: Split PHY functions
Move the code into PHY oriented functions, and for that a new structure is defines for each PHY which contain PHY properties and its own functions. This also enables to encapsulate all PHY specific operations into the PHY functions. During initialization, the PHYs will be probed by the "bnx2x_phy_probe" function to detect which PHYs exist on-board, and configure them accordingly. Note that the ext_phy_reset implementation was incorporated in the ext_phy_init since it is actually part of the PHY initialization procedure. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c270
1 files changed, 36 insertions, 234 deletions
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 174ed8b4587e..1ecff37bab18 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -1960,12 +1960,16 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
1960static inline void bnx2x_fan_failure(struct bnx2x *bp) 1960static inline void bnx2x_fan_failure(struct bnx2x *bp)
1961{ 1961{
1962 int port = BP_PORT(bp); 1962 int port = BP_PORT(bp);
1963 1963 u32 ext_phy_config;
1964 /* mark the failure */ 1964 /* mark the failure */
1965 bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 1965 ext_phy_config =
1966 bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 1966 SHMEM_RD(bp,
1967 dev_info.port_hw_config[port].external_phy_config);
1968
1969 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
1970 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
1967 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 1971 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
1968 bp->link_params.ext_phy_config); 1972 ext_phy_config);
1969 1973
1970 /* log the failure */ 1974 /* log the failure */
1971 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 1975 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
@@ -1991,7 +1995,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
1991 BNX2X_ERR("SPIO5 hw attention\n"); 1995 BNX2X_ERR("SPIO5 hw attention\n");
1992 1996
1993 /* Fan failure attention */ 1997 /* Fan failure attention */
1994 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { 1998 switch (bp->link_params.phy[EXT_PHY1].type) {
1995 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 1999 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1996 /* Low power mode is controlled by GPIO 2 */ 2000 /* Low power mode is controlled by GPIO 2 */
1997 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 2001 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
@@ -4140,7 +4144,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
4140 return -EBUSY; 4144 return -EBUSY;
4141 } 4145 }
4142 4146
4143 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { 4147 switch (bp->link_params.phy[EXT_PHY1].type) {
4144 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 4148 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 4149 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4146 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 4150 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
@@ -4299,7 +4303,7 @@ static int bnx2x_init_port(struct bnx2x *bp)
4299 bnx2x_init_block(bp, MCP_BLOCK, init_stage); 4303 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
4300 bnx2x_init_block(bp, DMAE_BLOCK, init_stage); 4304 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
4301 4305
4302 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { 4306 switch (bp->link_params.phy[EXT_PHY1].type) {
4303 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 4307 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4304 { 4308 {
4305 u32 swap_val, swap_override, aeu_gpio_mask, offset; 4309 u32 swap_val, swap_override, aeu_gpio_mask, offset;
@@ -4480,7 +4484,7 @@ static int bnx2x_init_func(struct bnx2x *bp)
4480 /* Reset PCIE errors for debug */ 4484 /* Reset PCIE errors for debug */
4481 REG_WR(bp, 0x2114, 0xffffffff); 4485 REG_WR(bp, 0x2114, 0xffffffff);
4482 REG_WR(bp, 0x2120, 0xffffffff); 4486 REG_WR(bp, 0x2120, 0xffffffff);
4483 4487 bnx2x_phy_probe(&bp->link_params);
4484 return 0; 4488 return 0;
4485} 4489}
4486 4490
@@ -6065,194 +6069,32 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6065 u32 switch_cfg) 6069 u32 switch_cfg)
6066{ 6070{
6067 int port = BP_PORT(bp); 6071 int port = BP_PORT(bp);
6068 u32 ext_phy_type; 6072 bp->port.supported = 0;
6069 6073 switch (bp->link_params.num_phys) {
6070 switch (switch_cfg) { 6074 case 1:
6071 case SWITCH_CFG_1G: 6075 bp->port.supported = bp->link_params.phy[INT_PHY].supported;
6072 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6073
6074 ext_phy_type =
6075 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6076 switch (ext_phy_type) {
6077 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6078 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6079 ext_phy_type);
6080
6081 bp->port.supported |= (SUPPORTED_10baseT_Half |
6082 SUPPORTED_10baseT_Full |
6083 SUPPORTED_100baseT_Half |
6084 SUPPORTED_100baseT_Full |
6085 SUPPORTED_1000baseT_Full |
6086 SUPPORTED_2500baseX_Full |
6087 SUPPORTED_TP |
6088 SUPPORTED_FIBRE |
6089 SUPPORTED_Autoneg |
6090 SUPPORTED_Pause |
6091 SUPPORTED_Asym_Pause);
6092 break; 6076 break;
6093 6077 case 2:
6094 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: 6078 bp->port.supported = bp->link_params.phy[EXT_PHY1].supported;
6095 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
6096 ext_phy_type);
6097
6098 bp->port.supported |= (SUPPORTED_10baseT_Half |
6099 SUPPORTED_10baseT_Full |
6100 SUPPORTED_100baseT_Half |
6101 SUPPORTED_100baseT_Full |
6102 SUPPORTED_1000baseT_Full |
6103 SUPPORTED_TP |
6104 SUPPORTED_FIBRE |
6105 SUPPORTED_Autoneg |
6106 SUPPORTED_Pause |
6107 SUPPORTED_Asym_Pause);
6108 break; 6079 break;
6080 }
6109 6081
6110 default: 6082 if (!(bp->port.supported)) {
6111 BNX2X_ERR("NVRAM config error. " 6083 BNX2X_ERR("NVRAM config error. BAD phy config."
6112 "BAD SerDes ext_phy_config 0x%x\n", 6084 "PHY1 config 0x%x\n",
6113 bp->link_params.ext_phy_config); 6085 SHMEM_RD(bp,
6086 dev_info.port_hw_config[port].external_phy_config));
6114 return; 6087 return;
6115 } 6088 }
6116 6089
6090 switch (switch_cfg) {
6091 case SWITCH_CFG_1G:
6117 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + 6092 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
6118 port*0x10); 6093 port*0x10);
6119 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 6094 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
6120 break; 6095 break;
6121 6096
6122 case SWITCH_CFG_10G: 6097 case SWITCH_CFG_10G:
6123 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
6124
6125 ext_phy_type =
6126 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6127 switch (ext_phy_type) {
6128 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6129 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6130 ext_phy_type);
6131
6132 bp->port.supported |= (SUPPORTED_10baseT_Half |
6133 SUPPORTED_10baseT_Full |
6134 SUPPORTED_100baseT_Half |
6135 SUPPORTED_100baseT_Full |
6136 SUPPORTED_1000baseT_Full |
6137 SUPPORTED_2500baseX_Full |
6138 SUPPORTED_10000baseT_Full |
6139 SUPPORTED_TP |
6140 SUPPORTED_FIBRE |
6141 SUPPORTED_Autoneg |
6142 SUPPORTED_Pause |
6143 SUPPORTED_Asym_Pause);
6144 break;
6145
6146 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6147 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
6148 ext_phy_type);
6149
6150 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6151 SUPPORTED_1000baseT_Full |
6152 SUPPORTED_FIBRE |
6153 SUPPORTED_Autoneg |
6154 SUPPORTED_Pause |
6155 SUPPORTED_Asym_Pause);
6156 break;
6157
6158 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6159 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
6160 ext_phy_type);
6161
6162 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6163 SUPPORTED_2500baseX_Full |
6164 SUPPORTED_1000baseT_Full |
6165 SUPPORTED_FIBRE |
6166 SUPPORTED_Autoneg |
6167 SUPPORTED_Pause |
6168 SUPPORTED_Asym_Pause);
6169 break;
6170
6171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6172 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
6173 ext_phy_type);
6174
6175 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6176 SUPPORTED_FIBRE |
6177 SUPPORTED_Pause |
6178 SUPPORTED_Asym_Pause);
6179 break;
6180
6181 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6182 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
6183 ext_phy_type);
6184
6185 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6186 SUPPORTED_1000baseT_Full |
6187 SUPPORTED_FIBRE |
6188 SUPPORTED_Pause |
6189 SUPPORTED_Asym_Pause);
6190 break;
6191
6192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6193 BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
6194 ext_phy_type);
6195
6196 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6197 SUPPORTED_1000baseT_Full |
6198 SUPPORTED_Autoneg |
6199 SUPPORTED_FIBRE |
6200 SUPPORTED_Pause |
6201 SUPPORTED_Asym_Pause);
6202 break;
6203
6204 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6205 BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
6206 ext_phy_type);
6207
6208 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6209 SUPPORTED_1000baseT_Full |
6210 SUPPORTED_Autoneg |
6211 SUPPORTED_FIBRE |
6212 SUPPORTED_Pause |
6213 SUPPORTED_Asym_Pause);
6214 break;
6215
6216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6217 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
6218 ext_phy_type);
6219
6220 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6221 SUPPORTED_TP |
6222 SUPPORTED_Autoneg |
6223 SUPPORTED_Pause |
6224 SUPPORTED_Asym_Pause);
6225 break;
6226
6227 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6228 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6229 BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM848xx)\n",
6230 ext_phy_type);
6231
6232 bp->port.supported |= (SUPPORTED_10baseT_Half |
6233 SUPPORTED_10baseT_Full |
6234 SUPPORTED_100baseT_Half |
6235 SUPPORTED_100baseT_Full |
6236 SUPPORTED_1000baseT_Full |
6237 SUPPORTED_10000baseT_Full |
6238 SUPPORTED_TP |
6239 SUPPORTED_Autoneg |
6240 SUPPORTED_Pause |
6241 SUPPORTED_Asym_Pause);
6242 break;
6243
6244 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6245 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
6246 bp->link_params.ext_phy_config);
6247 break;
6248
6249 default:
6250 BNX2X_ERR("NVRAM config error. "
6251 "BAD XGXS ext_phy_config 0x%x\n",
6252 bp->link_params.ext_phy_config);
6253 return;
6254 }
6255
6256 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + 6098 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
6257 port*0x18); 6099 port*0x18);
6258 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 6100 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
@@ -6264,8 +6106,6 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6264 bp->port.link_config); 6106 bp->port.link_config);
6265 return; 6107 return;
6266 } 6108 }
6267 bp->link_params.phy_addr = bp->port.phy_addr;
6268
6269 /* mask what we support according to speed_cap_mask */ 6109 /* mask what we support according to speed_cap_mask */
6270 if (!(bp->link_params.speed_cap_mask & 6110 if (!(bp->link_params.speed_cap_mask &
6271 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 6111 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
@@ -6309,25 +6149,10 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
6309 bp->link_params.req_line_speed = SPEED_AUTO_NEG; 6149 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
6310 bp->port.advertising = bp->port.supported; 6150 bp->port.advertising = bp->port.supported;
6311 } else { 6151 } else {
6312 u32 ext_phy_type =
6313 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6314
6315 if ((ext_phy_type ==
6316 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
6317 (ext_phy_type ==
6318 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
6319 /* force 10G, no AN */ 6152 /* force 10G, no AN */
6320 bp->link_params.req_line_speed = SPEED_10000; 6153 bp->link_params.req_line_speed = SPEED_10000;
6321 bp->port.advertising = 6154 bp->port.advertising = (ADVERTISED_10000baseT_Full |
6322 (ADVERTISED_10000baseT_Full |
6323 ADVERTISED_FIBRE); 6155 ADVERTISED_FIBRE);
6324 break;
6325 }
6326 BNX2X_ERR("NVRAM config error. "
6327 "Invalid link_config 0x%x"
6328 " Autoneg not supported\n",
6329 bp->port.link_config);
6330 return;
6331 } 6156 }
6332 break; 6157 break;
6333 6158
@@ -6475,27 +6300,13 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6475 int port = BP_PORT(bp); 6300 int port = BP_PORT(bp);
6476 u32 val, val2; 6301 u32 val, val2;
6477 u32 config; 6302 u32 config;
6478 u16 i; 6303 u32 ext_phy_type, ext_phy_config;;
6479 u32 ext_phy_type;
6480 6304
6481 bp->link_params.bp = bp; 6305 bp->link_params.bp = bp;
6482 bp->link_params.port = port; 6306 bp->link_params.port = port;
6483 6307
6484 bp->link_params.lane_config = 6308 bp->link_params.lane_config =
6485 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 6309 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
6486 bp->link_params.ext_phy_config =
6487 SHMEM_RD(bp,
6488 dev_info.port_hw_config[port].external_phy_config);
6489 /* BCM8727_NOC => BCM8727 no over current */
6490 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
6491 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
6492 bp->link_params.ext_phy_config &=
6493 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6494 bp->link_params.ext_phy_config |=
6495 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
6496 bp->link_params.feature_config_flags |=
6497 FEATURE_CONFIG_BCM8727_NOC;
6498 }
6499 6310
6500 bp->link_params.speed_cap_mask = 6311 bp->link_params.speed_cap_mask =
6501 SHMEM_RD(bp, 6312 SHMEM_RD(bp,
@@ -6504,18 +6315,6 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6504 bp->port.link_config = 6315 bp->port.link_config =
6505 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 6316 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
6506 6317
6507 /* Get the 4 lanes xgxs config rx and tx */
6508 for (i = 0; i < 2; i++) {
6509 val = SHMEM_RD(bp,
6510 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
6511 bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
6512 bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
6513
6514 val = SHMEM_RD(bp,
6515 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
6516 bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
6517 bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
6518 }
6519 6318
6520 /* If the device is capable of WoL, set the default state according 6319 /* If the device is capable of WoL, set the default state according
6521 * to the HW 6320 * to the HW
@@ -6524,14 +6323,14 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6524 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 6323 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
6525 (config & PORT_FEATURE_WOL_ENABLED)); 6324 (config & PORT_FEATURE_WOL_ENABLED));
6526 6325
6527 BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x" 6326 BNX2X_DEV_INFO("lane_config 0x%08x"
6528 " speed_cap_mask 0x%08x link_config 0x%08x\n", 6327 " speed_cap_mask 0x%08x link_config 0x%08x\n",
6529 bp->link_params.lane_config, 6328 bp->link_params.lane_config,
6530 bp->link_params.ext_phy_config,
6531 bp->link_params.speed_cap_mask, bp->port.link_config); 6329 bp->link_params.speed_cap_mask, bp->port.link_config);
6532 6330
6533 bp->link_params.switch_cfg |= (bp->port.link_config & 6331 bp->link_params.switch_cfg |= (bp->port.link_config &
6534 PORT_FEATURE_CONNECTED_SWITCH_MASK); 6332 PORT_FEATURE_CONNECTED_SWITCH_MASK);
6333 bnx2x_phy_probe(&bp->link_params);
6535 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 6334 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
6536 6335
6537 bnx2x_link_settings_requested(bp); 6336 bnx2x_link_settings_requested(bp);
@@ -6540,14 +6339,17 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6540 * If connected directly, work with the internal PHY, otherwise, work 6339 * If connected directly, work with the internal PHY, otherwise, work
6541 * with the external PHY 6340 * with the external PHY
6542 */ 6341 */
6543 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 6342 ext_phy_config =
6343 SHMEM_RD(bp,
6344 dev_info.port_hw_config[port].external_phy_config);
6345 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6544 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6346 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6545 bp->mdio.prtad = bp->link_params.phy_addr; 6347 bp->mdio.prtad = bp->port.phy_addr;
6546 6348
6547 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 6349 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
6548 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 6350 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
6549 bp->mdio.prtad = 6351 bp->mdio.prtad =
6550 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config); 6352 XGXS_EXT_PHY_ADDR(ext_phy_config);
6551 6353
6552 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 6354 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
6553 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 6355 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 01:22:54 -0500