bnx2x: Parity errors recovery for 578xx

Fix the parity errors recovery flow for 578xx:
    - Add a separate column for the 578xx in the parity mask
      registers DB.
    - Fix the bnx2x_process_kill_chip_reset() to handle the blocks
      newly introduced in the 578xx.

Cover ATC and PGLUE_B blocks for 57712 and 578xx.

Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 94 insertions, 25 deletions

diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 6ee9fc8d8e77..e1ec1a302474 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -3817,6 +3817,10 @@ static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
                                 if (print)
                                         _print_next_block(par_num++, "USDM");
                                 break;
+                        case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
+                                if (print)
+                                        _print_next_block(par_num++, "UCM");
+                                break;
                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
                                 if (print)
                                         _print_next_block(par_num++, "USEMI");
@@ -3829,6 +3833,10 @@ static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
                                 if (print)
                                         _print_next_block(par_num++, "CSDM");
                                 break;
+                        case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
+                                if (print)
+                                        _print_next_block(par_num++, "CCM");
+                                break;
                         }
 
                         /* Clear the bit */
@@ -3933,32 +3941,67 @@ static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
         return par_num;
 }
 
+static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
+                                                  bool print)
+{
+        int i = 0;
+        u32 cur_bit = 0;
+        for (i = 0; sig; i++) {
+                cur_bit = ((u32)0x1 << i);
+                if (sig & cur_bit) {
+                        switch (cur_bit) {
+                        case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
+                                if (print)
+                                        _print_next_block(par_num++, "PGLUE_B");
+                                break;
+                        case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
+                                if (print)
+                                        _print_next_block(par_num++, "ATC");
+                                break;
+                        }
+
+                        /* Clear the bit */
+                        sig &= ~cur_bit;
+                }
+        }
+
+        return par_num;
+}
+
 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
-                                     u32 sig0, u32 sig1, u32 sig2, u32 sig3)
+                                     u32 *sig)
 {
-        if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
-            (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
+        if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
+            (sig[1] & HW_PRTY_ASSERT_SET_1) ||
+            (sig[2] & HW_PRTY_ASSERT_SET_2) ||
+            (sig[3] & HW_PRTY_ASSERT_SET_3) ||
+            (sig[4] & HW_PRTY_ASSERT_SET_4)) {
                 int par_num = 0;
                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
-                        "[0]:0x%08x [1]:0x%08x "
-                        "[2]:0x%08x [3]:0x%08x\n",
-                          sig0 & HW_PRTY_ASSERT_SET_0,
-                          sig1 & HW_PRTY_ASSERT_SET_1,
-                          sig2 & HW_PRTY_ASSERT_SET_2,
-                          sig3 & HW_PRTY_ASSERT_SET_3);
+                        "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
+                        "[4]:0x%08x\n",
+                          sig[0] & HW_PRTY_ASSERT_SET_0,
+                          sig[1] & HW_PRTY_ASSERT_SET_1,
+                          sig[2] & HW_PRTY_ASSERT_SET_2,
+                          sig[3] & HW_PRTY_ASSERT_SET_3,
+                          sig[4] & HW_PRTY_ASSERT_SET_4);
                 if (print)
                         netdev_err(bp->dev,
                                    "Parity errors detected in blocks: ");
                 par_num = bnx2x_check_blocks_with_parity0(
-                        sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
+                        sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
                 par_num = bnx2x_check_blocks_with_parity1(
-                        sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
+                        sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
                 par_num = bnx2x_check_blocks_with_parity2(
-                        sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
+                        sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
                 par_num = bnx2x_check_blocks_with_parity3(
-                        sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
+                        sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
+                par_num = bnx2x_check_blocks_with_parity4(
+                        sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
+
                 if (print)
                         pr_cont("\n");
+
                 return true;
         } else
                 return false;
@@ -3973,7 +4016,7 @@ static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
  */
 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
 {
-        struct attn_route attn;
+        struct attn_route attn = { {0} };
         int port = BP_PORT(bp);
 
         attn.sig[0] = REG_RD(bp,
@@ -3989,8 +4032,12 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
                              port*4);
 
-        return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
-                                 attn.sig[2], attn.sig[3]);
+        if (!CHIP_IS_E1x(bp))
+                attn.sig[4] = REG_RD(bp,
+                        MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
+                                     port*4);
+
+        return bnx2x_parity_attn(bp, global, print, attn.sig);
 }
 
 
@@ -7932,7 +7979,7 @@ static void bnx2x_pxp_prep(struct bnx2x *bp)
 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
 {
         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
-        u32 global_bits2;
+        u32 global_bits2, stay_reset2;
 
         /*
          * Bits that have to be set in reset_mask2 if we want to reset 'global'
@@ -7942,6 +7989,7 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
 
+        /* Don't reset the following blocks */
         not_reset_mask1 =
                 MISC_REGISTERS_RESET_REG_1_RST_HC |
                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
@@ -7955,19 +8003,35 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
-                MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
+                MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
+                MISC_REGISTERS_RESET_REG_2_RST_ATC |
+                MISC_REGISTERS_RESET_REG_2_PGLC;
 
+        /*
+         * Keep the following blocks in reset:
+         *  - all xxMACs are handled by the bnx2x_link code.
+         */
+        stay_reset2 =
+                MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
+                MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
+                MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
+                MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
+                MISC_REGISTERS_RESET_REG_2_UMAC0 |
+                MISC_REGISTERS_RESET_REG_2_UMAC1 |
+                MISC_REGISTERS_RESET_REG_2_XMAC |
+                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
+
+        /* Full reset masks according to the chip */
         reset_mask1 = 0xffffffff;
 
         if (CHIP_IS_E1(bp))
                 reset_mask2 = 0xffff;
-        else
+        else if (CHIP_IS_E1H(bp))
                 reset_mask2 = 0x1ffff;
-
-        if (CHIP_IS_E3(bp)) {
-                reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
-                reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
-        }
+        else if (CHIP_IS_E2(bp))
+                reset_mask2 = 0xfffff;
+        else /* CHIP_IS_E3 */
+                reset_mask2 = 0x3ffffff;
 
         /* Don't reset global blocks unless we need to */
         if (!global)
@@ -7996,7 +8060,12 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
         barrier();
         mmiowb();
 
-        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
+        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+               reset_mask2 & (~stay_reset2));
+
+        barrier();
+        mmiowb();
+
         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
         mmiowb();
 }