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authorYaniv Rosner <yaniv.rosner@broadcom.com>2010-09-07 07:40:50 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-07 16:11:53 -0400
commite10bc84d0e96adff7569161e7d825074a119be36 (patch)
tree7a0d1903277f01d0d0dbf41f44261ad413d913c9 /drivers/net/bnx2x/bnx2x_link.c
parentdb40980fcdb560d7992b0511df16cdd3f7e381f3 (diff)
bnx2x: Unify PHY attributes
Start building the infrastructure for dual media by adding new component of PHY which will be used all along the function. Modify function to work with this component instead of the link_params. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c2180
1 files changed, 831 insertions, 1349 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 8fce54cd6ba5..e6bc70ff8432 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -168,32 +168,33 @@
168/**********************************************************/ 168/**********************************************************/
169/* INTERFACE */ 169/* INTERFACE */
170/**********************************************************/ 170/**********************************************************/
171#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \ 171
172 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \ 172#define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
173 bnx2x_cl45_write(_bp, _phy, \
173 DEFAULT_PHY_DEV_ADDR, \ 174 DEFAULT_PHY_DEV_ADDR, \
174 (_bank + (_addr & 0xf)), \ 175 (_bank + (_addr & 0xf)), \
175 _val) 176 _val)
176 177
177#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \ 178#define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
178 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \ 179 bnx2x_cl45_read(_bp, _phy, \
179 DEFAULT_PHY_DEV_ADDR, \ 180 DEFAULT_PHY_DEV_ADDR, \
180 (_bank + (_addr & 0xf)), \ 181 (_bank + (_addr & 0xf)), \
181 _val) 182 _val)
182 183
183static void bnx2x_set_serdes_access(struct link_params *params) 184static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
184{ 185{
185 struct bnx2x *bp = params->bp; 186 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
186 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
187 187
188 /* Set Clause 22 */ 188 /* Set Clause 22 */
189 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1); 189 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
190 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 190 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
191 udelay(500); 191 udelay(500);
192 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 192 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
193 udelay(500); 193 udelay(500);
194 /* Set Clause 45 */ 194 /* Set Clause 45 */
195 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0); 195 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
196} 196}
197
197static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags) 198static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
198{ 199{
199 struct bnx2x *bp = params->bp; 200 struct bnx2x *bp = params->bp;
@@ -204,7 +205,7 @@ static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
204 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 205 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
205 DEFAULT_PHY_DEV_ADDR); 206 DEFAULT_PHY_DEV_ADDR);
206 } else { 207 } else {
207 bnx2x_set_serdes_access(params); 208 bnx2x_set_serdes_access(bp, params->port);
208 209
209 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + 210 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
210 params->port*0x10, 211 params->port*0x10,
@@ -825,37 +826,37 @@ static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
825 826
826} 827}
827 828
828u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type, 829u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
829 u8 phy_addr, u8 devad, u16 reg, u16 val) 830 u8 devad, u16 reg, u16 val)
830{ 831{
831 u32 tmp, saved_mode; 832 u32 tmp, saved_mode;
832 u8 i, rc = 0; 833 u8 i, rc = 0;
833 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
834 834
835 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz 835 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
836 * (a value of 49==0x31) and make sure that the AUTO poll is off 836 * (a value of 49==0x31) and make sure that the AUTO poll is off
837 */ 837 */
838 838
839 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 839 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
840 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL | 840 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
841 EMAC_MDIO_MODE_CLOCK_CNT); 841 EMAC_MDIO_MODE_CLOCK_CNT);
842 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 | 842 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
843 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); 843 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
844 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp); 844 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
845 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 845 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
846 udelay(40); 846 udelay(40);
847 847
848 /* address */ 848 /* address */
849 849
850 tmp = ((phy_addr << 21) | (devad << 16) | reg | 850 tmp = ((phy->addr << 21) | (devad << 16) | reg |
851 EMAC_MDIO_COMM_COMMAND_ADDRESS | 851 EMAC_MDIO_COMM_COMMAND_ADDRESS |
852 EMAC_MDIO_COMM_START_BUSY); 852 EMAC_MDIO_COMM_START_BUSY);
853 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 853 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
854 854
855 for (i = 0; i < 50; i++) { 855 for (i = 0; i < 50; i++) {
856 udelay(10); 856 udelay(10);
857 857
858 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 858 tmp = REG_RD(bp, phy->mdio_ctrl +
859 EMAC_REG_EMAC_MDIO_COMM);
859 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 860 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
860 udelay(5); 861 udelay(5);
861 break; 862 break;
@@ -866,15 +867,15 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
866 rc = -EFAULT; 867 rc = -EFAULT;
867 } else { 868 } else {
868 /* data */ 869 /* data */
869 tmp = ((phy_addr << 21) | (devad << 16) | val | 870 tmp = ((phy->addr << 21) | (devad << 16) | val |
870 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 871 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
871 EMAC_MDIO_COMM_START_BUSY); 872 EMAC_MDIO_COMM_START_BUSY);
872 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 873 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
873 874
874 for (i = 0; i < 50; i++) { 875 for (i = 0; i < 50; i++) {
875 udelay(10); 876 udelay(10);
876 877
877 tmp = REG_RD(bp, mdio_ctrl + 878 tmp = REG_RD(bp, phy->mdio_ctrl +
878 EMAC_REG_EMAC_MDIO_COMM); 879 EMAC_REG_EMAC_MDIO_COMM);
879 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 880 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
880 udelay(5); 881 udelay(5);
@@ -888,42 +889,41 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
888 } 889 }
889 890
890 /* Restore the saved mode */ 891 /* Restore the saved mode */
891 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); 892 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
892 893
893 return rc; 894 return rc;
894} 895}
895 896
896u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type, 897u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
897 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val) 898 u8 devad, u16 reg, u16 *ret_val)
898{ 899{
899 u32 val, saved_mode; 900 u32 val, saved_mode;
900 u16 i; 901 u16 i;
901 u8 rc = 0; 902 u8 rc = 0;
902 903
903 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
904 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz 904 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
905 * (a value of 49==0x31) and make sure that the AUTO poll is off 905 * (a value of 49==0x31) and make sure that the AUTO poll is off
906 */ 906 */
907 907
908 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 908 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
909 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL | 909 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
910 EMAC_MDIO_MODE_CLOCK_CNT)); 910 EMAC_MDIO_MODE_CLOCK_CNT));
911 val |= (EMAC_MDIO_MODE_CLAUSE_45 | 911 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
912 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); 912 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
913 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); 913 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
914 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 914 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
915 udelay(40); 915 udelay(40);
916 916
917 /* address */ 917 /* address */
918 val = ((phy_addr << 21) | (devad << 16) | reg | 918 val = ((phy->addr << 21) | (devad << 16) | reg |
919 EMAC_MDIO_COMM_COMMAND_ADDRESS | 919 EMAC_MDIO_COMM_COMMAND_ADDRESS |
920 EMAC_MDIO_COMM_START_BUSY); 920 EMAC_MDIO_COMM_START_BUSY);
921 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 921 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
922 922
923 for (i = 0; i < 50; i++) { 923 for (i = 0; i < 50; i++) {
924 udelay(10); 924 udelay(10);
925 925
926 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 926 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
927 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 927 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
928 udelay(5); 928 udelay(5);
929 break; 929 break;
@@ -937,15 +937,15 @@ u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
937 937
938 } else { 938 } else {
939 /* data */ 939 /* data */
940 val = ((phy_addr << 21) | (devad << 16) | 940 val = ((phy->addr << 21) | (devad << 16) |
941 EMAC_MDIO_COMM_COMMAND_READ_45 | 941 EMAC_MDIO_COMM_COMMAND_READ_45 |
942 EMAC_MDIO_COMM_START_BUSY); 942 EMAC_MDIO_COMM_START_BUSY);
943 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 943 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
944 944
945 for (i = 0; i < 50; i++) { 945 for (i = 0; i < 50; i++) {
946 udelay(10); 946 udelay(10);
947 947
948 val = REG_RD(bp, mdio_ctrl + 948 val = REG_RD(bp, phy->mdio_ctrl +
949 EMAC_REG_EMAC_MDIO_COMM); 949 EMAC_REG_EMAC_MDIO_COMM);
950 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 950 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
951 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 951 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
@@ -961,13 +961,49 @@ u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
961 } 961 }
962 962
963 /* Restore the saved mode */ 963 /* Restore the saved mode */
964 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); 964 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
965 965
966 return rc; 966 return rc;
967} 967}
968 968
969u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
970 u8 devad, u16 reg, u16 *ret_val)
971{
972 u8 phy_index;
973 /**
974 * Probe for the phy according to the given phy_addr, and execute
975 * the read request on it
976 */
977 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
978 if (params->phy[phy_index].addr == phy_addr) {
979 return bnx2x_cl45_read(params->bp,
980 &params->phy[phy_index], devad,
981 reg, ret_val);
982 }
983 }
984 return -EINVAL;
985}
986
987u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
988 u8 devad, u16 reg, u16 val)
989{
990 u8 phy_index;
991 /**
992 * Probe for the phy according to the given phy_addr, and execute
993 * the write request on it
994 */
995 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
996 if (params->phy[phy_index].addr == phy_addr) {
997 return bnx2x_cl45_write(params->bp,
998 &params->phy[phy_index], devad,
999 reg, val);
1000 }
1001 }
1002 return -EINVAL;
1003}
1004
969static void bnx2x_set_aer_mmd(struct link_params *params, 1005static void bnx2x_set_aer_mmd(struct link_params *params,
970 struct link_vars *vars) 1006 struct bnx2x_phy *phy)
971{ 1007{
972 struct bnx2x *bp = params->bp; 1008 struct bnx2x *bp = params->bp;
973 u32 ser_lane; 1009 u32 ser_lane;
@@ -977,16 +1013,16 @@ static void bnx2x_set_aer_mmd(struct link_params *params,
977 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1013 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
978 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1014 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
979 1015
980 offset = (vars->phy_flags & PHY_XGXS_FLAG) ? 1016 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
981 (params->phy_addr + ser_lane) : 0; 1017 (phy->addr + ser_lane) : 0;
982 1018
983 CL45_WR_OVER_CL22(bp, params->port, 1019 CL45_WR_OVER_CL22(bp, phy,
984 params->phy_addr,
985 MDIO_REG_BANK_AER_BLOCK, 1020 MDIO_REG_BANK_AER_BLOCK,
986 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset); 1021 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
987} 1022}
988 1023
989static void bnx2x_set_master_ln(struct link_params *params) 1024static void bnx2x_set_master_ln(struct link_params *params,
1025 struct bnx2x_phy *phy)
990{ 1026{
991 struct bnx2x *bp = params->bp; 1027 struct bnx2x *bp = params->bp;
992 u16 new_master_ln, ser_lane; 1028 u16 new_master_ln, ser_lane;
@@ -995,47 +1031,44 @@ static void bnx2x_set_master_ln(struct link_params *params)
995 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1031 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
996 1032
997 /* set the master_ln for AN */ 1033 /* set the master_ln for AN */
998 CL45_RD_OVER_CL22(bp, params->port, 1034 CL45_RD_OVER_CL22(bp, phy,
999 params->phy_addr,
1000 MDIO_REG_BANK_XGXS_BLOCK2, 1035 MDIO_REG_BANK_XGXS_BLOCK2,
1001 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 1036 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1002 &new_master_ln); 1037 &new_master_ln);
1003 1038
1004 CL45_WR_OVER_CL22(bp, params->port, 1039 CL45_WR_OVER_CL22(bp, phy,
1005 params->phy_addr,
1006 MDIO_REG_BANK_XGXS_BLOCK2 , 1040 MDIO_REG_BANK_XGXS_BLOCK2 ,
1007 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 1041 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1008 (new_master_ln | ser_lane)); 1042 (new_master_ln | ser_lane));
1009} 1043}
1010 1044
1011static u8 bnx2x_reset_unicore(struct link_params *params) 1045static u8 bnx2x_reset_unicore(struct link_params *params,
1046 struct bnx2x_phy *phy,
1047 u8 set_serdes)
1012{ 1048{
1013 struct bnx2x *bp = params->bp; 1049 struct bnx2x *bp = params->bp;
1014 u16 mii_control; 1050 u16 mii_control;
1015 u16 i; 1051 u16 i;
1016 1052
1017 CL45_RD_OVER_CL22(bp, params->port, 1053 CL45_RD_OVER_CL22(bp, phy,
1018 params->phy_addr,
1019 MDIO_REG_BANK_COMBO_IEEE0, 1054 MDIO_REG_BANK_COMBO_IEEE0,
1020 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 1055 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1021 1056
1022 /* reset the unicore */ 1057 /* reset the unicore */
1023 CL45_WR_OVER_CL22(bp, params->port, 1058 CL45_WR_OVER_CL22(bp, phy,
1024 params->phy_addr,
1025 MDIO_REG_BANK_COMBO_IEEE0, 1059 MDIO_REG_BANK_COMBO_IEEE0,
1026 MDIO_COMBO_IEEE0_MII_CONTROL, 1060 MDIO_COMBO_IEEE0_MII_CONTROL,
1027 (mii_control | 1061 (mii_control |
1028 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 1062 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1029 if (params->switch_cfg == SWITCH_CFG_1G) 1063 if (set_serdes)
1030 bnx2x_set_serdes_access(params); 1064 bnx2x_set_serdes_access(bp, params->port);
1031 1065
1032 /* wait for the reset to self clear */ 1066 /* wait for the reset to self clear */
1033 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 1067 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1034 udelay(5); 1068 udelay(5);
1035 1069
1036 /* the reset erased the previous bank value */ 1070 /* the reset erased the previous bank value */
1037 CL45_RD_OVER_CL22(bp, params->port, 1071 CL45_RD_OVER_CL22(bp, phy,
1038 params->phy_addr,
1039 MDIO_REG_BANK_COMBO_IEEE0, 1072 MDIO_REG_BANK_COMBO_IEEE0,
1040 MDIO_COMBO_IEEE0_MII_CONTROL, 1073 MDIO_COMBO_IEEE0_MII_CONTROL,
1041 &mii_control); 1074 &mii_control);
@@ -1051,7 +1084,8 @@ static u8 bnx2x_reset_unicore(struct link_params *params)
1051 1084
1052} 1085}
1053 1086
1054static void bnx2x_set_swap_lanes(struct link_params *params) 1087static void bnx2x_set_swap_lanes(struct link_params *params,
1088 struct bnx2x_phy *phy)
1055{ 1089{
1056 struct bnx2x *bp = params->bp; 1090 struct bnx2x *bp = params->bp;
1057 /* Each two bits represents a lane number: 1091 /* Each two bits represents a lane number:
@@ -1069,43 +1103,37 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
1069 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 1103 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1070 1104
1071 if (rx_lane_swap != 0x1b) { 1105 if (rx_lane_swap != 0x1b) {
1072 CL45_WR_OVER_CL22(bp, params->port, 1106 CL45_WR_OVER_CL22(bp, phy,
1073 params->phy_addr,
1074 MDIO_REG_BANK_XGXS_BLOCK2, 1107 MDIO_REG_BANK_XGXS_BLOCK2,
1075 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 1108 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1076 (rx_lane_swap | 1109 (rx_lane_swap |
1077 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 1110 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1078 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 1111 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1079 } else { 1112 } else {
1080 CL45_WR_OVER_CL22(bp, params->port, 1113 CL45_WR_OVER_CL22(bp, phy,
1081 params->phy_addr,
1082 MDIO_REG_BANK_XGXS_BLOCK2, 1114 MDIO_REG_BANK_XGXS_BLOCK2,
1083 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 1115 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1084 } 1116 }
1085 1117
1086 if (tx_lane_swap != 0x1b) { 1118 if (tx_lane_swap != 0x1b) {
1087 CL45_WR_OVER_CL22(bp, params->port, 1119 CL45_WR_OVER_CL22(bp, phy,
1088 params->phy_addr,
1089 MDIO_REG_BANK_XGXS_BLOCK2, 1120 MDIO_REG_BANK_XGXS_BLOCK2,
1090 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 1121 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1091 (tx_lane_swap | 1122 (tx_lane_swap |
1092 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 1123 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1093 } else { 1124 } else {
1094 CL45_WR_OVER_CL22(bp, params->port, 1125 CL45_WR_OVER_CL22(bp, phy,
1095 params->phy_addr,
1096 MDIO_REG_BANK_XGXS_BLOCK2, 1126 MDIO_REG_BANK_XGXS_BLOCK2,
1097 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 1127 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1098 } 1128 }
1099} 1129}
1100 1130
1101static void bnx2x_set_parallel_detection(struct link_params *params, 1131static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1102 u8 phy_flags) 1132 struct link_params *params)
1103{ 1133{
1104 struct bnx2x *bp = params->bp; 1134 struct bnx2x *bp = params->bp;
1105 u16 control2; 1135 u16 control2;
1106 1136 CL45_RD_OVER_CL22(bp, phy,
1107 CL45_RD_OVER_CL22(bp, params->port,
1108 params->phy_addr,
1109 MDIO_REG_BANK_SERDES_DIGITAL, 1137 MDIO_REG_BANK_SERDES_DIGITAL,
1110 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1138 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1111 &control2); 1139 &control2);
@@ -1115,25 +1143,22 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1115 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 1143 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1116 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n", 1144 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1117 params->speed_cap_mask, control2); 1145 params->speed_cap_mask, control2);
1118 CL45_WR_OVER_CL22(bp, params->port, 1146 CL45_WR_OVER_CL22(bp, phy,
1119 params->phy_addr,
1120 MDIO_REG_BANK_SERDES_DIGITAL, 1147 MDIO_REG_BANK_SERDES_DIGITAL,
1121 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1148 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1122 control2); 1149 control2);
1123 1150
1124 if ((phy_flags & PHY_XGXS_FLAG) && 1151 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1125 (params->speed_cap_mask & 1152 (params->speed_cap_mask &
1126 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 1153 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1127 DP(NETIF_MSG_LINK, "XGXS\n"); 1154 DP(NETIF_MSG_LINK, "XGXS\n");
1128 1155
1129 CL45_WR_OVER_CL22(bp, params->port, 1156 CL45_WR_OVER_CL22(bp, phy,
1130 params->phy_addr,
1131 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1157 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1132 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 1158 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1133 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 1159 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1134 1160
1135 CL45_RD_OVER_CL22(bp, params->port, 1161 CL45_RD_OVER_CL22(bp, phy,
1136 params->phy_addr,
1137 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1162 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1138 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 1163 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1139 &control2); 1164 &control2);
@@ -1142,15 +1167,13 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1142 control2 |= 1167 control2 |=
1143 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 1168 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1144 1169
1145 CL45_WR_OVER_CL22(bp, params->port, 1170 CL45_WR_OVER_CL22(bp, phy,
1146 params->phy_addr,
1147 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1171 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1148 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 1172 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1149 control2); 1173 control2);
1150 1174
1151 /* Disable parallel detection of HiG */ 1175 /* Disable parallel detection of HiG */
1152 CL45_WR_OVER_CL22(bp, params->port, 1176 CL45_WR_OVER_CL22(bp, phy,
1153 params->phy_addr,
1154 MDIO_REG_BANK_XGXS_BLOCK2, 1177 MDIO_REG_BANK_XGXS_BLOCK2,
1155 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 1178 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1156 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 1179 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
@@ -1158,7 +1181,8 @@ static void bnx2x_set_parallel_detection(struct link_params *params,
1158 } 1181 }
1159} 1182}
1160 1183
1161static void bnx2x_set_autoneg(struct link_params *params, 1184static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1185 struct link_params *params,
1162 struct link_vars *vars, 1186 struct link_vars *vars,
1163 u8 enable_cl73) 1187 u8 enable_cl73)
1164{ 1188{
@@ -1166,9 +1190,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1166 u16 reg_val; 1190 u16 reg_val;
1167 1191
1168 /* CL37 Autoneg */ 1192 /* CL37 Autoneg */
1169 1193 CL45_RD_OVER_CL22(bp, phy,
1170 CL45_RD_OVER_CL22(bp, params->port,
1171 params->phy_addr,
1172 MDIO_REG_BANK_COMBO_IEEE0, 1194 MDIO_REG_BANK_COMBO_IEEE0,
1173 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 1195 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1174 1196
@@ -1179,15 +1201,13 @@ static void bnx2x_set_autoneg(struct link_params *params,
1179 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 1201 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1180 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 1202 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1181 1203
1182 CL45_WR_OVER_CL22(bp, params->port, 1204 CL45_WR_OVER_CL22(bp, phy,
1183 params->phy_addr,
1184 MDIO_REG_BANK_COMBO_IEEE0, 1205 MDIO_REG_BANK_COMBO_IEEE0,
1185 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 1206 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1186 1207
1187 /* Enable/Disable Autodetection */ 1208 /* Enable/Disable Autodetection */
1188 1209
1189 CL45_RD_OVER_CL22(bp, params->port, 1210 CL45_RD_OVER_CL22(bp, phy,
1190 params->phy_addr,
1191 MDIO_REG_BANK_SERDES_DIGITAL, 1211 MDIO_REG_BANK_SERDES_DIGITAL,
1192 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val); 1212 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1193 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 1213 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
@@ -1198,14 +1218,12 @@ static void bnx2x_set_autoneg(struct link_params *params,
1198 else 1218 else
1199 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1219 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1200 1220
1201 CL45_WR_OVER_CL22(bp, params->port, 1221 CL45_WR_OVER_CL22(bp, phy,
1202 params->phy_addr,
1203 MDIO_REG_BANK_SERDES_DIGITAL, 1222 MDIO_REG_BANK_SERDES_DIGITAL,
1204 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 1223 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1205 1224
1206 /* Enable TetonII and BAM autoneg */ 1225 /* Enable TetonII and BAM autoneg */
1207 CL45_RD_OVER_CL22(bp, params->port, 1226 CL45_RD_OVER_CL22(bp, phy,
1208 params->phy_addr,
1209 MDIO_REG_BANK_BAM_NEXT_PAGE, 1227 MDIO_REG_BANK_BAM_NEXT_PAGE,
1210 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1228 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1211 &reg_val); 1229 &reg_val);
@@ -1218,23 +1236,20 @@ static void bnx2x_set_autoneg(struct link_params *params,
1218 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 1236 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1219 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 1237 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1220 } 1238 }
1221 CL45_WR_OVER_CL22(bp, params->port, 1239 CL45_WR_OVER_CL22(bp, phy,
1222 params->phy_addr,
1223 MDIO_REG_BANK_BAM_NEXT_PAGE, 1240 MDIO_REG_BANK_BAM_NEXT_PAGE,
1224 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1241 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1225 reg_val); 1242 reg_val);
1226 1243
1227 if (enable_cl73) { 1244 if (enable_cl73) {
1228 /* Enable Cl73 FSM status bits */ 1245 /* Enable Cl73 FSM status bits */
1229 CL45_WR_OVER_CL22(bp, params->port, 1246 CL45_WR_OVER_CL22(bp, phy,
1230 params->phy_addr,
1231 MDIO_REG_BANK_CL73_USERB0, 1247 MDIO_REG_BANK_CL73_USERB0,
1232 MDIO_CL73_USERB0_CL73_UCTRL, 1248 MDIO_CL73_USERB0_CL73_UCTRL,
1233 0xe); 1249 0xe);
1234 1250
1235 /* Enable BAM Station Manager*/ 1251 /* Enable BAM Station Manager*/
1236 CL45_WR_OVER_CL22(bp, params->port, 1252 CL45_WR_OVER_CL22(bp, phy,
1237 params->phy_addr,
1238 MDIO_REG_BANK_CL73_USERB0, 1253 MDIO_REG_BANK_CL73_USERB0,
1239 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 1254 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1240 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 1255 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
@@ -1242,8 +1257,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1242 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 1257 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1243 1258
1244 /* Advertise CL73 link speeds */ 1259 /* Advertise CL73 link speeds */
1245 CL45_RD_OVER_CL22(bp, params->port, 1260 CL45_RD_OVER_CL22(bp, phy,
1246 params->phy_addr,
1247 MDIO_REG_BANK_CL73_IEEEB1, 1261 MDIO_REG_BANK_CL73_IEEEB1,
1248 MDIO_CL73_IEEEB1_AN_ADV2, 1262 MDIO_CL73_IEEEB1_AN_ADV2,
1249 &reg_val); 1263 &reg_val);
@@ -1254,8 +1268,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1254 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 1268 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1255 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 1269 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1256 1270
1257 CL45_WR_OVER_CL22(bp, params->port, 1271 CL45_WR_OVER_CL22(bp, phy,
1258 params->phy_addr,
1259 MDIO_REG_BANK_CL73_IEEEB1, 1272 MDIO_REG_BANK_CL73_IEEEB1,
1260 MDIO_CL73_IEEEB1_AN_ADV2, 1273 MDIO_CL73_IEEEB1_AN_ADV2,
1261 reg_val); 1274 reg_val);
@@ -1266,22 +1279,21 @@ static void bnx2x_set_autoneg(struct link_params *params,
1266 } else /* CL73 Autoneg Disabled */ 1279 } else /* CL73 Autoneg Disabled */
1267 reg_val = 0; 1280 reg_val = 0;
1268 1281
1269 CL45_WR_OVER_CL22(bp, params->port, 1282 CL45_WR_OVER_CL22(bp, phy,
1270 params->phy_addr,
1271 MDIO_REG_BANK_CL73_IEEEB0, 1283 MDIO_REG_BANK_CL73_IEEEB0,
1272 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 1284 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1273} 1285}
1274 1286
1275/* program SerDes, forced speed */ 1287/* program SerDes, forced speed */
1276static void bnx2x_program_serdes(struct link_params *params, 1288static void bnx2x_program_serdes(struct bnx2x_phy *phy,
1289 struct link_params *params,
1277 struct link_vars *vars) 1290 struct link_vars *vars)
1278{ 1291{
1279 struct bnx2x *bp = params->bp; 1292 struct bnx2x *bp = params->bp;
1280 u16 reg_val; 1293 u16 reg_val;
1281 1294
1282 /* program duplex, disable autoneg and sgmii*/ 1295 /* program duplex, disable autoneg and sgmii*/
1283 CL45_RD_OVER_CL22(bp, params->port, 1296 CL45_RD_OVER_CL22(bp, phy,
1284 params->phy_addr,
1285 MDIO_REG_BANK_COMBO_IEEE0, 1297 MDIO_REG_BANK_COMBO_IEEE0,
1286 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 1298 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1287 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 1299 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
@@ -1289,15 +1301,13 @@ static void bnx2x_program_serdes(struct link_params *params,
1289 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 1301 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
1290 if (params->req_duplex == DUPLEX_FULL) 1302 if (params->req_duplex == DUPLEX_FULL)
1291 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 1303 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1292 CL45_WR_OVER_CL22(bp, params->port, 1304 CL45_WR_OVER_CL22(bp, phy,
1293 params->phy_addr,
1294 MDIO_REG_BANK_COMBO_IEEE0, 1305 MDIO_REG_BANK_COMBO_IEEE0,
1295 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 1306 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1296 1307
1297 /* program speed 1308 /* program speed
1298 - needed only if the speed is greater than 1G (2.5G or 10G) */ 1309 - needed only if the speed is greater than 1G (2.5G or 10G) */
1299 CL45_RD_OVER_CL22(bp, params->port, 1310 CL45_RD_OVER_CL22(bp, phy,
1300 params->phy_addr,
1301 MDIO_REG_BANK_SERDES_DIGITAL, 1311 MDIO_REG_BANK_SERDES_DIGITAL,
1302 MDIO_SERDES_DIGITAL_MISC1, &reg_val); 1312 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
1303 /* clearing the speed value before setting the right speed */ 1313 /* clearing the speed value before setting the right speed */
@@ -1320,14 +1330,14 @@ static void bnx2x_program_serdes(struct link_params *params,
1320 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; 1330 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1321 } 1331 }
1322 1332
1323 CL45_WR_OVER_CL22(bp, params->port, 1333 CL45_WR_OVER_CL22(bp, phy,
1324 params->phy_addr,
1325 MDIO_REG_BANK_SERDES_DIGITAL, 1334 MDIO_REG_BANK_SERDES_DIGITAL,
1326 MDIO_SERDES_DIGITAL_MISC1, reg_val); 1335 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1327 1336
1328} 1337}
1329 1338
1330static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params) 1339static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
1340 struct link_params *params)
1331{ 1341{
1332 struct bnx2x *bp = params->bp; 1342 struct bnx2x *bp = params->bp;
1333 u16 val = 0; 1343 u16 val = 0;
@@ -1339,18 +1349,17 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1339 val |= MDIO_OVER_1G_UP1_2_5G; 1349 val |= MDIO_OVER_1G_UP1_2_5G;
1340 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 1350 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1341 val |= MDIO_OVER_1G_UP1_10G; 1351 val |= MDIO_OVER_1G_UP1_10G;
1342 CL45_WR_OVER_CL22(bp, params->port, 1352 CL45_WR_OVER_CL22(bp, phy,
1343 params->phy_addr,
1344 MDIO_REG_BANK_OVER_1G, 1353 MDIO_REG_BANK_OVER_1G,
1345 MDIO_OVER_1G_UP1, val); 1354 MDIO_OVER_1G_UP1, val);
1346 1355
1347 CL45_WR_OVER_CL22(bp, params->port, 1356 CL45_WR_OVER_CL22(bp, phy,
1348 params->phy_addr,
1349 MDIO_REG_BANK_OVER_1G, 1357 MDIO_REG_BANK_OVER_1G,
1350 MDIO_OVER_1G_UP3, 0x400); 1358 MDIO_OVER_1G_UP3, 0x400);
1351} 1359}
1352 1360
1353static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc) 1361static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1362 struct link_params *params, u16 *ieee_fc)
1354{ 1363{
1355 struct bnx2x *bp = params->bp; 1364 struct bnx2x *bp = params->bp;
1356 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 1365 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
@@ -1385,30 +1394,30 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1385 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 1394 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1386} 1395}
1387 1396
1388static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 1397static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
1398 struct link_params *params,
1389 u16 ieee_fc) 1399 u16 ieee_fc)
1390{ 1400{
1391 struct bnx2x *bp = params->bp; 1401 struct bnx2x *bp = params->bp;
1392 u16 val; 1402 u16 val;
1393 /* for AN, we are always publishing full duplex */ 1403 /* for AN, we are always publishing full duplex */
1394 1404
1395 CL45_WR_OVER_CL22(bp, params->port, 1405 CL45_WR_OVER_CL22(bp, phy,
1396 params->phy_addr,
1397 MDIO_REG_BANK_COMBO_IEEE0, 1406 MDIO_REG_BANK_COMBO_IEEE0,
1398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 1407 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
1399 CL45_RD_OVER_CL22(bp, params->port, 1408 CL45_RD_OVER_CL22(bp, phy,
1400 params->phy_addr,
1401 MDIO_REG_BANK_CL73_IEEEB1, 1409 MDIO_REG_BANK_CL73_IEEEB1,
1402 MDIO_CL73_IEEEB1_AN_ADV1, &val); 1410 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1403 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 1411 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1404 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 1412 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1405 CL45_WR_OVER_CL22(bp, params->port, 1413 CL45_WR_OVER_CL22(bp, phy,
1406 params->phy_addr,
1407 MDIO_REG_BANK_CL73_IEEEB1, 1414 MDIO_REG_BANK_CL73_IEEEB1,
1408 MDIO_CL73_IEEEB1_AN_ADV1, val); 1415 MDIO_CL73_IEEEB1_AN_ADV1, val);
1409} 1416}
1410 1417
1411static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73) 1418static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
1419 struct link_params *params,
1420 u8 enable_cl73)
1412{ 1421{
1413 struct bnx2x *bp = params->bp; 1422 struct bnx2x *bp = params->bp;
1414 u16 mii_control; 1423 u16 mii_control;
@@ -1417,14 +1426,12 @@ static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
1417 /* Enable and restart BAM/CL37 aneg */ 1426 /* Enable and restart BAM/CL37 aneg */
1418 1427
1419 if (enable_cl73) { 1428 if (enable_cl73) {
1420 CL45_RD_OVER_CL22(bp, params->port, 1429 CL45_RD_OVER_CL22(bp, phy,
1421 params->phy_addr,
1422 MDIO_REG_BANK_CL73_IEEEB0, 1430 MDIO_REG_BANK_CL73_IEEEB0,
1423 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 1431 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1424 &mii_control); 1432 &mii_control);
1425 1433
1426 CL45_WR_OVER_CL22(bp, params->port, 1434 CL45_WR_OVER_CL22(bp, phy,
1427 params->phy_addr,
1428 MDIO_REG_BANK_CL73_IEEEB0, 1435 MDIO_REG_BANK_CL73_IEEEB0,
1429 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 1436 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1430 (mii_control | 1437 (mii_control |
@@ -1432,16 +1439,14 @@ static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
1432 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 1439 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1433 } else { 1440 } else {
1434 1441
1435 CL45_RD_OVER_CL22(bp, params->port, 1442 CL45_RD_OVER_CL22(bp, phy,
1436 params->phy_addr,
1437 MDIO_REG_BANK_COMBO_IEEE0, 1443 MDIO_REG_BANK_COMBO_IEEE0,
1438 MDIO_COMBO_IEEE0_MII_CONTROL, 1444 MDIO_COMBO_IEEE0_MII_CONTROL,
1439 &mii_control); 1445 &mii_control);
1440 DP(NETIF_MSG_LINK, 1446 DP(NETIF_MSG_LINK,
1441 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 1447 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1442 mii_control); 1448 mii_control);
1443 CL45_WR_OVER_CL22(bp, params->port, 1449 CL45_WR_OVER_CL22(bp, phy,
1444 params->phy_addr,
1445 MDIO_REG_BANK_COMBO_IEEE0, 1450 MDIO_REG_BANK_COMBO_IEEE0,
1446 MDIO_COMBO_IEEE0_MII_CONTROL, 1451 MDIO_COMBO_IEEE0_MII_CONTROL,
1447 (mii_control | 1452 (mii_control |
@@ -1450,7 +1455,8 @@ static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
1450 } 1455 }
1451} 1456}
1452 1457
1453static void bnx2x_initialize_sgmii_process(struct link_params *params, 1458static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
1459 struct link_params *params,
1454 struct link_vars *vars) 1460 struct link_vars *vars)
1455{ 1461{
1456 struct bnx2x *bp = params->bp; 1462 struct bnx2x *bp = params->bp;
@@ -1458,8 +1464,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params,
1458 1464
1459 /* in SGMII mode, the unicore is always slave */ 1465 /* in SGMII mode, the unicore is always slave */
1460 1466
1461 CL45_RD_OVER_CL22(bp, params->port, 1467 CL45_RD_OVER_CL22(bp, phy,
1462 params->phy_addr,
1463 MDIO_REG_BANK_SERDES_DIGITAL, 1468 MDIO_REG_BANK_SERDES_DIGITAL,
1464 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 1469 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1465 &control1); 1470 &control1);
@@ -1468,8 +1473,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params,
1468 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 1473 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1469 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 1474 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1470 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 1475 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1471 CL45_WR_OVER_CL22(bp, params->port, 1476 CL45_WR_OVER_CL22(bp, phy,
1472 params->phy_addr,
1473 MDIO_REG_BANK_SERDES_DIGITAL, 1477 MDIO_REG_BANK_SERDES_DIGITAL,
1474 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 1478 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1475 control1); 1479 control1);
@@ -1479,8 +1483,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params,
1479 /* set speed, disable autoneg */ 1483 /* set speed, disable autoneg */
1480 u16 mii_control; 1484 u16 mii_control;
1481 1485
1482 CL45_RD_OVER_CL22(bp, params->port, 1486 CL45_RD_OVER_CL22(bp, phy,
1483 params->phy_addr,
1484 MDIO_REG_BANK_COMBO_IEEE0, 1487 MDIO_REG_BANK_COMBO_IEEE0,
1485 MDIO_COMBO_IEEE0_MII_CONTROL, 1488 MDIO_COMBO_IEEE0_MII_CONTROL,
1486 &mii_control); 1489 &mii_control);
@@ -1511,15 +1514,14 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params,
1511 if (params->req_duplex == DUPLEX_FULL) 1514 if (params->req_duplex == DUPLEX_FULL)
1512 mii_control |= 1515 mii_control |=
1513 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 1516 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1514 CL45_WR_OVER_CL22(bp, params->port, 1517 CL45_WR_OVER_CL22(bp, phy,
1515 params->phy_addr,
1516 MDIO_REG_BANK_COMBO_IEEE0, 1518 MDIO_REG_BANK_COMBO_IEEE0,
1517 MDIO_COMBO_IEEE0_MII_CONTROL, 1519 MDIO_COMBO_IEEE0_MII_CONTROL,
1518 mii_control); 1520 mii_control);
1519 1521
1520 } else { /* AN mode */ 1522 } else { /* AN mode */
1521 /* enable and restart AN */ 1523 /* enable and restart AN */
1522 bnx2x_restart_autoneg(params, 0); 1524 bnx2x_restart_autoneg(phy, params, 0);
1523 } 1525 }
1524} 1526}
1525 1527
@@ -1551,43 +1553,31 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1551 } 1553 }
1552} 1554}
1553 1555
1554static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params, 1556static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
1555 struct link_vars *vars) 1557 struct link_params *params,
1558 struct link_vars *vars)
1556{ 1559{
1557 struct bnx2x *bp = params->bp; 1560 struct bnx2x *bp = params->bp;
1558 u8 ext_phy_addr;
1559 u16 ld_pause; /* local */ 1561 u16 ld_pause; /* local */
1560 u16 lp_pause; /* link partner */ 1562 u16 lp_pause; /* link partner */
1561 u16 an_complete; /* AN complete */ 1563 u16 an_complete; /* AN complete */
1562 u16 pause_result; 1564 u16 pause_result;
1563 u8 ret = 0; 1565 u8 ret = 0;
1564 u32 ext_phy_type;
1565 u8 port = params->port;
1566 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
1567 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1568 /* read twice */ 1566 /* read twice */
1569 1567
1570 bnx2x_cl45_read(bp, port, 1568 bnx2x_cl45_read(bp, phy,
1571 ext_phy_type,
1572 ext_phy_addr,
1573 MDIO_AN_DEVAD, 1569 MDIO_AN_DEVAD,
1574 MDIO_AN_REG_STATUS, &an_complete); 1570 MDIO_AN_REG_STATUS, &an_complete);
1575 bnx2x_cl45_read(bp, port, 1571 bnx2x_cl45_read(bp, phy,
1576 ext_phy_type,
1577 ext_phy_addr,
1578 MDIO_AN_DEVAD, 1572 MDIO_AN_DEVAD,
1579 MDIO_AN_REG_STATUS, &an_complete); 1573 MDIO_AN_REG_STATUS, &an_complete);
1580 1574
1581 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) { 1575 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1582 ret = 1; 1576 ret = 1;
1583 bnx2x_cl45_read(bp, port, 1577 bnx2x_cl45_read(bp, phy,
1584 ext_phy_type,
1585 ext_phy_addr,
1586 MDIO_AN_DEVAD, 1578 MDIO_AN_DEVAD,
1587 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 1579 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1588 bnx2x_cl45_read(bp, port, 1580 bnx2x_cl45_read(bp, phy,
1589 ext_phy_type,
1590 ext_phy_addr,
1591 MDIO_AN_DEVAD, 1581 MDIO_AN_DEVAD,
1592 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 1582 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1593 pause_result = (ld_pause & 1583 pause_result = (ld_pause &
@@ -1598,16 +1588,12 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
1598 pause_result); 1588 pause_result);
1599 bnx2x_pause_resolve(vars, pause_result); 1589 bnx2x_pause_resolve(vars, pause_result);
1600 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE && 1590 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
1601 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 1591 phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1602 bnx2x_cl45_read(bp, port, 1592 bnx2x_cl45_read(bp, phy,
1603 ext_phy_type,
1604 ext_phy_addr,
1605 MDIO_AN_DEVAD, 1593 MDIO_AN_DEVAD,
1606 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 1594 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1607 1595
1608 bnx2x_cl45_read(bp, port, 1596 bnx2x_cl45_read(bp, phy,
1609 ext_phy_type,
1610 ext_phy_addr,
1611 MDIO_AN_DEVAD, 1597 MDIO_AN_DEVAD,
1612 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 1598 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1613 pause_result = (ld_pause & 1599 pause_result = (ld_pause &
@@ -1623,17 +1609,16 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
1623 return ret; 1609 return ret;
1624} 1610}
1625 1611
1626static u8 bnx2x_direct_parallel_detect_used(struct link_params *params) 1612static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
1613 struct link_params *params)
1627{ 1614{
1628 struct bnx2x *bp = params->bp; 1615 struct bnx2x *bp = params->bp;
1629 u16 pd_10g, status2_1000x; 1616 u16 pd_10g, status2_1000x;
1630 CL45_RD_OVER_CL22(bp, params->port, 1617 CL45_RD_OVER_CL22(bp, phy,
1631 params->phy_addr,
1632 MDIO_REG_BANK_SERDES_DIGITAL, 1618 MDIO_REG_BANK_SERDES_DIGITAL,
1633 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 1619 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1634 &status2_1000x); 1620 &status2_1000x);
1635 CL45_RD_OVER_CL22(bp, params->port, 1621 CL45_RD_OVER_CL22(bp, phy,
1636 params->phy_addr,
1637 MDIO_REG_BANK_SERDES_DIGITAL, 1622 MDIO_REG_BANK_SERDES_DIGITAL,
1638 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 1623 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1639 &status2_1000x); 1624 &status2_1000x);
@@ -1643,8 +1628,7 @@ static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1643 return 1; 1628 return 1;
1644 } 1629 }
1645 1630
1646 CL45_RD_OVER_CL22(bp, params->port, 1631 CL45_RD_OVER_CL22(bp, phy,
1647 params->phy_addr,
1648 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1632 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1649 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 1633 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1650 &pd_10g); 1634 &pd_10g);
@@ -1657,9 +1641,10 @@ static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1657 return 0; 1641 return 0;
1658} 1642}
1659 1643
1660static void bnx2x_flow_ctrl_resolve(struct link_params *params, 1644static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
1661 struct link_vars *vars, 1645 struct link_params *params,
1662 u32 gp_status) 1646 struct link_vars *vars,
1647 u32 gp_status)
1663{ 1648{
1664 struct bnx2x *bp = params->bp; 1649 struct bnx2x *bp = params->bp;
1665 u16 ld_pause; /* local driver */ 1650 u16 ld_pause; /* local driver */
@@ -1672,9 +1657,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1672 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && 1657 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1673 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 1658 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1674 (!(vars->phy_flags & PHY_SGMII_FLAG)) && 1659 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1675 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1660 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1676 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) { 1661 if (bnx2x_direct_parallel_detect_used(phy, params)) {
1677 if (bnx2x_direct_parallel_detect_used(params)) {
1678 vars->flow_ctrl = params->req_fc_auto_adv; 1662 vars->flow_ctrl = params->req_fc_auto_adv;
1679 return; 1663 return;
1680 } 1664 }
@@ -1684,13 +1668,11 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1684 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 1668 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1685 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 1669 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1686 1670
1687 CL45_RD_OVER_CL22(bp, params->port, 1671 CL45_RD_OVER_CL22(bp, phy,
1688 params->phy_addr,
1689 MDIO_REG_BANK_CL73_IEEEB1, 1672 MDIO_REG_BANK_CL73_IEEEB1,
1690 MDIO_CL73_IEEEB1_AN_ADV1, 1673 MDIO_CL73_IEEEB1_AN_ADV1,
1691 &ld_pause); 1674 &ld_pause);
1692 CL45_RD_OVER_CL22(bp, params->port, 1675 CL45_RD_OVER_CL22(bp, phy,
1693 params->phy_addr,
1694 MDIO_REG_BANK_CL73_IEEEB1, 1676 MDIO_REG_BANK_CL73_IEEEB1,
1695 MDIO_CL73_IEEEB1_AN_LP_ADV1, 1677 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1696 &lp_pause); 1678 &lp_pause);
@@ -1703,14 +1685,11 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1703 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", 1685 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1704 pause_result); 1686 pause_result);
1705 } else { 1687 } else {
1706 1688 CL45_RD_OVER_CL22(bp, phy,
1707 CL45_RD_OVER_CL22(bp, params->port,
1708 params->phy_addr,
1709 MDIO_REG_BANK_COMBO_IEEE0, 1689 MDIO_REG_BANK_COMBO_IEEE0,
1710 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 1690 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1711 &ld_pause); 1691 &ld_pause);
1712 CL45_RD_OVER_CL22(bp, params->port, 1692 CL45_RD_OVER_CL22(bp, phy,
1713 params->phy_addr,
1714 MDIO_REG_BANK_COMBO_IEEE0, 1693 MDIO_REG_BANK_COMBO_IEEE0,
1715 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 1694 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1716 &lp_pause); 1695 &lp_pause);
@@ -1723,7 +1702,7 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1723 } 1702 }
1724 bnx2x_pause_resolve(vars, pause_result); 1703 bnx2x_pause_resolve(vars, pause_result);
1725 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && 1704 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1726 (bnx2x_ext_phy_resolve_fc(params, vars))) { 1705 (bnx2x_ext_phy_resolve_fc(phy, params, vars))) {
1727 return; 1706 return;
1728 } else { 1707 } else {
1729 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) 1708 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
@@ -1734,14 +1713,14 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1734 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 1713 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1735} 1714}
1736 1715
1737static void bnx2x_check_fallback_to_cl37(struct link_params *params) 1716static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
1717 struct link_params *params)
1738{ 1718{
1739 struct bnx2x *bp = params->bp; 1719 struct bnx2x *bp = params->bp;
1740 u16 rx_status, ustat_val, cl37_fsm_recieved; 1720 u16 rx_status, ustat_val, cl37_fsm_recieved;
1741 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 1721 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1742 /* Step 1: Make sure signal is detected */ 1722 /* Step 1: Make sure signal is detected */
1743 CL45_RD_OVER_CL22(bp, params->port, 1723 CL45_RD_OVER_CL22(bp, phy,
1744 params->phy_addr,
1745 MDIO_REG_BANK_RX0, 1724 MDIO_REG_BANK_RX0,
1746 MDIO_RX0_RX_STATUS, 1725 MDIO_RX0_RX_STATUS,
1747 &rx_status); 1726 &rx_status);
@@ -1749,16 +1728,14 @@ static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1749 (MDIO_RX0_RX_STATUS_SIGDET)) { 1728 (MDIO_RX0_RX_STATUS_SIGDET)) {
1750 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 1729 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1751 "rx_status(0x80b0) = 0x%x\n", rx_status); 1730 "rx_status(0x80b0) = 0x%x\n", rx_status);
1752 CL45_WR_OVER_CL22(bp, params->port, 1731 CL45_WR_OVER_CL22(bp, phy,
1753 params->phy_addr,
1754 MDIO_REG_BANK_CL73_IEEEB0, 1732 MDIO_REG_BANK_CL73_IEEEB0,
1755 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 1733 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1756 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 1734 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1757 return; 1735 return;
1758 } 1736 }
1759 /* Step 2: Check CL73 state machine */ 1737 /* Step 2: Check CL73 state machine */
1760 CL45_RD_OVER_CL22(bp, params->port, 1738 CL45_RD_OVER_CL22(bp, phy,
1761 params->phy_addr,
1762 MDIO_REG_BANK_CL73_USERB0, 1739 MDIO_REG_BANK_CL73_USERB0,
1763 MDIO_CL73_USERB0_CL73_USTAT1, 1740 MDIO_CL73_USERB0_CL73_USTAT1,
1764 &ustat_val); 1741 &ustat_val);
@@ -1773,8 +1750,7 @@ static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1773 } 1750 }
1774 /* Step 3: Check CL37 Message Pages received to indicate LP 1751 /* Step 3: Check CL37 Message Pages received to indicate LP
1775 supports only CL37 */ 1752 supports only CL37 */
1776 CL45_RD_OVER_CL22(bp, params->port, 1753 CL45_RD_OVER_CL22(bp, phy,
1777 params->phy_addr,
1778 MDIO_REG_BANK_REMOTE_PHY, 1754 MDIO_REG_BANK_REMOTE_PHY,
1779 MDIO_REMOTE_PHY_MISC_RX_STATUS, 1755 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1780 &cl37_fsm_recieved); 1756 &cl37_fsm_recieved);
@@ -1792,13 +1768,12 @@ static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1792 connected to a device which does not support cl73, but does support 1768 connected to a device which does not support cl73, but does support
1793 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */ 1769 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1794 /* Disable CL73 */ 1770 /* Disable CL73 */
1795 CL45_WR_OVER_CL22(bp, params->port, 1771 CL45_WR_OVER_CL22(bp, phy,
1796 params->phy_addr,
1797 MDIO_REG_BANK_CL73_IEEEB0, 1772 MDIO_REG_BANK_CL73_IEEEB0,
1798 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 1773 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1799 0); 1774 0);
1800 /* Restart CL37 autoneg */ 1775 /* Restart CL37 autoneg */
1801 bnx2x_restart_autoneg(params, 0); 1776 bnx2x_restart_autoneg(phy, params, 0);
1802 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 1777 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1803} 1778}
1804static u8 bnx2x_link_settings_status(struct link_params *params, 1779static u8 bnx2x_link_settings_status(struct link_params *params,
@@ -1809,8 +1784,8 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1809 struct bnx2x *bp = params->bp; 1784 struct bnx2x *bp = params->bp;
1810 u16 new_line_speed; 1785 u16 new_line_speed;
1811 u8 rc = 0; 1786 u8 rc = 0;
1787 u32 ext_phy_type;
1812 vars->link_status = 0; 1788 vars->link_status = 0;
1813
1814 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 1789 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1815 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n", 1790 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1816 gp_status); 1791 gp_status);
@@ -1823,7 +1798,8 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1823 else 1798 else
1824 vars->duplex = DUPLEX_HALF; 1799 vars->duplex = DUPLEX_HALF;
1825 1800
1826 bnx2x_flow_ctrl_resolve(params, vars, gp_status); 1801 bnx2x_flow_ctrl_resolve(&params->phy[INT_PHY],
1802 params, vars, gp_status);
1827 1803
1828 switch (gp_status & GP_STATUS_SPEED_MASK) { 1804 switch (gp_status & GP_STATUS_SPEED_MASK) {
1829 case GP_STATUS_10M: 1805 case GP_STATUS_10M:
@@ -1909,8 +1885,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1909 Comes to deals with possible FIFO glitch due to clk change 1885 Comes to deals with possible FIFO glitch due to clk change
1910 when speed is decreased without link down indicator */ 1886 when speed is decreased without link down indicator */
1911 if (new_line_speed != vars->line_speed) { 1887 if (new_line_speed != vars->line_speed) {
1912 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) != 1888 if (!SINGLE_MEDIA_DIRECT(params) &&
1913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1914 ext_phy_link_up) { 1889 ext_phy_link_up) {
1915 DP(NETIF_MSG_LINK, "Internal link speed %d is" 1890 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1916 " different than the external" 1891 " different than the external"
@@ -1925,15 +1900,15 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1925 } 1900 }
1926 vars->line_speed = new_line_speed; 1901 vars->line_speed = new_line_speed;
1927 vars->link_status |= LINK_STATUS_SERDES_LINK; 1902 vars->link_status |= LINK_STATUS_SERDES_LINK;
1928 1903 ext_phy_type = params->phy[EXT_PHY1].type;
1929 if ((params->req_line_speed == SPEED_AUTO_NEG) && 1904 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1930 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1905 ((ext_phy_type ==
1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || 1906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1907 (ext_phy_type ==
1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 1908 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1934 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1909 (ext_phy_type ==
1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) || 1910 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
1936 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1911 (ext_phy_type ==
1937 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) { 1912 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1938 vars->autoneg = AUTO_NEG_ENABLED; 1913 vars->autoneg = AUTO_NEG_ENABLED;
1939 1914
@@ -1956,6 +1931,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1956 vars->link_status |= 1931 vars->link_status |=
1957 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 1932 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1958 1933
1934
1959 } else { /* link_down */ 1935 } else { /* link_down */
1960 DP(NETIF_MSG_LINK, "phy link down\n"); 1936 DP(NETIF_MSG_LINK, "phy link down\n");
1961 1937
@@ -1967,10 +1943,10 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1967 vars->mac_type = MAC_TYPE_NONE; 1943 vars->mac_type = MAC_TYPE_NONE;
1968 1944
1969 if ((params->req_line_speed == SPEED_AUTO_NEG) && 1945 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1970 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1946 (SINGLE_MEDIA_DIRECT(params))) {
1971 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
1972 /* Check signal is detected */ 1947 /* Check signal is detected */
1973 bnx2x_check_fallback_to_cl37(params); 1948 bnx2x_check_fallback_to_cl37(&params->phy[INT_PHY],
1949 params);
1974 } 1950 }
1975 } 1951 }
1976 1952
@@ -1988,13 +1964,13 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1988static void bnx2x_set_gmii_tx_driver(struct link_params *params) 1964static void bnx2x_set_gmii_tx_driver(struct link_params *params)
1989{ 1965{
1990 struct bnx2x *bp = params->bp; 1966 struct bnx2x *bp = params->bp;
1967 struct bnx2x_phy *phy = &params->phy[INT_PHY];
1991 u16 lp_up2; 1968 u16 lp_up2;
1992 u16 tx_driver; 1969 u16 tx_driver;
1993 u16 bank; 1970 u16 bank;
1994 1971
1995 /* read precomp */ 1972 /* read precomp */
1996 CL45_RD_OVER_CL22(bp, params->port, 1973 CL45_RD_OVER_CL22(bp, phy,
1997 params->phy_addr,
1998 MDIO_REG_BANK_OVER_1G, 1974 MDIO_REG_BANK_OVER_1G,
1999 MDIO_OVER_1G_LP_UP2, &lp_up2); 1975 MDIO_OVER_1G_LP_UP2, &lp_up2);
2000 1976
@@ -2008,8 +1984,7 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2008 1984
2009 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 1985 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2010 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 1986 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2011 CL45_RD_OVER_CL22(bp, params->port, 1987 CL45_RD_OVER_CL22(bp, phy,
2012 params->phy_addr,
2013 bank, 1988 bank,
2014 MDIO_TX0_TX_DRIVER, &tx_driver); 1989 MDIO_TX0_TX_DRIVER, &tx_driver);
2015 1990
@@ -2018,8 +1993,7 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2018 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 1993 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2019 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 1994 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2020 tx_driver |= lp_up2; 1995 tx_driver |= lp_up2;
2021 CL45_WR_OVER_CL22(bp, params->port, 1996 CL45_WR_OVER_CL22(bp, phy,
2022 params->phy_addr,
2023 bank, 1997 bank,
2024 MDIO_TX0_TX_DRIVER, tx_driver); 1998 MDIO_TX0_TX_DRIVER, tx_driver);
2025 } 1999 }
@@ -2072,6 +2046,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
2072 return 0; 2046 return 0;
2073} 2047}
2074 2048
2049
2075/*****************************************************************************/ 2050/*****************************************************************************/
2076/* External Phy section */ 2051/* External Phy section */
2077/*****************************************************************************/ 2052/*****************************************************************************/
@@ -2084,21 +2059,16 @@ void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
2084 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 2059 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
2085} 2060}
2086 2061
2087static void bnx2x_ext_phy_reset(struct link_params *params, 2062static void bnx2x_ext_phy_reset(struct bnx2x_phy *phy,
2088 struct link_vars *vars) 2063 struct link_params *params,
2064 struct link_vars *vars)
2089{ 2065{
2090 struct bnx2x *bp = params->bp; 2066 struct bnx2x *bp = params->bp;
2091 u32 ext_phy_type;
2092 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2093
2094 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port); 2067 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
2095 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2096 /* The PHY reset is controled by GPIO 1 2068 /* The PHY reset is controled by GPIO 1
2097 * Give it 1ms of reset pulse 2069 * Give it 1ms of reset pulse
2098 */ 2070 */
2099 if (vars->phy_flags & PHY_XGXS_FLAG) { 2071 switch (phy->type) {
2100
2101 switch (ext_phy_type) {
2102 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 2072 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2103 DP(NETIF_MSG_LINK, "XGXS Direct\n"); 2073 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2104 break; 2074 break;
@@ -2115,9 +2085,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2115 /* HW reset */ 2085 /* HW reset */
2116 bnx2x_ext_phy_hw_reset(bp, params->port); 2086 bnx2x_ext_phy_hw_reset(bp, params->port);
2117 2087
2118 bnx2x_cl45_write(bp, params->port, 2088 bnx2x_cl45_write(bp, phy,
2119 ext_phy_type,
2120 ext_phy_addr,
2121 MDIO_PMA_DEVAD, 2089 MDIO_PMA_DEVAD,
2122 MDIO_PMA_REG_CTRL, 0xa040); 2090 MDIO_PMA_REG_CTRL, 0xa040);
2123 break; 2091 break;
@@ -2136,9 +2104,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2136 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 2104 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2137 params->port); 2105 params->port);
2138 2106
2139 bnx2x_cl45_write(bp, params->port, 2107 bnx2x_cl45_write(bp, phy,
2140 ext_phy_type,
2141 ext_phy_addr,
2142 MDIO_PMA_DEVAD, 2108 MDIO_PMA_DEVAD,
2143 MDIO_PMA_REG_CTRL, 2109 MDIO_PMA_REG_CTRL,
2144 1<<15); 2110 1<<15);
@@ -2153,9 +2119,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2153 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 2119 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2154 params->port); 2120 params->port);
2155 2121
2156 bnx2x_cl45_write(bp, params->port, 2122 bnx2x_cl45_write(bp, phy,
2157 ext_phy_type,
2158 ext_phy_addr,
2159 MDIO_PMA_DEVAD, 2123 MDIO_PMA_DEVAD,
2160 MDIO_PMA_REG_CTRL, 2124 MDIO_PMA_REG_CTRL,
2161 1<<15); 2125 1<<15);
@@ -2195,9 +2159,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2195 /* HW reset */ 2159 /* HW reset */
2196 bnx2x_ext_phy_hw_reset(bp, params->port); 2160 bnx2x_ext_phy_hw_reset(bp, params->port);
2197 2161
2198 bnx2x_cl45_write(bp, params->port, 2162 bnx2x_cl45_write(bp, phy,
2199 ext_phy_type,
2200 ext_phy_addr,
2201 MDIO_PMA_DEVAD, 2163 MDIO_PMA_DEVAD,
2202 MDIO_PMA_REG_CTRL, 2164 MDIO_PMA_REG_CTRL,
2203 1<<15); 2165 1<<15);
@@ -2211,31 +2173,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
2211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 2173 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2212 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); 2174 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2213 break; 2175 break;
2214
2215 default: 2176 default:
2216 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", 2177 DP(NETIF_MSG_LINK, "BAD phy type 0x%x\n",
2217 params->ext_phy_config); 2178 phy->type);
2218 break; 2179 break;
2219 } 2180 }
2220
2221 } else { /* SerDes */
2222 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2223 switch (ext_phy_type) {
2224 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2225 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2226 break;
2227
2228 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2229 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2230 bnx2x_ext_phy_hw_reset(bp, params->port);
2231 break;
2232
2233 default:
2234 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2235 params->ext_phy_config);
2236 break;
2237 }
2238 }
2239} 2181}
2240 2182
2241static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 2183static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
@@ -2250,59 +2192,49 @@ static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2250} 2192}
2251 2193
2252static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port, 2194static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2253 u32 ext_phy_type, u8 ext_phy_addr, 2195 struct bnx2x_phy *phy,
2254 u32 shmem_base) 2196 u32 shmem_base)
2255{ 2197{
2256 u16 fw_ver1, fw_ver2; 2198 u16 fw_ver1, fw_ver2;
2257 2199
2258 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, 2200 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
2259 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 2201 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2260 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, 2202 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
2261 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 2203 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2262 bnx2x_save_spirom_version(bp, port, shmem_base, 2204 bnx2x_save_spirom_version(bp, port, shmem_base,
2263 (u32)(fw_ver1<<16 | fw_ver2)); 2205 (u32)(fw_ver1<<16 | fw_ver2));
2264} 2206}
2265 2207
2266 2208static void bnx2x_save_8481_spirom_version(struct bnx2x_phy *phy,
2267static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port, 2209 struct link_params *params,
2268 u8 ext_phy_addr, u32 shmem_base) 2210 u32 shmem_base)
2269{ 2211{
2270 u16 val, fw_ver1, fw_ver2, cnt; 2212 u16 val, fw_ver1, fw_ver2, cnt;
2271 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/ 2213 struct bnx2x *bp = params->bp;
2214
2215 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
2272 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 2216 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2273 bnx2x_cl45_write(bp, port, 2217 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
2274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2275 ext_phy_addr, MDIO_PMA_DEVAD,
2276 0xA819, 0x0014); 2218 0xA819, 0x0014);
2277 bnx2x_cl45_write(bp, port, 2219 bnx2x_cl45_write(bp, phy,
2278 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2279 ext_phy_addr,
2280 MDIO_PMA_DEVAD, 2220 MDIO_PMA_DEVAD,
2281 0xA81A, 2221 0xA81A,
2282 0xc200); 2222 0xc200);
2283 bnx2x_cl45_write(bp, port, 2223 bnx2x_cl45_write(bp, phy,
2284 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2285 ext_phy_addr,
2286 MDIO_PMA_DEVAD, 2224 MDIO_PMA_DEVAD,
2287 0xA81B, 2225 0xA81B,
2288 0x0000); 2226 0x0000);
2289 bnx2x_cl45_write(bp, port, 2227 bnx2x_cl45_write(bp, phy,
2290 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2291 ext_phy_addr,
2292 MDIO_PMA_DEVAD, 2228 MDIO_PMA_DEVAD,
2293 0xA81C, 2229 0xA81C,
2294 0x0300); 2230 0x0300);
2295 bnx2x_cl45_write(bp, port, 2231 bnx2x_cl45_write(bp, phy,
2296 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2297 ext_phy_addr,
2298 MDIO_PMA_DEVAD, 2232 MDIO_PMA_DEVAD,
2299 0xA817, 2233 0xA817,
2300 0x0009); 2234 0x0009);
2301 2235
2302 for (cnt = 0; cnt < 100; cnt++) { 2236 for (cnt = 0; cnt < 100; cnt++) {
2303 bnx2x_cl45_read(bp, port, 2237 bnx2x_cl45_read(bp, phy,
2304 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2305 ext_phy_addr,
2306 MDIO_PMA_DEVAD, 2238 MDIO_PMA_DEVAD,
2307 0xA818, 2239 0xA818,
2308 &val); 2240 &val);
@@ -2312,29 +2244,21 @@ static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2312 } 2244 }
2313 if (cnt == 100) { 2245 if (cnt == 100) {
2314 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n"); 2246 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2315 bnx2x_save_spirom_version(bp, port, 2247 bnx2x_save_spirom_version(bp, params->port,
2316 shmem_base, 0); 2248 shmem_base, 0);
2317 return; 2249 return;
2318 } 2250 }
2319 2251
2320 2252
2321 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 2253 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2322 bnx2x_cl45_write(bp, port, 2254 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
2323 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2324 ext_phy_addr, MDIO_PMA_DEVAD,
2325 0xA819, 0x0000); 2255 0xA819, 0x0000);
2326 bnx2x_cl45_write(bp, port, 2256 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
2327 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2328 ext_phy_addr, MDIO_PMA_DEVAD,
2329 0xA81A, 0xc200); 2257 0xA81A, 0xc200);
2330 bnx2x_cl45_write(bp, port, 2258 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
2331 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2332 ext_phy_addr, MDIO_PMA_DEVAD,
2333 0xA817, 0x000A); 2259 0xA817, 0x000A);
2334 for (cnt = 0; cnt < 100; cnt++) { 2260 for (cnt = 0; cnt < 100; cnt++) {
2335 bnx2x_cl45_read(bp, port, 2261 bnx2x_cl45_read(bp, phy,
2336 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2337 ext_phy_addr,
2338 MDIO_PMA_DEVAD, 2262 MDIO_PMA_DEVAD,
2339 0xA818, 2263 0xA818,
2340 &val); 2264 &val);
@@ -2344,58 +2268,53 @@ static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2344 } 2268 }
2345 if (cnt == 100) { 2269 if (cnt == 100) {
2346 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n"); 2270 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2347 bnx2x_save_spirom_version(bp, port, 2271 bnx2x_save_spirom_version(bp, params->port,
2348 shmem_base, 0); 2272 shmem_base, 0);
2349 return; 2273 return;
2350 } 2274 }
2351 2275
2352 /* lower 16 bits of the register SPI_FW_STATUS */ 2276 /* lower 16 bits of the register SPI_FW_STATUS */
2353 bnx2x_cl45_read(bp, port, 2277 bnx2x_cl45_read(bp, phy,
2354 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2355 ext_phy_addr,
2356 MDIO_PMA_DEVAD, 2278 MDIO_PMA_DEVAD,
2357 0xA81B, 2279 0xA81B,
2358 &fw_ver1); 2280 &fw_ver1);
2359 /* upper 16 bits of register SPI_FW_STATUS */ 2281 /* upper 16 bits of register SPI_FW_STATUS */
2360 bnx2x_cl45_read(bp, port, 2282 bnx2x_cl45_read(bp, phy,
2361 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2362 ext_phy_addr,
2363 MDIO_PMA_DEVAD, 2283 MDIO_PMA_DEVAD,
2364 0xA81C, 2284 0xA81C,
2365 &fw_ver2); 2285 &fw_ver2);
2366 2286
2367 bnx2x_save_spirom_version(bp, port, 2287 bnx2x_save_spirom_version(bp, params->port,
2368 shmem_base, (fw_ver2<<16) | fw_ver1); 2288 shmem_base, (fw_ver2<<16) | fw_ver1);
2369} 2289}
2370 2290
2371static void bnx2x_bcm8072_external_rom_boot(struct link_params *params) 2291static void bnx2x_bcm8072_external_rom_boot(struct bnx2x_phy *phy,
2292 struct link_params *params)
2372{ 2293{
2373 struct bnx2x *bp = params->bp; 2294 struct bnx2x *bp = params->bp;
2374 u8 port = params->port; 2295 u8 port = params->port;
2375 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2376 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2377 2296
2378 /* Need to wait 200ms after reset */ 2297 /* Need to wait 200ms after reset */
2379 msleep(200); 2298 msleep(200);
2380 /* Boot port from external ROM 2299 /* Boot port from external ROM
2381 * Set ser_boot_ctl bit in the MISC_CTRL1 register 2300 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2382 */ 2301 */
2383 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2302 bnx2x_cl45_write(bp, phy,
2384 MDIO_PMA_DEVAD, 2303 MDIO_PMA_DEVAD,
2385 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 2304 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2386 2305
2387 /* Reset internal microprocessor */ 2306 /* Reset internal microprocessor */
2388 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2307 bnx2x_cl45_write(bp, phy,
2389 MDIO_PMA_DEVAD, 2308 MDIO_PMA_DEVAD,
2390 MDIO_PMA_REG_GEN_CTRL, 2309 MDIO_PMA_REG_GEN_CTRL,
2391 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2310 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2392 /* set micro reset = 0 */ 2311 /* set micro reset = 0 */
2393 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2312 bnx2x_cl45_write(bp, phy,
2394 MDIO_PMA_DEVAD, 2313 MDIO_PMA_DEVAD,
2395 MDIO_PMA_REG_GEN_CTRL, 2314 MDIO_PMA_REG_GEN_CTRL,
2396 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2315 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2397 /* Reset internal microprocessor */ 2316 /* Reset internal microprocessor */
2398 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2317 bnx2x_cl45_write(bp, phy,
2399 MDIO_PMA_DEVAD, 2318 MDIO_PMA_DEVAD,
2400 MDIO_PMA_REG_GEN_CTRL, 2319 MDIO_PMA_REG_GEN_CTRL,
2401 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2320 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2403,30 +2322,24 @@ static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2403 msleep(100); 2322 msleep(100);
2404 2323
2405 /* Clear ser_boot_ctl bit */ 2324 /* Clear ser_boot_ctl bit */
2406 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2325 bnx2x_cl45_write(bp, phy,
2407 MDIO_PMA_DEVAD, 2326 MDIO_PMA_DEVAD,
2408 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 2327 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2409 /* Wait 100ms */ 2328 /* Wait 100ms */
2410 msleep(100); 2329 msleep(100);
2411 2330
2412 bnx2x_save_bcm_spirom_ver(bp, port, 2331 bnx2x_save_bcm_spirom_ver(bp, port,
2413 ext_phy_type, 2332 phy,
2414 ext_phy_addr,
2415 params->shmem_base); 2333 params->shmem_base);
2416} 2334}
2417 2335
2418static u8 bnx2x_8073_is_snr_needed(struct link_params *params) 2336static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
2419{ 2337{
2420 /* This is only required for 8073A1, version 102 only */ 2338 /* This is only required for 8073A1, version 102 only */
2421
2422 struct bnx2x *bp = params->bp;
2423 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2424 u16 val; 2339 u16 val;
2425 2340
2426 /* Read 8073 HW revision*/ 2341 /* Read 8073 HW revision*/
2427 bnx2x_cl45_read(bp, params->port, 2342 bnx2x_cl45_read(bp, phy,
2428 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2429 ext_phy_addr,
2430 MDIO_PMA_DEVAD, 2343 MDIO_PMA_DEVAD,
2431 MDIO_PMA_REG_8073_CHIP_REV, &val); 2344 MDIO_PMA_REG_8073_CHIP_REV, &val);
2432 2345
@@ -2435,9 +2348,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2435 return 0; 2348 return 0;
2436 } 2349 }
2437 2350
2438 bnx2x_cl45_read(bp, params->port, 2351 bnx2x_cl45_read(bp, phy,
2439 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2440 ext_phy_addr,
2441 MDIO_PMA_DEVAD, 2352 MDIO_PMA_DEVAD,
2442 MDIO_PMA_REG_ROM_VER2, &val); 2353 MDIO_PMA_REG_ROM_VER2, &val);
2443 2354
@@ -2447,16 +2358,11 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2447 2358
2448 return 1; 2359 return 1;
2449} 2360}
2450 2361static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
2451static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2452{ 2362{
2453 struct bnx2x *bp = params->bp;
2454 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2455 u16 val, cnt, cnt1 ; 2363 u16 val, cnt, cnt1 ;
2456 2364
2457 bnx2x_cl45_read(bp, params->port, 2365 bnx2x_cl45_read(bp, phy,
2458 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2459 ext_phy_addr,
2460 MDIO_PMA_DEVAD, 2366 MDIO_PMA_DEVAD,
2461 MDIO_PMA_REG_8073_CHIP_REV, &val); 2367 MDIO_PMA_REG_8073_CHIP_REV, &val);
2462 2368
@@ -2470,9 +2376,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2470 poll Dev1, Reg $C820: */ 2376 poll Dev1, Reg $C820: */
2471 2377
2472 for (cnt = 0; cnt < 1000; cnt++) { 2378 for (cnt = 0; cnt < 1000; cnt++) {
2473 bnx2x_cl45_read(bp, params->port, 2379 bnx2x_cl45_read(bp, phy,
2474 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2475 ext_phy_addr,
2476 MDIO_PMA_DEVAD, 2380 MDIO_PMA_DEVAD,
2477 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 2381 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2478 &val); 2382 &val);
@@ -2489,9 +2393,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2489 XAUI workaround has completed), 2393 XAUI workaround has completed),
2490 then continue on with system initialization.*/ 2394 then continue on with system initialization.*/
2491 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 2395 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2492 bnx2x_cl45_read(bp, params->port, 2396 bnx2x_cl45_read(bp, phy,
2493 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2494 ext_phy_addr,
2495 MDIO_PMA_DEVAD, 2397 MDIO_PMA_DEVAD,
2496 MDIO_PMA_REG_8073_XAUI_WA, &val); 2398 MDIO_PMA_REG_8073_XAUI_WA, &val);
2497 if (val & (1<<15)) { 2399 if (val & (1<<15)) {
@@ -2509,46 +2411,35 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2509 return -EINVAL; 2411 return -EINVAL;
2510} 2412}
2511 2413
2512static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port, 2414static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
2513 u8 ext_phy_addr, 2415 struct bnx2x_phy *phy,
2514 u32 ext_phy_type, 2416 u8 port, u32 shmem_base)
2515 u32 shmem_base)
2516{ 2417{
2517 /* Boot port from external ROM */ 2418 /* Boot port from external ROM */
2518 /* EDC grst */ 2419 /* EDC grst */
2519 bnx2x_cl45_write(bp, port, 2420 bnx2x_cl45_write(bp, phy,
2520 ext_phy_type,
2521 ext_phy_addr,
2522 MDIO_PMA_DEVAD, 2421 MDIO_PMA_DEVAD,
2523 MDIO_PMA_REG_GEN_CTRL, 2422 MDIO_PMA_REG_GEN_CTRL,
2524 0x0001); 2423 0x0001);
2525 2424
2526 /* ucode reboot and rst */ 2425 /* ucode reboot and rst */
2527 bnx2x_cl45_write(bp, port, 2426 bnx2x_cl45_write(bp, phy,
2528 ext_phy_type,
2529 ext_phy_addr,
2530 MDIO_PMA_DEVAD, 2427 MDIO_PMA_DEVAD,
2531 MDIO_PMA_REG_GEN_CTRL, 2428 MDIO_PMA_REG_GEN_CTRL,
2532 0x008c); 2429 0x008c);
2533 2430
2534 bnx2x_cl45_write(bp, port, 2431 bnx2x_cl45_write(bp, phy,
2535 ext_phy_type,
2536 ext_phy_addr,
2537 MDIO_PMA_DEVAD, 2432 MDIO_PMA_DEVAD,
2538 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 2433 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2539 2434
2540 /* Reset internal microprocessor */ 2435 /* Reset internal microprocessor */
2541 bnx2x_cl45_write(bp, port, 2436 bnx2x_cl45_write(bp, phy,
2542 ext_phy_type,
2543 ext_phy_addr,
2544 MDIO_PMA_DEVAD, 2437 MDIO_PMA_DEVAD,
2545 MDIO_PMA_REG_GEN_CTRL, 2438 MDIO_PMA_REG_GEN_CTRL,
2546 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2439 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2547 2440
2548 /* Release srst bit */ 2441 /* Release srst bit */
2549 bnx2x_cl45_write(bp, port, 2442 bnx2x_cl45_write(bp, phy,
2550 ext_phy_type,
2551 ext_phy_addr,
2552 MDIO_PMA_DEVAD, 2443 MDIO_PMA_DEVAD,
2553 MDIO_PMA_REG_GEN_CTRL, 2444 MDIO_PMA_REG_GEN_CTRL,
2554 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2445 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2557,64 +2448,36 @@ static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2557 msleep(120); 2448 msleep(120);
2558 2449
2559 /* Clear ser_boot_ctl bit */ 2450 /* Clear ser_boot_ctl bit */
2560 bnx2x_cl45_write(bp, port, 2451 bnx2x_cl45_write(bp, phy,
2561 ext_phy_type,
2562 ext_phy_addr,
2563 MDIO_PMA_DEVAD, 2452 MDIO_PMA_DEVAD,
2564 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 2453 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2565 2454 bnx2x_save_bcm_spirom_ver(bp, port, phy, shmem_base);
2566 bnx2x_save_bcm_spirom_ver(bp, port,
2567 ext_phy_type,
2568 ext_phy_addr,
2569 shmem_base);
2570} 2455}
2571 2456
2572static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port, 2457static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
2573 u8 ext_phy_addr, 2458 struct link_params *params)
2574 u32 shmem_base)
2575{
2576 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2577 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2578 shmem_base);
2579}
2580
2581static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2582 u8 ext_phy_addr,
2583 u32 shmem_base)
2584{
2585 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2586 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2587 shmem_base);
2588
2589}
2590
2591static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2592{ 2459{
2593 struct bnx2x *bp = params->bp; 2460 struct bnx2x *bp = params->bp;
2594 u8 port = params->port;
2595 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2596 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2597
2598 /* Need to wait 100ms after reset */ 2461 /* Need to wait 100ms after reset */
2599 msleep(100); 2462 msleep(100);
2600 2463
2601 /* Micro controller re-boot */ 2464 /* Micro controller re-boot */
2602 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2465 bnx2x_cl45_write(bp, phy,
2603 MDIO_PMA_DEVAD, 2466 MDIO_PMA_DEVAD,
2604 MDIO_PMA_REG_GEN_CTRL, 2467 MDIO_PMA_REG_GEN_CTRL,
2605 0x018B); 2468 0x018B);
2606 2469
2607 /* Set soft reset */ 2470 /* Set soft reset */
2608 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2471 bnx2x_cl45_write(bp, phy,
2609 MDIO_PMA_DEVAD, 2472 MDIO_PMA_DEVAD,
2610 MDIO_PMA_REG_GEN_CTRL, 2473 MDIO_PMA_REG_GEN_CTRL,
2611 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2474 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2612 2475
2613 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2476 bnx2x_cl45_write(bp, phy,
2614 MDIO_PMA_DEVAD, 2477 MDIO_PMA_DEVAD,
2615 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 2478 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2616 2479
2617 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2480 bnx2x_cl45_write(bp, phy,
2618 MDIO_PMA_DEVAD, 2481 MDIO_PMA_DEVAD,
2619 MDIO_PMA_REG_GEN_CTRL, 2482 MDIO_PMA_REG_GEN_CTRL,
2620 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2483 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2623,29 +2486,25 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2623 msleep(150); 2486 msleep(150);
2624 2487
2625 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 2488 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2626 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2489 bnx2x_cl45_write(bp, phy,
2627 MDIO_PMA_DEVAD, 2490 MDIO_PMA_DEVAD,
2628 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 2491 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2629 2492
2630 msleep(200); 2493 msleep(200);
2631 bnx2x_save_bcm_spirom_ver(bp, port, 2494 bnx2x_save_bcm_spirom_ver(bp, params->port,
2632 ext_phy_type, 2495 phy,
2633 ext_phy_addr,
2634 params->shmem_base); 2496 params->shmem_base);
2635} 2497}
2636 2498
2637static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port, 2499static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
2638 u32 ext_phy_type, u8 ext_phy_addr, 2500 struct bnx2x_phy *phy,
2639 u8 tx_en) 2501 u8 tx_en)
2640{ 2502{
2641 u16 val; 2503 u16 val;
2642 2504
2643 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n", 2505 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x\n", tx_en);
2644 tx_en, port);
2645 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 2506 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2646 bnx2x_cl45_read(bp, port, 2507 bnx2x_cl45_read(bp, phy,
2647 ext_phy_type,
2648 ext_phy_addr,
2649 MDIO_PMA_DEVAD, 2508 MDIO_PMA_DEVAD,
2650 MDIO_PMA_REG_PHY_IDENTIFIER, 2509 MDIO_PMA_REG_PHY_IDENTIFIER,
2651 &val); 2510 &val);
@@ -2655,58 +2514,42 @@ static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2655 else 2514 else
2656 val |= (1<<15); 2515 val |= (1<<15);
2657 2516
2658 bnx2x_cl45_write(bp, port, 2517 bnx2x_cl45_write(bp, phy,
2659 ext_phy_type,
2660 ext_phy_addr,
2661 MDIO_PMA_DEVAD, 2518 MDIO_PMA_DEVAD,
2662 MDIO_PMA_REG_PHY_IDENTIFIER, 2519 MDIO_PMA_REG_PHY_IDENTIFIER,
2663 val); 2520 val);
2664} 2521}
2665 2522
2666static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params, 2523static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2524 struct link_params *params,
2667 u16 addr, u8 byte_cnt, u8 *o_buf) 2525 u16 addr, u8 byte_cnt, u8 *o_buf)
2668{ 2526{
2669 struct bnx2x *bp = params->bp; 2527 struct bnx2x *bp = params->bp;
2670 u16 val = 0; 2528 u16 val = 0;
2671 u16 i; 2529 u16 i;
2672 u8 port = params->port;
2673 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2674 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2675
2676 if (byte_cnt > 16) { 2530 if (byte_cnt > 16) {
2677 DP(NETIF_MSG_LINK, "Reading from eeprom is" 2531 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2678 " is limited to 0xf\n"); 2532 " is limited to 0xf\n");
2679 return -EINVAL; 2533 return -EINVAL;
2680 } 2534 }
2681 /* Set the read command byte count */ 2535 /* Set the read command byte count */
2682 bnx2x_cl45_write(bp, port, 2536 bnx2x_cl45_write(bp, phy,
2683 ext_phy_type, 2537 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2684 ext_phy_addr,
2685 MDIO_PMA_DEVAD,
2686 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2687 (byte_cnt | 0xa000)); 2538 (byte_cnt | 0xa000));
2688 2539
2689 /* Set the read command address */ 2540 /* Set the read command address */
2690 bnx2x_cl45_write(bp, port, 2541 bnx2x_cl45_write(bp, phy,
2691 ext_phy_type, 2542 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2692 ext_phy_addr,
2693 MDIO_PMA_DEVAD,
2694 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2695 addr); 2543 addr);
2696 2544
2697 /* Activate read command */ 2545 /* Activate read command */
2698 bnx2x_cl45_write(bp, port, 2546 bnx2x_cl45_write(bp, phy,
2699 ext_phy_type, 2547 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2700 ext_phy_addr,
2701 MDIO_PMA_DEVAD,
2702 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2703 0x2c0f); 2548 0x2c0f);
2704 2549
2705 /* Wait up to 500us for command complete status */ 2550 /* Wait up to 500us for command complete status */
2706 for (i = 0; i < 100; i++) { 2551 for (i = 0; i < 100; i++) {
2707 bnx2x_cl45_read(bp, port, 2552 bnx2x_cl45_read(bp, phy,
2708 ext_phy_type,
2709 ext_phy_addr,
2710 MDIO_PMA_DEVAD, 2553 MDIO_PMA_DEVAD,
2711 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 2554 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2712 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 2555 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
@@ -2725,36 +2568,30 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2725 2568
2726 /* Read the buffer */ 2569 /* Read the buffer */
2727 for (i = 0; i < byte_cnt; i++) { 2570 for (i = 0; i < byte_cnt; i++) {
2728 bnx2x_cl45_read(bp, port, 2571 bnx2x_cl45_read(bp, phy,
2729 ext_phy_type,
2730 ext_phy_addr,
2731 MDIO_PMA_DEVAD, 2572 MDIO_PMA_DEVAD,
2732 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 2573 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2733 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 2574 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2734 } 2575 }
2735 2576
2736 for (i = 0; i < 100; i++) { 2577 for (i = 0; i < 100; i++) {
2737 bnx2x_cl45_read(bp, port, 2578 bnx2x_cl45_read(bp, phy,
2738 ext_phy_type,
2739 ext_phy_addr,
2740 MDIO_PMA_DEVAD, 2579 MDIO_PMA_DEVAD,
2741 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 2580 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2742 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 2581 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2743 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 2582 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2744 return 0;; 2583 return 0;
2745 msleep(1); 2584 msleep(1);
2746 } 2585 }
2747 return -EINVAL; 2586 return -EINVAL;
2748} 2587}
2749 2588
2750static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params, 2589static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2590 struct link_params *params,
2751 u16 addr, u8 byte_cnt, u8 *o_buf) 2591 u16 addr, u8 byte_cnt, u8 *o_buf)
2752{ 2592{
2753 struct bnx2x *bp = params->bp; 2593 struct bnx2x *bp = params->bp;
2754 u16 val, i; 2594 u16 val, i;
2755 u8 port = params->port;
2756 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2757 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2758 2595
2759 if (byte_cnt > 16) { 2596 if (byte_cnt > 16) {
2760 DP(NETIF_MSG_LINK, "Reading from eeprom is" 2597 DP(NETIF_MSG_LINK, "Reading from eeprom is"
@@ -2763,40 +2600,30 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2763 } 2600 }
2764 2601
2765 /* Need to read from 1.8000 to clear it */ 2602 /* Need to read from 1.8000 to clear it */
2766 bnx2x_cl45_read(bp, port, 2603 bnx2x_cl45_read(bp, phy,
2767 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2768 ext_phy_addr,
2769 MDIO_PMA_DEVAD, 2604 MDIO_PMA_DEVAD,
2770 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 2605 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2771 &val); 2606 &val);
2772 2607
2773 /* Set the read command byte count */ 2608 /* Set the read command byte count */
2774 bnx2x_cl45_write(bp, port, 2609 bnx2x_cl45_write(bp, phy,
2775 ext_phy_type,
2776 ext_phy_addr,
2777 MDIO_PMA_DEVAD, 2610 MDIO_PMA_DEVAD,
2778 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 2611 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2779 ((byte_cnt < 2) ? 2 : byte_cnt)); 2612 ((byte_cnt < 2) ? 2 : byte_cnt));
2780 2613
2781 /* Set the read command address */ 2614 /* Set the read command address */
2782 bnx2x_cl45_write(bp, port, 2615 bnx2x_cl45_write(bp, phy,
2783 ext_phy_type,
2784 ext_phy_addr,
2785 MDIO_PMA_DEVAD, 2616 MDIO_PMA_DEVAD,
2786 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 2617 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2787 addr); 2618 addr);
2788 /* Set the destination address */ 2619 /* Set the destination address */
2789 bnx2x_cl45_write(bp, port, 2620 bnx2x_cl45_write(bp, phy,
2790 ext_phy_type,
2791 ext_phy_addr,
2792 MDIO_PMA_DEVAD, 2621 MDIO_PMA_DEVAD,
2793 0x8004, 2622 0x8004,
2794 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 2623 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2795 2624
2796 /* Activate read command */ 2625 /* Activate read command */
2797 bnx2x_cl45_write(bp, port, 2626 bnx2x_cl45_write(bp, phy,
2798 ext_phy_type,
2799 ext_phy_addr,
2800 MDIO_PMA_DEVAD, 2627 MDIO_PMA_DEVAD,
2801 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 2628 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2802 0x8002); 2629 0x8002);
@@ -2806,9 +2633,7 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2806 2633
2807 /* Wait up to 500us for command complete status */ 2634 /* Wait up to 500us for command complete status */
2808 for (i = 0; i < 100; i++) { 2635 for (i = 0; i < 100; i++) {
2809 bnx2x_cl45_read(bp, port, 2636 bnx2x_cl45_read(bp, phy,
2810 ext_phy_type,
2811 ext_phy_addr,
2812 MDIO_PMA_DEVAD, 2637 MDIO_PMA_DEVAD,
2813 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 2638 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2814 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 2639 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
@@ -2827,18 +2652,14 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2827 2652
2828 /* Read the buffer */ 2653 /* Read the buffer */
2829 for (i = 0; i < byte_cnt; i++) { 2654 for (i = 0; i < byte_cnt; i++) {
2830 bnx2x_cl45_read(bp, port, 2655 bnx2x_cl45_read(bp, phy,
2831 ext_phy_type,
2832 ext_phy_addr,
2833 MDIO_PMA_DEVAD, 2656 MDIO_PMA_DEVAD,
2834 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 2657 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2835 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 2658 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2836 } 2659 }
2837 2660
2838 for (i = 0; i < 100; i++) { 2661 for (i = 0; i < 100; i++) {
2839 bnx2x_cl45_read(bp, port, 2662 bnx2x_cl45_read(bp, phy,
2840 ext_phy_type,
2841 ext_phy_addr,
2842 MDIO_PMA_DEVAD, 2663 MDIO_PMA_DEVAD,
2843 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 2664 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2844 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 2665 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
@@ -2850,21 +2671,21 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2850 return -EINVAL; 2671 return -EINVAL;
2851} 2672}
2852 2673
2853u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr, 2674u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
2675 struct link_params *params, u16 addr,
2854 u8 byte_cnt, u8 *o_buf) 2676 u8 byte_cnt, u8 *o_buf)
2855{ 2677{
2856 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 2678 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2857 2679 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
2858 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2859 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2860 byte_cnt, o_buf); 2680 byte_cnt, o_buf);
2861 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) 2681 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2862 return bnx2x_8727_read_sfp_module_eeprom(params, addr, 2682 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
2863 byte_cnt, o_buf); 2683 byte_cnt, o_buf);
2864 return -EINVAL; 2684 return -EINVAL;
2865} 2685}
2866 2686
2867static u8 bnx2x_get_edc_mode(struct link_params *params, 2687static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
2688 struct link_params *params,
2868 u16 *edc_mode) 2689 u16 *edc_mode)
2869{ 2690{
2870 struct bnx2x *bp = params->bp; 2691 struct bnx2x *bp = params->bp;
@@ -2872,7 +2693,7 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
2872 *edc_mode = EDC_MODE_LIMITING; 2693 *edc_mode = EDC_MODE_LIMITING;
2873 2694
2874 /* First check for copper cable */ 2695 /* First check for copper cable */
2875 if (bnx2x_read_sfp_module_eeprom(params, 2696 if (bnx2x_read_sfp_module_eeprom(phy, params,
2876 SFP_EEPROM_CON_TYPE_ADDR, 2697 SFP_EEPROM_CON_TYPE_ADDR,
2877 1, 2698 1,
2878 &val) != 0) { 2699 &val) != 0) {
@@ -2887,7 +2708,7 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
2887 2708
2888 /* Check if its active cable( includes SFP+ module) 2709 /* Check if its active cable( includes SFP+ module)
2889 of passive cable*/ 2710 of passive cable*/
2890 if (bnx2x_read_sfp_module_eeprom(params, 2711 if (bnx2x_read_sfp_module_eeprom(phy, params,
2891 SFP_EEPROM_FC_TX_TECH_ADDR, 2712 SFP_EEPROM_FC_TX_TECH_ADDR,
2892 1, 2713 1,
2893 &copper_module_type) != 2714 &copper_module_type) !=
@@ -2927,7 +2748,7 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
2927 2748
2928 if (check_limiting_mode) { 2749 if (check_limiting_mode) {
2929 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 2750 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2930 if (bnx2x_read_sfp_module_eeprom(params, 2751 if (bnx2x_read_sfp_module_eeprom(phy, params,
2931 SFP_EEPROM_OPTIONS_ADDR, 2752 SFP_EEPROM_OPTIONS_ADDR,
2932 SFP_EEPROM_OPTIONS_SIZE, 2753 SFP_EEPROM_OPTIONS_SIZE,
2933 options) != 0) { 2754 options) != 0) {
@@ -2943,10 +2764,10 @@ static u8 bnx2x_get_edc_mode(struct link_params *params,
2943 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 2764 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
2944 return 0; 2765 return 0;
2945} 2766}
2946
2947/* This function read the relevant field from the module ( SFP+ ), 2767/* This function read the relevant field from the module ( SFP+ ),
2948 and verify it is compliant with this board */ 2768 and verify it is compliant with this board */
2949static u8 bnx2x_verify_sfp_module(struct link_params *params) 2769static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
2770 struct link_params *params)
2950{ 2771{
2951 struct bnx2x *bp = params->bp; 2772 struct bnx2x *bp = params->bp;
2952 u32 val; 2773 u32 val;
@@ -2978,14 +2799,14 @@ static u8 bnx2x_verify_sfp_module(struct link_params *params)
2978 } 2799 }
2979 2800
2980 /* format the warning message */ 2801 /* format the warning message */
2981 if (bnx2x_read_sfp_module_eeprom(params, 2802 if (bnx2x_read_sfp_module_eeprom(phy, params,
2982 SFP_EEPROM_VENDOR_NAME_ADDR, 2803 SFP_EEPROM_VENDOR_NAME_ADDR,
2983 SFP_EEPROM_VENDOR_NAME_SIZE, 2804 SFP_EEPROM_VENDOR_NAME_SIZE,
2984 (u8 *)vendor_name)) 2805 (u8 *)vendor_name))
2985 vendor_name[0] = '\0'; 2806 vendor_name[0] = '\0';
2986 else 2807 else
2987 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 2808 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2988 if (bnx2x_read_sfp_module_eeprom(params, 2809 if (bnx2x_read_sfp_module_eeprom(phy, params,
2989 SFP_EEPROM_PART_NO_ADDR, 2810 SFP_EEPROM_PART_NO_ADDR,
2990 SFP_EEPROM_PART_NO_SIZE, 2811 SFP_EEPROM_PART_NO_SIZE,
2991 (u8 *)vendor_pn)) 2812 (u8 *)vendor_pn))
@@ -2993,22 +2814,19 @@ static u8 bnx2x_verify_sfp_module(struct link_params *params)
2993 else 2814 else
2994 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 2815 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
2995 2816
2996 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected, Port %d from %s part number %s\n", 2817 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
2818 " Port %d from %s part number %s\n",
2997 params->port, vendor_name, vendor_pn); 2819 params->port, vendor_name, vendor_pn);
2998 return -EINVAL; 2820 return -EINVAL;
2999} 2821}
3000 2822
3001static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params, 2823static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
2824 struct bnx2x_phy *phy,
3002 u16 edc_mode) 2825 u16 edc_mode)
3003{ 2826{
3004 struct bnx2x *bp = params->bp;
3005 u8 port = params->port;
3006 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3007 u16 cur_limiting_mode; 2827 u16 cur_limiting_mode;
3008 2828
3009 bnx2x_cl45_read(bp, port, 2829 bnx2x_cl45_read(bp, phy,
3010 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3011 ext_phy_addr,
3012 MDIO_PMA_DEVAD, 2830 MDIO_PMA_DEVAD,
3013 MDIO_PMA_REG_ROM_VER2, 2831 MDIO_PMA_REG_ROM_VER2,
3014 &cur_limiting_mode); 2832 &cur_limiting_mode);
@@ -3018,9 +2836,7 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
3018 if (edc_mode == EDC_MODE_LIMITING) { 2836 if (edc_mode == EDC_MODE_LIMITING) {
3019 DP(NETIF_MSG_LINK, 2837 DP(NETIF_MSG_LINK,
3020 "Setting LIMITING MODE\n"); 2838 "Setting LIMITING MODE\n");
3021 bnx2x_cl45_write(bp, port, 2839 bnx2x_cl45_write(bp, phy,
3022 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3023 ext_phy_addr,
3024 MDIO_PMA_DEVAD, 2840 MDIO_PMA_DEVAD,
3025 MDIO_PMA_REG_ROM_VER2, 2841 MDIO_PMA_REG_ROM_VER2,
3026 EDC_MODE_LIMITING); 2842 EDC_MODE_LIMITING);
@@ -3034,27 +2850,19 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
3034 if (cur_limiting_mode != EDC_MODE_LIMITING) 2850 if (cur_limiting_mode != EDC_MODE_LIMITING)
3035 return 0; 2851 return 0;
3036 2852
3037 bnx2x_cl45_write(bp, port, 2853 bnx2x_cl45_write(bp, phy,
3038 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3039 ext_phy_addr,
3040 MDIO_PMA_DEVAD, 2854 MDIO_PMA_DEVAD,
3041 MDIO_PMA_REG_LRM_MODE, 2855 MDIO_PMA_REG_LRM_MODE,
3042 0); 2856 0);
3043 bnx2x_cl45_write(bp, port, 2857 bnx2x_cl45_write(bp, phy,
3044 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3045 ext_phy_addr,
3046 MDIO_PMA_DEVAD, 2858 MDIO_PMA_DEVAD,
3047 MDIO_PMA_REG_ROM_VER2, 2859 MDIO_PMA_REG_ROM_VER2,
3048 0x128); 2860 0x128);
3049 bnx2x_cl45_write(bp, port, 2861 bnx2x_cl45_write(bp, phy,
3050 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3051 ext_phy_addr,
3052 MDIO_PMA_DEVAD, 2862 MDIO_PMA_DEVAD,
3053 MDIO_PMA_REG_MISC_CTRL0, 2863 MDIO_PMA_REG_MISC_CTRL0,
3054 0x4008); 2864 0x4008);
3055 bnx2x_cl45_write(bp, port, 2865 bnx2x_cl45_write(bp, phy,
3056 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3057 ext_phy_addr,
3058 MDIO_PMA_DEVAD, 2866 MDIO_PMA_DEVAD,
3059 MDIO_PMA_REG_LRM_MODE, 2867 MDIO_PMA_REG_LRM_MODE,
3060 0xaaaa); 2868 0xaaaa);
@@ -3062,46 +2870,33 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
3062 return 0; 2870 return 0;
3063} 2871}
3064 2872
3065static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params, 2873static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
2874 struct bnx2x_phy *phy,
3066 u16 edc_mode) 2875 u16 edc_mode)
3067{ 2876{
3068 struct bnx2x *bp = params->bp;
3069 u8 port = params->port;
3070 u16 phy_identifier; 2877 u16 phy_identifier;
3071 u16 rom_ver2_val; 2878 u16 rom_ver2_val;
3072 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 2879 bnx2x_cl45_read(bp, phy,
3073
3074 bnx2x_cl45_read(bp, port,
3075 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3076 ext_phy_addr,
3077 MDIO_PMA_DEVAD, 2880 MDIO_PMA_DEVAD,
3078 MDIO_PMA_REG_PHY_IDENTIFIER, 2881 MDIO_PMA_REG_PHY_IDENTIFIER,
3079 &phy_identifier); 2882 &phy_identifier);
3080 2883
3081 bnx2x_cl45_write(bp, port, 2884 bnx2x_cl45_write(bp, phy,
3082 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3083 ext_phy_addr,
3084 MDIO_PMA_DEVAD, 2885 MDIO_PMA_DEVAD,
3085 MDIO_PMA_REG_PHY_IDENTIFIER, 2886 MDIO_PMA_REG_PHY_IDENTIFIER,
3086 (phy_identifier & ~(1<<9))); 2887 (phy_identifier & ~(1<<9)));
3087 2888
3088 bnx2x_cl45_read(bp, port, 2889 bnx2x_cl45_read(bp, phy,
3089 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3090 ext_phy_addr,
3091 MDIO_PMA_DEVAD, 2890 MDIO_PMA_DEVAD,
3092 MDIO_PMA_REG_ROM_VER2, 2891 MDIO_PMA_REG_ROM_VER2,
3093 &rom_ver2_val); 2892 &rom_ver2_val);
3094 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 2893 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3095 bnx2x_cl45_write(bp, port, 2894 bnx2x_cl45_write(bp, phy,
3096 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3097 ext_phy_addr,
3098 MDIO_PMA_DEVAD, 2895 MDIO_PMA_DEVAD,
3099 MDIO_PMA_REG_ROM_VER2, 2896 MDIO_PMA_REG_ROM_VER2,
3100 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 2897 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
3101 2898
3102 bnx2x_cl45_write(bp, port, 2899 bnx2x_cl45_write(bp, phy,
3103 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3104 ext_phy_addr,
3105 MDIO_PMA_DEVAD, 2900 MDIO_PMA_DEVAD,
3106 MDIO_PMA_REG_PHY_IDENTIFIER, 2901 MDIO_PMA_REG_PHY_IDENTIFIER,
3107 (phy_identifier | (1<<9))); 2902 (phy_identifier | (1<<9)));
@@ -3110,7 +2905,9 @@ static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
3110} 2905}
3111 2906
3112 2907
3113static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params) 2908static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
2909 struct link_params *params)
2910
3114{ 2911{
3115 u8 val; 2912 u8 val;
3116 struct bnx2x *bp = params->bp; 2913 struct bnx2x *bp = params->bp;
@@ -3118,7 +2915,7 @@ static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3118 /* Initialization time after hot-plug may take up to 300ms for some 2915 /* Initialization time after hot-plug may take up to 300ms for some
3119 phys type ( e.g. JDSU ) */ 2916 phys type ( e.g. JDSU ) */
3120 for (timeout = 0; timeout < 60; timeout++) { 2917 for (timeout = 0; timeout < 60; timeout++) {
3121 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val) 2918 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
3122 == 0) { 2919 == 0) {
3123 DP(NETIF_MSG_LINK, "SFP+ module initialization " 2920 DP(NETIF_MSG_LINK, "SFP+ module initialization "
3124 "took %d ms\n", timeout * 5); 2921 "took %d ms\n", timeout * 5);
@@ -3131,10 +2928,10 @@ static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3131 2928
3132static void bnx2x_8727_power_module(struct bnx2x *bp, 2929static void bnx2x_8727_power_module(struct bnx2x *bp,
3133 struct link_params *params, 2930 struct link_params *params,
3134 u8 ext_phy_addr, u8 is_power_up) { 2931 struct bnx2x_phy *phy,
2932 u8 is_power_up) {
3135 /* Make sure GPIOs are not using for LED mode */ 2933 /* Make sure GPIOs are not using for LED mode */
3136 u16 val; 2934 u16 val;
3137 u8 port = params->port;
3138 /* 2935 /*
3139 * In the GPIO register, bit 4 is use to detemine if the GPIOs are 2936 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3140 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 2937 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
@@ -3160,21 +2957,19 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
3160 */ 2957 */
3161 val = ((!(is_power_up)) << 1); 2958 val = ((!(is_power_up)) << 1);
3162 2959
3163 bnx2x_cl45_write(bp, port, 2960 bnx2x_cl45_write(bp, phy,
3164 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3165 ext_phy_addr,
3166 MDIO_PMA_DEVAD, 2961 MDIO_PMA_DEVAD,
3167 MDIO_PMA_REG_8727_GPIO_CTRL, 2962 MDIO_PMA_REG_8727_GPIO_CTRL,
3168 val); 2963 val);
3169} 2964}
3170 2965
3171static u8 bnx2x_sfp_module_detection(struct link_params *params) 2966static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
2967 struct link_params *params)
3172{ 2968{
3173 struct bnx2x *bp = params->bp; 2969 struct bnx2x *bp = params->bp;
3174 u16 edc_mode; 2970 u16 edc_mode;
3175 u8 rc = 0; 2971 u8 rc = 0;
3176 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 2972
3177 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3178 u32 val = REG_RD(bp, params->shmem_base + 2973 u32 val = REG_RD(bp, params->shmem_base +
3179 offsetof(struct shmem_region, dev_info. 2974 offsetof(struct shmem_region, dev_info.
3180 port_feature_config[params->port].config)); 2975 port_feature_config[params->port].config));
@@ -3182,10 +2977,10 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
3182 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 2977 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
3183 params->port); 2978 params->port);
3184 2979
3185 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) { 2980 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
3186 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 2981 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
3187 return -EINVAL; 2982 return -EINVAL;
3188 } else if (bnx2x_verify_sfp_module(params) != 2983 } else if (bnx2x_verify_sfp_module(phy, params) !=
3189 0) { 2984 0) {
3190 /* check SFP+ module compatibility */ 2985 /* check SFP+ module compatibility */
3191 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 2986 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
@@ -3194,13 +2989,12 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
3194 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 2989 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3195 MISC_REGISTERS_GPIO_HIGH, 2990 MISC_REGISTERS_GPIO_HIGH,
3196 params->port); 2991 params->port);
3197 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) && 2992 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3198 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 2993 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3199 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { 2994 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3200 /* Shutdown SFP+ module */ 2995 /* Shutdown SFP+ module */
3201 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 2996 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3202 bnx2x_8727_power_module(bp, params, 2997 bnx2x_8727_power_module(bp, params, phy, 0);
3203 ext_phy_addr, 0);
3204 return rc; 2998 return rc;
3205 } 2999 }
3206 } else { 3000 } else {
@@ -3212,15 +3006,15 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
3212 } 3006 }
3213 3007
3214 /* power up the SFP module */ 3008 /* power up the SFP module */
3215 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) 3009 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3216 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1); 3010 bnx2x_8727_power_module(bp, params, phy, 1);
3217 3011
3218 /* Check and set limiting mode / LRM mode on 8726. 3012 /* Check and set limiting mode / LRM mode on 8726.
3219 On 8727 it is done automatically */ 3013 On 8727 it is done automatically */
3220 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) 3014 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3221 bnx2x_bcm8726_set_limiting_mode(params, edc_mode); 3015 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
3222 else 3016 else
3223 bnx2x_bcm8727_set_limiting_mode(params, edc_mode); 3017 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
3224 /* 3018 /*
3225 * Enable transmit for this module if the module is approved, or 3019 * Enable transmit for this module if the module is approved, or
3226 * if unapproved modules should also enable the Tx laser 3020 * if unapproved modules should also enable the Tx laser
@@ -3228,11 +3022,9 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
3228 if (rc == 0 || 3022 if (rc == 0 ||
3229 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 3023 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3230 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 3024 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3231 bnx2x_sfp_set_transmitter(bp, params->port, 3025 bnx2x_sfp_set_transmitter(bp, phy, 1);
3232 ext_phy_type, ext_phy_addr, 1);
3233 else 3026 else
3234 bnx2x_sfp_set_transmitter(bp, params->port, 3027 bnx2x_sfp_set_transmitter(bp, phy, 0);
3235 ext_phy_type, ext_phy_addr, 0);
3236 3028
3237 return rc; 3029 return rc;
3238} 3030}
@@ -3240,6 +3032,7 @@ static u8 bnx2x_sfp_module_detection(struct link_params *params)
3240void bnx2x_handle_module_detect_int(struct link_params *params) 3032void bnx2x_handle_module_detect_int(struct link_params *params)
3241{ 3033{
3242 struct bnx2x *bp = params->bp; 3034 struct bnx2x *bp = params->bp;
3035 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
3243 u32 gpio_val; 3036 u32 gpio_val;
3244 u8 port = params->port; 3037 u8 port = params->port;
3245 3038
@@ -3249,25 +3042,20 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
3249 params->port); 3042 params->port);
3250 3043
3251 /* Get current gpio val refelecting module plugged in / out*/ 3044 /* Get current gpio val refelecting module plugged in / out*/
3252 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port); 3045 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3253 3046
3254 /* Call the handling function in case module is detected */ 3047 /* Call the handling function in case module is detected */
3255 if (gpio_val == 0) { 3048 if (gpio_val == 0) {
3256 3049
3257 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, 3050 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3258 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 3051 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3259 port); 3052 port);
3260 3053
3261 if (bnx2x_wait_for_sfp_module_initialized(params) == 3054 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
3262 0) 3055 bnx2x_sfp_module_detection(phy, params);
3263 bnx2x_sfp_module_detection(params);
3264 else 3056 else
3265 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 3057 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3266 } else { 3058 } else {
3267 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3268
3269 u32 ext_phy_type =
3270 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3271 u32 val = REG_RD(bp, params->shmem_base + 3059 u32 val = REG_RD(bp, params->shmem_base +
3272 offsetof(struct shmem_region, dev_info. 3060 offsetof(struct shmem_region, dev_info.
3273 port_feature_config[params->port]. 3061 port_feature_config[params->port].
@@ -3280,48 +3068,36 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
3280 /* Disable transmit for this module */ 3068 /* Disable transmit for this module */
3281 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 3069 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3282 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 3070 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3283 bnx2x_sfp_set_transmitter(bp, params->port, 3071 bnx2x_sfp_set_transmitter(bp, phy, 0);
3284 ext_phy_type, ext_phy_addr, 0);
3285 } 3072 }
3286} 3073}
3287 3074
3288static void bnx2x_bcm807x_force_10G(struct link_params *params) 3075static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
3289{ 3076{
3290 struct bnx2x *bp = params->bp;
3291 u8 port = params->port;
3292 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3293 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3294
3295 /* Force KR or KX */ 3077 /* Force KR or KX */
3296 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3078 bnx2x_cl45_write(bp, phy,
3297 MDIO_PMA_DEVAD, 3079 MDIO_PMA_DEVAD,
3298 MDIO_PMA_REG_CTRL, 3080 MDIO_PMA_REG_CTRL,
3299 0x2040); 3081 0x2040);
3300 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3082 bnx2x_cl45_write(bp, phy,
3301 MDIO_PMA_DEVAD, 3083 MDIO_PMA_DEVAD,
3302 MDIO_PMA_REG_10G_CTRL2, 3084 MDIO_PMA_REG_10G_CTRL2,
3303 0x000b); 3085 0x000b);
3304 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3086 bnx2x_cl45_write(bp, phy,
3305 MDIO_PMA_DEVAD, 3087 MDIO_PMA_DEVAD,
3306 MDIO_PMA_REG_BCM_CTRL, 3088 MDIO_PMA_REG_BCM_CTRL,
3307 0x0000); 3089 0x0000);
3308 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3090 bnx2x_cl45_write(bp, phy,
3309 MDIO_AN_DEVAD, 3091 MDIO_AN_DEVAD,
3310 MDIO_AN_REG_CTRL, 3092 MDIO_AN_REG_CTRL,
3311 0x0000); 3093 0x0000);
3312} 3094}
3313 3095
3314static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) 3096static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3097 struct bnx2x_phy *phy)
3315{ 3098{
3316 struct bnx2x *bp = params->bp;
3317 u8 port = params->port;
3318 u16 val; 3099 u16 val;
3319 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 3100 bnx2x_cl45_read(bp, phy,
3320 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3321
3322 bnx2x_cl45_read(bp, params->port,
3323 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3324 ext_phy_addr,
3325 MDIO_PMA_DEVAD, 3101 MDIO_PMA_DEVAD,
3326 MDIO_PMA_REG_8073_CHIP_REV, &val); 3102 MDIO_PMA_REG_8073_CHIP_REV, &val);
3327 3103
@@ -3331,67 +3107,63 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3331 } 3107 }
3332 3108
3333 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */ 3109 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3334 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 3110 bnx2x_cl45_read(bp, phy,
3335 MDIO_XS_DEVAD, 3111 MDIO_XS_DEVAD,
3336 MDIO_XS_PLL_SEQUENCER, &val); 3112 MDIO_XS_PLL_SEQUENCER, &val);
3337 val &= ~(1<<13); 3113 val &= ~(1<<13);
3338 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3114 bnx2x_cl45_write(bp, phy,
3339 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); 3115 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3340 3116
3341 /* PLL controls */ 3117 /* PLL controls */
3342 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3118 bnx2x_cl45_write(bp, phy,
3343 MDIO_XS_DEVAD, 0x805E, 0x1077); 3119 MDIO_XS_DEVAD, 0x805E, 0x1077);
3344 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3120 bnx2x_cl45_write(bp, phy,
3345 MDIO_XS_DEVAD, 0x805D, 0x0000); 3121 MDIO_XS_DEVAD, 0x805D, 0x0000);
3346 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3122 bnx2x_cl45_write(bp, phy,
3347 MDIO_XS_DEVAD, 0x805C, 0x030B); 3123 MDIO_XS_DEVAD, 0x805C, 0x030B);
3348 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3124 bnx2x_cl45_write(bp, phy,
3349 MDIO_XS_DEVAD, 0x805B, 0x1240); 3125 MDIO_XS_DEVAD, 0x805B, 0x1240);
3350 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3126 bnx2x_cl45_write(bp, phy,
3351 MDIO_XS_DEVAD, 0x805A, 0x2490); 3127 MDIO_XS_DEVAD, 0x805A, 0x2490);
3352 3128
3353 /* Tx Controls */ 3129 /* Tx Controls */
3354 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3130 bnx2x_cl45_write(bp, phy,
3355 MDIO_XS_DEVAD, 0x80A7, 0x0C74); 3131 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3356 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3132 bnx2x_cl45_write(bp, phy,
3357 MDIO_XS_DEVAD, 0x80A6, 0x9041); 3133 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3358 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3134 bnx2x_cl45_write(bp, phy,
3359 MDIO_XS_DEVAD, 0x80A5, 0x4640); 3135 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3360 3136
3361 /* Rx Controls */ 3137 /* Rx Controls */
3362 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3138 bnx2x_cl45_write(bp, phy,
3363 MDIO_XS_DEVAD, 0x80FE, 0x01C4); 3139 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3364 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3140 bnx2x_cl45_write(bp, phy,
3365 MDIO_XS_DEVAD, 0x80FD, 0x9249); 3141 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3366 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3142 bnx2x_cl45_write(bp, phy,
3367 MDIO_XS_DEVAD, 0x80FC, 0x2015); 3143 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3368 3144
3369 /* Enable PLL sequencer (use read-modify-write to set bit 13) */ 3145 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3370 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 3146 bnx2x_cl45_read(bp, phy,
3371 MDIO_XS_DEVAD, 3147 MDIO_XS_DEVAD,
3372 MDIO_XS_PLL_SEQUENCER, &val); 3148 MDIO_XS_PLL_SEQUENCER, &val);
3373 val |= (1<<13); 3149 val |= (1<<13);
3374 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 3150 bnx2x_cl45_write(bp, phy,
3375 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); 3151 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3376} 3152}
3377 3153
3378static void bnx2x_8073_set_pause_cl37(struct link_params *params, 3154static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3379 struct link_vars *vars) 3155 struct bnx2x_phy *phy,
3156 struct link_vars *vars)
3380{ 3157{
3381 struct bnx2x *bp = params->bp;
3382 u16 cl37_val; 3158 u16 cl37_val;
3383 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 3159 struct bnx2x *bp = params->bp;
3384 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 3160 bnx2x_cl45_read(bp, phy,
3385
3386 bnx2x_cl45_read(bp, params->port,
3387 ext_phy_type,
3388 ext_phy_addr,
3389 MDIO_AN_DEVAD, 3161 MDIO_AN_DEVAD,
3390 MDIO_AN_REG_CL37_FC_LD, &cl37_val); 3162 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3391 3163
3392 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3164 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3393 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3165 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3394 3166 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3395 if ((vars->ieee_fc & 3167 if ((vars->ieee_fc &
3396 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 3168 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3397 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 3169 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
@@ -3410,26 +3182,20 @@ static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3410 DP(NETIF_MSG_LINK, 3182 DP(NETIF_MSG_LINK,
3411 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 3183 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3412 3184
3413 bnx2x_cl45_write(bp, params->port, 3185 bnx2x_cl45_write(bp, phy,
3414 ext_phy_type,
3415 ext_phy_addr,
3416 MDIO_AN_DEVAD, 3186 MDIO_AN_DEVAD,
3417 MDIO_AN_REG_CL37_FC_LD, cl37_val); 3187 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3418 msleep(500); 3188 msleep(500);
3419} 3189}
3420 3190
3421static void bnx2x_ext_phy_set_pause(struct link_params *params, 3191static void bnx2x_ext_phy_set_pause(struct link_params *params,
3422 struct link_vars *vars) 3192 struct bnx2x_phy *phy,
3193 struct link_vars *vars)
3423{ 3194{
3424 struct bnx2x *bp = params->bp;
3425 u16 val; 3195 u16 val;
3426 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 3196 struct bnx2x *bp = params->bp;
3427 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3428
3429 /* read modify write pause advertizing */ 3197 /* read modify write pause advertizing */
3430 bnx2x_cl45_read(bp, params->port, 3198 bnx2x_cl45_read(bp, phy,
3431 ext_phy_type,
3432 ext_phy_addr,
3433 MDIO_AN_DEVAD, 3199 MDIO_AN_DEVAD,
3434 MDIO_AN_REG_ADV_PAUSE, &val); 3200 MDIO_AN_REG_ADV_PAUSE, &val);
3435 3201
@@ -3450,21 +3216,21 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
3450 } 3216 }
3451 DP(NETIF_MSG_LINK, 3217 DP(NETIF_MSG_LINK,
3452 "Ext phy AN advertize 0x%x\n", val); 3218 "Ext phy AN advertize 0x%x\n", val);
3453 bnx2x_cl45_write(bp, params->port, 3219 bnx2x_cl45_write(bp, phy,
3454 ext_phy_type,
3455 ext_phy_addr,
3456 MDIO_AN_DEVAD, 3220 MDIO_AN_DEVAD,
3457 MDIO_AN_REG_ADV_PAUSE, val); 3221 MDIO_AN_REG_ADV_PAUSE, val);
3458} 3222}
3459static void bnx2x_set_preemphasis(struct link_params *params) 3223
3224static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
3225 struct link_params *params)
3460{ 3226{
3227
3461 u16 bank, i = 0; 3228 u16 bank, i = 0;
3462 struct bnx2x *bp = params->bp; 3229 struct bnx2x *bp = params->bp;
3463 3230
3464 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 3231 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3465 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 3232 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3466 CL45_WR_OVER_CL22(bp, params->port, 3233 CL45_WR_OVER_CL22(bp, phy,
3467 params->phy_addr,
3468 bank, 3234 bank,
3469 MDIO_RX0_RX_EQ_BOOST, 3235 MDIO_RX0_RX_EQ_BOOST,
3470 params->xgxs_config_rx[i]); 3236 params->xgxs_config_rx[i]);
@@ -3472,141 +3238,120 @@ static void bnx2x_set_preemphasis(struct link_params *params)
3472 3238
3473 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 3239 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3474 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 3240 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3475 CL45_WR_OVER_CL22(bp, params->port, 3241 CL45_WR_OVER_CL22(bp, phy,
3476 params->phy_addr,
3477 bank, 3242 bank,
3478 MDIO_TX0_TX_DRIVER, 3243 MDIO_TX0_TX_DRIVER,
3479 params->xgxs_config_tx[i]); 3244 params->xgxs_config_tx[i]);
3480 } 3245 }
3481} 3246}
3482 3247
3483 3248static void bnx2x_8481_set_led(struct bnx2x *bp,
3484static void bnx2x_8481_set_led(struct link_params *params, 3249 struct bnx2x_phy *phy)
3485 u32 ext_phy_type, u8 ext_phy_addr)
3486{ 3250{
3487 struct bnx2x *bp = params->bp;
3488 u16 val; 3251 u16 val;
3489 bnx2x_cl45_read(bp, params->port, 3252
3490 ext_phy_type, 3253 /* PHYC_CTL_LED_CTL */
3491 ext_phy_addr, 3254 bnx2x_cl45_read(bp, phy,
3492 MDIO_PMA_DEVAD, 3255 MDIO_PMA_DEVAD,
3493 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 3256 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
3494 val &= 0xFE00; 3257 val &= 0xFE00;
3495 val |= 0x0092; 3258 val |= 0x0092;
3496 3259
3497 bnx2x_cl45_write(bp, params->port, 3260 bnx2x_cl45_write(bp, phy,
3498 ext_phy_type,
3499 ext_phy_addr,
3500 MDIO_PMA_DEVAD, 3261 MDIO_PMA_DEVAD,
3501 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 3262 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
3502 3263
3503 bnx2x_cl45_write(bp, params->port, 3264 bnx2x_cl45_write(bp, phy,
3504 ext_phy_type,
3505 ext_phy_addr,
3506 MDIO_PMA_DEVAD, 3265 MDIO_PMA_DEVAD,
3507 MDIO_PMA_REG_8481_LED1_MASK, 3266 MDIO_PMA_REG_8481_LED1_MASK,
3508 0x80); 3267 0x80);
3509 3268
3510 bnx2x_cl45_write(bp, params->port, 3269 bnx2x_cl45_write(bp, phy,
3511 ext_phy_type,
3512 ext_phy_addr,
3513 MDIO_PMA_DEVAD, 3270 MDIO_PMA_DEVAD,
3514 MDIO_PMA_REG_8481_LED2_MASK, 3271 MDIO_PMA_REG_8481_LED2_MASK,
3515 0x18); 3272 0x18);
3516 3273
3517 bnx2x_cl45_write(bp, params->port, 3274 bnx2x_cl45_write(bp, phy,
3518 ext_phy_type,
3519 ext_phy_addr,
3520 MDIO_PMA_DEVAD, 3275 MDIO_PMA_DEVAD,
3521 MDIO_PMA_REG_8481_LED3_MASK, 3276 MDIO_PMA_REG_8481_LED3_MASK,
3522 0x0040); 3277 0x0040);
3523 3278
3524 /* 'Interrupt Mask' */ 3279 /* 'Interrupt Mask' */
3525 bnx2x_cl45_write(bp, params->port, 3280 bnx2x_cl45_write(bp, phy,
3526 ext_phy_type,
3527 ext_phy_addr,
3528 MDIO_AN_DEVAD, 3281 MDIO_AN_DEVAD,
3529 0xFFFB, 0xFFFD); 3282 0xFFFB, 0xFFFD);
3530} 3283}
3531 3284
3532static void bnx2x_init_internal_phy(struct link_params *params, 3285static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
3533 struct link_vars *vars, 3286 struct link_params *params,
3534 u8 enable_cl73) 3287 struct link_vars *vars)
3535{ 3288{
3536 struct bnx2x *bp = params->bp; 3289 struct bnx2x *bp = params->bp;
3537 3290 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
3291 (params->loopback_mode == LOOPBACK_XGXS_10));
3538 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 3292 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3539 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 3293 if (SINGLE_MEDIA_DIRECT(params) &&
3540 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3541 (params->feature_config_flags & 3294 (params->feature_config_flags &
3542 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 3295 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3543 bnx2x_set_preemphasis(params); 3296 bnx2x_set_preemphasis(phy, params);
3544 3297
3545 /* forced speed requested? */ 3298 /* forced speed requested? */
3546 if (vars->line_speed != SPEED_AUTO_NEG || 3299 if (vars->line_speed != SPEED_AUTO_NEG ||
3547 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 3300 (SINGLE_MEDIA_DIRECT(params) &&
3548 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3549 params->loopback_mode == LOOPBACK_EXT)) { 3301 params->loopback_mode == LOOPBACK_EXT)) {
3550 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 3302 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3551 3303
3552 /* disable autoneg */ 3304 /* disable autoneg */
3553 bnx2x_set_autoneg(params, vars, 0); 3305 bnx2x_set_autoneg(phy, params, vars, 0);
3554 3306
3555 /* program speed and duplex */ 3307 /* program speed and duplex */
3556 bnx2x_program_serdes(params, vars); 3308 bnx2x_program_serdes(phy, params, vars);
3557 3309
3558 } else { /* AN_mode */ 3310 } else { /* AN_mode */
3559 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 3311 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3560 3312
3561 /* AN enabled */ 3313 /* AN enabled */
3562 bnx2x_set_brcm_cl37_advertisment(params); 3314 bnx2x_set_brcm_cl37_advertisment(phy, params);
3563 3315
3564 /* program duplex & pause advertisement (for aneg) */ 3316 /* program duplex & pause advertisement (for aneg) */
3565 bnx2x_set_ieee_aneg_advertisment(params, 3317 bnx2x_set_ieee_aneg_advertisment(phy, params,
3566 vars->ieee_fc); 3318 vars->ieee_fc);
3567 3319
3568 /* enable autoneg */ 3320 /* enable autoneg */
3569 bnx2x_set_autoneg(params, vars, enable_cl73); 3321 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
3570 3322
3571 /* enable and restart AN */ 3323 /* enable and restart AN */
3572 bnx2x_restart_autoneg(params, enable_cl73); 3324 bnx2x_restart_autoneg(phy, params, enable_cl73);
3573 } 3325 }
3574 3326
3575 } else { /* SGMII mode */ 3327 } else { /* SGMII mode */
3576 DP(NETIF_MSG_LINK, "SGMII\n"); 3328 DP(NETIF_MSG_LINK, "SGMII\n");
3577 3329
3578 bnx2x_initialize_sgmii_process(params, vars); 3330 bnx2x_initialize_sgmii_process(phy, params, vars);
3579 } 3331 }
3580} 3332}
3581 3333
3582static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) 3334static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3583{ 3335{
3584 struct bnx2x *bp = params->bp; 3336 struct bnx2x *bp = params->bp;
3585 u32 ext_phy_type;
3586 u8 ext_phy_addr;
3587 u16 cnt; 3337 u16 cnt;
3588 u16 ctrl = 0; 3338 u16 ctrl = 0;
3589 u16 val = 0; 3339 u16 val = 0;
3590 u8 rc = 0; 3340 u8 rc = 0;
3591 3341 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
3592 if (vars->phy_flags & PHY_XGXS_FLAG) { 3342 if (vars->phy_flags & PHY_XGXS_FLAG) {
3593 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3594
3595 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3596 /* Make sure that the soft reset is off (expect for the 8072: 3343 /* Make sure that the soft reset is off (expect for the 8072:
3597 * due to the lock, it will be done inside the specific 3344 * due to the lock, it will be done inside the specific
3598 * handling) 3345 * handling)
3599 */ 3346 */
3600 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 3347 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3601 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 3348 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3602 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) && 3349 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3603 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) && 3350 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3604 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) { 3351 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3605 /* Wait for soft reset to get cleared upto 1 sec */ 3352 /* Wait for soft reset to get cleared upto 1 sec */
3606 for (cnt = 0; cnt < 1000; cnt++) { 3353 for (cnt = 0; cnt < 1000; cnt++) {
3607 bnx2x_cl45_read(bp, params->port, 3354 bnx2x_cl45_read(bp, phy,
3608 ext_phy_type,
3609 ext_phy_addr,
3610 MDIO_PMA_DEVAD, 3355 MDIO_PMA_DEVAD,
3611 MDIO_PMA_REG_CTRL, &ctrl); 3356 MDIO_PMA_REG_CTRL, &ctrl);
3612 if (!(ctrl & (1<<15))) 3357 if (!(ctrl & (1<<15)))
@@ -3617,34 +3362,26 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3617 ctrl, cnt); 3362 ctrl, cnt);
3618 } 3363 }
3619 3364
3620 switch (ext_phy_type) { 3365 switch (phy->type) {
3621 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 3366 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3622 break; 3367 break;
3623 3368
3624 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 3369 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3625 DP(NETIF_MSG_LINK, "XGXS 8705\n"); 3370 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3626 3371
3627 bnx2x_cl45_write(bp, params->port, 3372 bnx2x_cl45_write(bp, phy,
3628 ext_phy_type,
3629 ext_phy_addr,
3630 MDIO_PMA_DEVAD, 3373 MDIO_PMA_DEVAD,
3631 MDIO_PMA_REG_MISC_CTRL, 3374 MDIO_PMA_REG_MISC_CTRL,
3632 0x8288); 3375 0x8288);
3633 bnx2x_cl45_write(bp, params->port, 3376 bnx2x_cl45_write(bp, phy,
3634 ext_phy_type,
3635 ext_phy_addr,
3636 MDIO_PMA_DEVAD, 3377 MDIO_PMA_DEVAD,
3637 MDIO_PMA_REG_PHY_IDENTIFIER, 3378 MDIO_PMA_REG_PHY_IDENTIFIER,
3638 0x7fbf); 3379 0x7fbf);
3639 bnx2x_cl45_write(bp, params->port, 3380 bnx2x_cl45_write(bp, phy,
3640 ext_phy_type,
3641 ext_phy_addr,
3642 MDIO_PMA_DEVAD, 3381 MDIO_PMA_DEVAD,
3643 MDIO_PMA_REG_CMU_PLL_BYPASS, 3382 MDIO_PMA_REG_CMU_PLL_BYPASS,
3644 0x0100); 3383 0x0100);
3645 bnx2x_cl45_write(bp, params->port, 3384 bnx2x_cl45_write(bp, phy,
3646 ext_phy_type,
3647 ext_phy_addr,
3648 MDIO_WIS_DEVAD, 3385 MDIO_WIS_DEVAD,
3649 MDIO_WIS_REG_LASI_CNTL, 0x1); 3386 MDIO_WIS_REG_LASI_CNTL, 0x1);
3650 3387
@@ -3656,8 +3393,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3656 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 3393 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3657 /* Wait until fw is loaded */ 3394 /* Wait until fw is loaded */
3658 for (cnt = 0; cnt < 100; cnt++) { 3395 for (cnt = 0; cnt < 100; cnt++) {
3659 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3396 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3660 ext_phy_addr, MDIO_PMA_DEVAD,
3661 MDIO_PMA_REG_ROM_VER1, &val); 3397 MDIO_PMA_REG_ROM_VER1, &val);
3662 if (val) 3398 if (val)
3663 break; 3399 break;
@@ -3673,9 +3409,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3673 reg = MDIO_XS_8706_REG_BANK_RX0 + 3409 reg = MDIO_XS_8706_REG_BANK_RX0 +
3674 i*(MDIO_XS_8706_REG_BANK_RX1 - 3410 i*(MDIO_XS_8706_REG_BANK_RX1 -
3675 MDIO_XS_8706_REG_BANK_RX0); 3411 MDIO_XS_8706_REG_BANK_RX0);
3676 bnx2x_cl45_read(bp, params->port, 3412 bnx2x_cl45_read(bp, phy,
3677 ext_phy_type,
3678 ext_phy_addr,
3679 MDIO_XS_DEVAD, 3413 MDIO_XS_DEVAD,
3680 reg, &val); 3414 reg, &val);
3681 /* Clear first 3 bits of the control */ 3415 /* Clear first 3 bits of the control */
@@ -3687,9 +3421,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3687 DP(NETIF_MSG_LINK, "Setting RX" 3421 DP(NETIF_MSG_LINK, "Setting RX"
3688 "Equalizer to BCM8706 reg 0x%x" 3422 "Equalizer to BCM8706 reg 0x%x"
3689 " <-- val 0x%x\n", reg, val); 3423 " <-- val 0x%x\n", reg, val);
3690 bnx2x_cl45_write(bp, params->port, 3424 bnx2x_cl45_write(bp, phy,
3691 ext_phy_type,
3692 ext_phy_addr,
3693 MDIO_XS_DEVAD, 3425 MDIO_XS_DEVAD,
3694 reg, val); 3426 reg, val);
3695 } 3427 }
@@ -3698,14 +3430,11 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3698 if (params->req_line_speed == SPEED_10000) { 3430 if (params->req_line_speed == SPEED_10000) {
3699 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 3431 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3700 3432
3701 bnx2x_cl45_write(bp, params->port, 3433 bnx2x_cl45_write(bp, phy,
3702 ext_phy_type,
3703 ext_phy_addr,
3704 MDIO_PMA_DEVAD, 3434 MDIO_PMA_DEVAD,
3705 MDIO_PMA_REG_DIGITAL_CTRL, 3435 MDIO_PMA_REG_DIGITAL_CTRL,
3706 0x400); 3436 0x400);
3707 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3437 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3708 ext_phy_addr, MDIO_PMA_DEVAD,
3709 MDIO_PMA_REG_LASI_CTRL, 1); 3438 MDIO_PMA_REG_LASI_CTRL, 1);
3710 } else { 3439 } else {
3711 /* Force 1Gbps using autoneg with 1G 3440 /* Force 1Gbps using autoneg with 1G
@@ -3713,85 +3442,66 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3713 3442
3714 /* Allow CL37 through CL73 */ 3443 /* Allow CL37 through CL73 */
3715 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 3444 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3716 bnx2x_cl45_write(bp, params->port, 3445 bnx2x_cl45_write(bp, phy,
3717 ext_phy_type,
3718 ext_phy_addr,
3719 MDIO_AN_DEVAD, 3446 MDIO_AN_DEVAD,
3720 MDIO_AN_REG_CL37_CL73, 3447 MDIO_AN_REG_CL37_CL73,
3721 0x040c); 3448 0x040c);
3722 3449
3723 /* Enable Full-Duplex advertisment on CL37 */ 3450 /* Enable Full-Duplex advertisment on CL37 */
3724 bnx2x_cl45_write(bp, params->port, 3451 bnx2x_cl45_write(bp, phy,
3725 ext_phy_type,
3726 ext_phy_addr,
3727 MDIO_AN_DEVAD, 3452 MDIO_AN_DEVAD,
3728 MDIO_AN_REG_CL37_FC_LP, 3453 MDIO_AN_REG_CL37_FC_LP,
3729 0x0020); 3454 0x0020);
3730 /* Enable CL37 AN */ 3455 /* Enable CL37 AN */
3731 bnx2x_cl45_write(bp, params->port, 3456 bnx2x_cl45_write(bp, phy,
3732 ext_phy_type,
3733 ext_phy_addr,
3734 MDIO_AN_DEVAD, 3457 MDIO_AN_DEVAD,
3735 MDIO_AN_REG_CL37_AN, 3458 MDIO_AN_REG_CL37_AN,
3736 0x1000); 3459 0x1000);
3737 /* 1G support */ 3460 /* 1G support */
3738 bnx2x_cl45_write(bp, params->port, 3461 bnx2x_cl45_write(bp, phy,
3739 ext_phy_type,
3740 ext_phy_addr,
3741 MDIO_AN_DEVAD, 3462 MDIO_AN_DEVAD,
3742 MDIO_AN_REG_ADV, (1<<5)); 3463 MDIO_AN_REG_ADV, (1<<5));
3743 3464
3744 /* Enable clause 73 AN */ 3465 /* Enable clause 73 AN */
3745 bnx2x_cl45_write(bp, params->port, 3466 bnx2x_cl45_write(bp, phy,
3746 ext_phy_type,
3747 ext_phy_addr,
3748 MDIO_AN_DEVAD, 3467 MDIO_AN_DEVAD,
3749 MDIO_AN_REG_CTRL, 3468 MDIO_AN_REG_CTRL,
3750 0x1200); 3469 0x1200);
3751 bnx2x_cl45_write(bp, params->port, 3470 bnx2x_cl45_write(bp, phy,
3752 ext_phy_type,
3753 ext_phy_addr,
3754 MDIO_PMA_DEVAD, 3471 MDIO_PMA_DEVAD,
3755 MDIO_PMA_REG_RX_ALARM_CTRL, 3472 MDIO_PMA_REG_RX_ALARM_CTRL,
3756 0x0400); 3473 0x0400);
3757 bnx2x_cl45_write(bp, params->port, 3474 bnx2x_cl45_write(bp, phy,
3758 ext_phy_type,
3759 ext_phy_addr,
3760 MDIO_PMA_DEVAD, 3475 MDIO_PMA_DEVAD,
3761 MDIO_PMA_REG_LASI_CTRL, 0x0004); 3476 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3762 3477
3763 } 3478 }
3764 bnx2x_save_bcm_spirom_ver(bp, params->port, 3479 bnx2x_save_bcm_spirom_ver(bp, params->port,
3765 ext_phy_type, 3480 phy,
3766 ext_phy_addr,
3767 params->shmem_base); 3481 params->shmem_base);
3768 break; 3482 break;
3769 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 3483 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3770 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 3484 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3771 bnx2x_bcm8726_external_rom_boot(params); 3485 bnx2x_8726_external_rom_boot(phy, params);
3772 3486
3773 /* Need to call module detected on initialization since 3487 /* Need to call module detected on initialization since
3774 the module detection triggered by actual module 3488 the module detection triggered by actual module
3775 insertion might occur before driver is loaded, and when 3489 insertion might occur before driver is loaded, and when
3776 driver is loaded, it reset all registers, including the 3490 driver is loaded, it reset all registers, including the
3777 transmitter */ 3491 transmitter */
3778 bnx2x_sfp_module_detection(params); 3492 bnx2x_sfp_module_detection(phy, params);
3779 3493
3780 /* Set Flow control */ 3494 /* Set Flow control */
3781 bnx2x_ext_phy_set_pause(params, vars); 3495 bnx2x_ext_phy_set_pause(params, phy, vars);
3782 if (params->req_line_speed == SPEED_1000) { 3496 if (params->req_line_speed == SPEED_1000) {
3783 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 3497 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3784 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3498 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3785 ext_phy_addr, MDIO_PMA_DEVAD,
3786 MDIO_PMA_REG_CTRL, 0x40); 3499 MDIO_PMA_REG_CTRL, 0x40);
3787 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3500 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3788 ext_phy_addr, MDIO_PMA_DEVAD,
3789 MDIO_PMA_REG_10G_CTRL2, 0xD); 3501 MDIO_PMA_REG_10G_CTRL2, 0xD);
3790 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3502 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3791 ext_phy_addr, MDIO_PMA_DEVAD,
3792 MDIO_PMA_REG_LASI_CTRL, 0x5); 3503 MDIO_PMA_REG_LASI_CTRL, 0x5);
3793 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3504 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3794 ext_phy_addr, MDIO_PMA_DEVAD,
3795 MDIO_PMA_REG_RX_ALARM_CTRL, 3505 MDIO_PMA_REG_RX_ALARM_CTRL,
3796 0x400); 3506 0x400);
3797 } else if ((params->req_line_speed == 3507 } else if ((params->req_line_speed ==
@@ -3799,35 +3509,27 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3799 ((params->speed_cap_mask & 3509 ((params->speed_cap_mask &
3800 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) { 3510 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3801 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 3511 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3802 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3512 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3803 ext_phy_addr, MDIO_AN_DEVAD,
3804 MDIO_AN_REG_ADV, 0x20); 3513 MDIO_AN_REG_ADV, 0x20);
3805 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3514 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3806 ext_phy_addr, MDIO_AN_DEVAD,
3807 MDIO_AN_REG_CL37_CL73, 0x040c); 3515 MDIO_AN_REG_CL37_CL73, 0x040c);
3808 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3516 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3809 ext_phy_addr, MDIO_AN_DEVAD,
3810 MDIO_AN_REG_CL37_FC_LD, 0x0020); 3517 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3811 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3518 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3812 ext_phy_addr, MDIO_AN_DEVAD,
3813 MDIO_AN_REG_CL37_AN, 0x1000); 3519 MDIO_AN_REG_CL37_AN, 0x1000);
3814 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3520 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3815 ext_phy_addr, MDIO_AN_DEVAD,
3816 MDIO_AN_REG_CTRL, 0x1200); 3521 MDIO_AN_REG_CTRL, 0x1200);
3817 3522
3818 /* Enable RX-ALARM control to receive 3523 /* Enable RX-ALARM control to receive
3819 interrupt for 1G speed change */ 3524 interrupt for 1G speed change */
3820 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3525 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3821 ext_phy_addr, MDIO_PMA_DEVAD,
3822 MDIO_PMA_REG_LASI_CTRL, 0x4); 3526 MDIO_PMA_REG_LASI_CTRL, 0x4);
3823 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3527 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3824 ext_phy_addr, MDIO_PMA_DEVAD,
3825 MDIO_PMA_REG_RX_ALARM_CTRL, 3528 MDIO_PMA_REG_RX_ALARM_CTRL,
3826 0x400); 3529 0x400);
3827 3530
3828 } else { /* Default 10G. Set only LASI control */ 3531 } else { /* Default 10G. Set only LASI control */
3829 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3532 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3830 ext_phy_addr, MDIO_PMA_DEVAD,
3831 MDIO_PMA_REG_LASI_CTRL, 1); 3533 MDIO_PMA_REG_LASI_CTRL, 1);
3832 } 3534 }
3833 3535
@@ -3838,16 +3540,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3838 "TX_CTRL2 0x%x\n", 3540 "TX_CTRL2 0x%x\n",
3839 params->xgxs_config_tx[0], 3541 params->xgxs_config_tx[0],
3840 params->xgxs_config_tx[1]); 3542 params->xgxs_config_tx[1]);
3841 bnx2x_cl45_write(bp, params->port, 3543 bnx2x_cl45_write(bp, phy,
3842 ext_phy_type,
3843 ext_phy_addr,
3844 MDIO_PMA_DEVAD, 3544 MDIO_PMA_DEVAD,
3845 MDIO_PMA_REG_8726_TX_CTRL1, 3545 MDIO_PMA_REG_8726_TX_CTRL1,
3846 params->xgxs_config_tx[0]); 3546 params->xgxs_config_tx[0]);
3847 3547
3848 bnx2x_cl45_write(bp, params->port, 3548 bnx2x_cl45_write(bp, phy,
3849 ext_phy_type,
3850 ext_phy_addr,
3851 MDIO_PMA_DEVAD, 3549 MDIO_PMA_DEVAD,
3852 MDIO_PMA_REG_8726_TX_CTRL2, 3550 MDIO_PMA_REG_8726_TX_CTRL2,
3853 params->xgxs_config_tx[1]); 3551 params->xgxs_config_tx[1]);
@@ -3859,7 +3557,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3859 u16 tmp1; 3557 u16 tmp1;
3860 u16 rx_alarm_ctrl_val; 3558 u16 rx_alarm_ctrl_val;
3861 u16 lasi_ctrl_val; 3559 u16 lasi_ctrl_val;
3862 if (ext_phy_type == 3560 if (phy->type ==
3863 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { 3561 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3864 rx_alarm_ctrl_val = 0x400; 3562 rx_alarm_ctrl_val = 0x400;
3865 lasi_ctrl_val = 0x0004; 3563 lasi_ctrl_val = 0x0004;
@@ -3869,40 +3567,32 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3869 } 3567 }
3870 3568
3871 /* enable LASI */ 3569 /* enable LASI */
3872 bnx2x_cl45_write(bp, params->port, 3570 bnx2x_cl45_write(bp, phy,
3873 ext_phy_type,
3874 ext_phy_addr,
3875 MDIO_PMA_DEVAD, 3571 MDIO_PMA_DEVAD,
3876 MDIO_PMA_REG_RX_ALARM_CTRL, 3572 MDIO_PMA_REG_RX_ALARM_CTRL,
3877 rx_alarm_ctrl_val); 3573 rx_alarm_ctrl_val);
3878 3574
3879 bnx2x_cl45_write(bp, params->port, 3575 bnx2x_cl45_write(bp, phy,
3880 ext_phy_type,
3881 ext_phy_addr,
3882 MDIO_PMA_DEVAD, 3576 MDIO_PMA_DEVAD,
3883 MDIO_PMA_REG_LASI_CTRL, 3577 MDIO_PMA_REG_LASI_CTRL,
3884 lasi_ctrl_val); 3578 lasi_ctrl_val);
3885 3579
3886 bnx2x_8073_set_pause_cl37(params, vars); 3580 bnx2x_8073_set_pause_cl37(params, phy, vars);
3887 3581
3888 if (ext_phy_type == 3582 if (phy->type ==
3889 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) 3583 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
3890 bnx2x_bcm8072_external_rom_boot(params); 3584 bnx2x_bcm8072_external_rom_boot(phy, params);
3891 else 3585 else
3892 /* In case of 8073 with long xaui lines, 3586 /* In case of 8073 with long xaui lines,
3893 don't set the 8073 xaui low power*/ 3587 don't set the 8073 xaui low power*/
3894 bnx2x_bcm8073_set_xaui_low_power_mode(params); 3588 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
3895 3589
3896 bnx2x_cl45_read(bp, params->port, 3590 bnx2x_cl45_read(bp, phy,
3897 ext_phy_type,
3898 ext_phy_addr,
3899 MDIO_PMA_DEVAD, 3591 MDIO_PMA_DEVAD,
3900 MDIO_PMA_REG_M8051_MSGOUT_REG, 3592 MDIO_PMA_REG_M8051_MSGOUT_REG,
3901 &tmp1); 3593 &tmp1);
3902 3594
3903 bnx2x_cl45_read(bp, params->port, 3595 bnx2x_cl45_read(bp, phy,
3904 ext_phy_type,
3905 ext_phy_addr,
3906 MDIO_PMA_DEVAD, 3596 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_RX_ALARM, &tmp1); 3597 MDIO_PMA_REG_RX_ALARM, &tmp1);
3908 3598
@@ -3913,13 +3603,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3913 * (all other are not supported) 3603 * (all other are not supported)
3914 */ 3604 */
3915 if (params->loopback_mode == LOOPBACK_EXT) { 3605 if (params->loopback_mode == LOOPBACK_EXT) {
3916 bnx2x_bcm807x_force_10G(params); 3606 bnx2x_807x_force_10G(bp, phy);
3917 DP(NETIF_MSG_LINK, 3607 DP(NETIF_MSG_LINK,
3918 "Forced speed 10G on 807X\n"); 3608 "Forced speed 10G on 807X\n");
3919 break; 3609 break;
3920 } else { 3610 } else {
3921 bnx2x_cl45_write(bp, params->port, 3611 bnx2x_cl45_write(bp, phy,
3922 ext_phy_type, ext_phy_addr,
3923 MDIO_PMA_DEVAD, 3612 MDIO_PMA_DEVAD,
3924 MDIO_PMA_REG_BCM_CTRL, 3613 MDIO_PMA_REG_BCM_CTRL,
3925 0x0002); 3614 0x0002);
@@ -3951,16 +3640,11 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3951 "807x autoneg val = 0x%x\n", val); 3640 "807x autoneg val = 0x%x\n", val);
3952 } 3641 }
3953 3642
3954 bnx2x_cl45_write(bp, params->port, 3643 bnx2x_cl45_write(bp, phy,
3955 ext_phy_type,
3956 ext_phy_addr,
3957 MDIO_AN_DEVAD, 3644 MDIO_AN_DEVAD,
3958 MDIO_AN_REG_ADV, val); 3645 MDIO_AN_REG_ADV, val);
3959 if (ext_phy_type == 3646
3960 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 3647 bnx2x_cl45_read(bp, phy,
3961 bnx2x_cl45_read(bp, params->port,
3962 ext_phy_type,
3963 ext_phy_addr,
3964 MDIO_AN_DEVAD, 3648 MDIO_AN_DEVAD,
3965 MDIO_AN_REG_8073_2_5G, &tmp1); 3649 MDIO_AN_REG_8073_2_5G, &tmp1);
3966 3650
@@ -3972,9 +3656,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3972 SPEED_2500)) { 3656 SPEED_2500)) {
3973 u16 phy_ver; 3657 u16 phy_ver;
3974 /* Allow 2.5G for A1 and above */ 3658 /* Allow 2.5G for A1 and above */
3975 bnx2x_cl45_read(bp, params->port, 3659 bnx2x_cl45_read(bp, phy,
3976 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3977 ext_phy_addr,
3978 MDIO_PMA_DEVAD, 3660 MDIO_PMA_DEVAD,
3979 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver); 3661 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
3980 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 3662 DP(NETIF_MSG_LINK, "Add 2.5G\n");
@@ -3987,76 +3669,59 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3987 tmp1 &= 0xfffe; 3669 tmp1 &= 0xfffe;
3988 } 3670 }
3989 3671
3990 bnx2x_cl45_write(bp, params->port, 3672 bnx2x_cl45_write(bp, phy,
3991 ext_phy_type,
3992 ext_phy_addr,
3993 MDIO_AN_DEVAD, 3673 MDIO_AN_DEVAD,
3994 MDIO_AN_REG_8073_2_5G, tmp1); 3674 MDIO_AN_REG_8073_2_5G, tmp1);
3995 }
3996 3675
3997 /* Add support for CL37 (passive mode) II */ 3676 /* Add support for CL37 (passive mode) II */
3998 3677
3999 bnx2x_cl45_read(bp, params->port, 3678 bnx2x_cl45_read(bp, phy,
4000 ext_phy_type,
4001 ext_phy_addr,
4002 MDIO_AN_DEVAD, 3679 MDIO_AN_DEVAD,
4003 MDIO_AN_REG_CL37_FC_LD, 3680 MDIO_AN_REG_CL37_FC_LD,
4004 &tmp1); 3681 &tmp1);
4005 3682
4006 bnx2x_cl45_write(bp, params->port, 3683 bnx2x_cl45_write(bp, phy,
4007 ext_phy_type,
4008 ext_phy_addr,
4009 MDIO_AN_DEVAD, 3684 MDIO_AN_DEVAD,
4010 MDIO_AN_REG_CL37_FC_LD, (tmp1 | 3685 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
4011 ((params->req_duplex == DUPLEX_FULL) ? 3686 ((params->req_duplex == DUPLEX_FULL) ?
4012 0x20 : 0x40))); 3687 0x20 : 0x40)));
4013 3688
4014 /* Add support for CL37 (passive mode) III */ 3689 /* Add support for CL37 (passive mode) III */
4015 bnx2x_cl45_write(bp, params->port, 3690 bnx2x_cl45_write(bp, phy,
4016 ext_phy_type,
4017 ext_phy_addr,
4018 MDIO_AN_DEVAD, 3691 MDIO_AN_DEVAD,
4019 MDIO_AN_REG_CL37_AN, 0x1000); 3692 MDIO_AN_REG_CL37_AN, 0x1000);
4020 3693
4021 if (ext_phy_type == 3694 if (phy->type ==
4022 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 3695 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4023 /* The SNR will improve about 2db by changing 3696 /* The SNR will improve about 2db by changing
4024 BW and FEE main tap. Rest commands are executed 3697 BW and FEE main tap. Rest commands are executed
4025 after link is up*/ 3698 after link is up*/
4026 /*Change FFE main cursor to 5 in EDC register*/ 3699 /*Change FFE main cursor to 5 in EDC register*/
4027 if (bnx2x_8073_is_snr_needed(params)) 3700 if (bnx2x_8073_is_snr_needed(bp, phy))
4028 bnx2x_cl45_write(bp, params->port, 3701 bnx2x_cl45_write(bp, phy,
4029 ext_phy_type,
4030 ext_phy_addr,
4031 MDIO_PMA_DEVAD, 3702 MDIO_PMA_DEVAD,
4032 MDIO_PMA_REG_EDC_FFE_MAIN, 3703 MDIO_PMA_REG_EDC_FFE_MAIN,
4033 0xFB0C); 3704 0xFB0C);
4034 3705
4035 /* Enable FEC (Forware Error Correction) 3706 /* Enable FEC (Forware Error Correction)
4036 Request in the AN */ 3707 Request in the AN */
4037 bnx2x_cl45_read(bp, params->port, 3708 bnx2x_cl45_read(bp, phy,
4038 ext_phy_type,
4039 ext_phy_addr,
4040 MDIO_AN_DEVAD, 3709 MDIO_AN_DEVAD,
4041 MDIO_AN_REG_ADV2, &tmp1); 3710 MDIO_AN_REG_ADV2, &tmp1);
4042 3711
4043 tmp1 |= (1<<15); 3712 tmp1 |= (1<<15);
4044 3713
4045 bnx2x_cl45_write(bp, params->port, 3714 bnx2x_cl45_write(bp, phy,
4046 ext_phy_type,
4047 ext_phy_addr,
4048 MDIO_AN_DEVAD, 3715 MDIO_AN_DEVAD,
4049 MDIO_AN_REG_ADV2, tmp1); 3716 MDIO_AN_REG_ADV2, tmp1);
4050 3717
4051 } 3718 }
4052 3719
4053 bnx2x_ext_phy_set_pause(params, vars); 3720 bnx2x_ext_phy_set_pause(params, phy, vars);
4054 3721
4055 /* Restart autoneg */ 3722 /* Restart autoneg */
4056 msleep(500); 3723 msleep(500);
4057 bnx2x_cl45_write(bp, params->port, 3724 bnx2x_cl45_write(bp, phy,
4058 ext_phy_type,
4059 ext_phy_addr,
4060 MDIO_AN_DEVAD, 3725 MDIO_AN_DEVAD,
4061 MDIO_AN_REG_CTRL, 0x1200); 3726 MDIO_AN_REG_CTRL, 0x1200);
4062 DP(NETIF_MSG_LINK, "807x Autoneg Restart: " 3727 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
@@ -4080,25 +3745,19 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4080 3745
4081 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 3746 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4082 /* enable LASI */ 3747 /* enable LASI */
4083 bnx2x_cl45_write(bp, params->port, 3748 bnx2x_cl45_write(bp, phy,
4084 ext_phy_type,
4085 ext_phy_addr,
4086 MDIO_PMA_DEVAD, 3749 MDIO_PMA_DEVAD,
4087 MDIO_PMA_REG_RX_ALARM_CTRL, 3750 MDIO_PMA_REG_RX_ALARM_CTRL,
4088 rx_alarm_ctrl_val); 3751 rx_alarm_ctrl_val);
4089 3752
4090 bnx2x_cl45_write(bp, params->port, 3753 bnx2x_cl45_write(bp, phy,
4091 ext_phy_type,
4092 ext_phy_addr,
4093 MDIO_PMA_DEVAD, 3754 MDIO_PMA_DEVAD,
4094 MDIO_PMA_REG_LASI_CTRL, 3755 MDIO_PMA_REG_LASI_CTRL,
4095 lasi_ctrl_val); 3756 lasi_ctrl_val);
4096 3757
4097 /* Initially configure MOD_ABS to interrupt when 3758 /* Initially configure MOD_ABS to interrupt when
4098 module is presence( bit 8) */ 3759 module is presence( bit 8) */
4099 bnx2x_cl45_read(bp, params->port, 3760 bnx2x_cl45_read(bp, phy,
4100 ext_phy_type,
4101 ext_phy_addr,
4102 MDIO_PMA_DEVAD, 3761 MDIO_PMA_DEVAD,
4103 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 3762 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4104 /* Set EDC off by setting OPTXLOS signal input to low 3763 /* Set EDC off by setting OPTXLOS signal input to low
@@ -4106,23 +3765,17 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4106 When the EDC is off it locks onto a reference clock and 3765 When the EDC is off it locks onto a reference clock and
4107 avoids becoming 'lost'.*/ 3766 avoids becoming 'lost'.*/
4108 mod_abs &= ~((1<<8) | (1<<9)); 3767 mod_abs &= ~((1<<8) | (1<<9));
4109 bnx2x_cl45_write(bp, params->port, 3768 bnx2x_cl45_write(bp, phy,
4110 ext_phy_type,
4111 ext_phy_addr,
4112 MDIO_PMA_DEVAD, 3769 MDIO_PMA_DEVAD,
4113 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 3770 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4114 3771
4115 /* Make MOD_ABS give interrupt on change */ 3772 /* Make MOD_ABS give interrupt on change */
4116 bnx2x_cl45_read(bp, params->port, 3773 bnx2x_cl45_read(bp, phy,
4117 ext_phy_type,
4118 ext_phy_addr,
4119 MDIO_PMA_DEVAD, 3774 MDIO_PMA_DEVAD,
4120 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 3775 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4121 &val); 3776 &val);
4122 val |= (1<<12); 3777 val |= (1<<12);
4123 bnx2x_cl45_write(bp, params->port, 3778 bnx2x_cl45_write(bp, phy,
4124 ext_phy_type,
4125 ext_phy_addr,
4126 MDIO_PMA_DEVAD, 3779 MDIO_PMA_DEVAD,
4127 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 3780 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4128 val); 3781 val);
@@ -4131,32 +3784,24 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4131 8727 GPIO0 status which reflect SFP+ module 3784 8727 GPIO0 status which reflect SFP+ module
4132 over-current */ 3785 over-current */
4133 3786
4134 bnx2x_cl45_read(bp, params->port, 3787 bnx2x_cl45_read(bp, phy,
4135 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4136 ext_phy_addr,
4137 MDIO_PMA_DEVAD, 3788 MDIO_PMA_DEVAD,
4138 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 3789 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4139 &val); 3790 &val);
4140 val &= 0xff8f; /* Reset bits 4-6 */ 3791 val &= 0xff8f; /* Reset bits 4-6 */
4141 bnx2x_cl45_write(bp, params->port, 3792 bnx2x_cl45_write(bp, phy,
4142 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4143 ext_phy_addr,
4144 MDIO_PMA_DEVAD, 3793 MDIO_PMA_DEVAD,
4145 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 3794 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4146 val); 3795 val);
4147 3796
4148 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1); 3797 bnx2x_8727_power_module(bp, params, phy, 1);
4149 3798
4150 bnx2x_cl45_read(bp, params->port, 3799 bnx2x_cl45_read(bp, phy,
4151 ext_phy_type,
4152 ext_phy_addr,
4153 MDIO_PMA_DEVAD, 3800 MDIO_PMA_DEVAD,
4154 MDIO_PMA_REG_M8051_MSGOUT_REG, 3801 MDIO_PMA_REG_M8051_MSGOUT_REG,
4155 &tmp1); 3802 &tmp1);
4156 3803
4157 bnx2x_cl45_read(bp, params->port, 3804 bnx2x_cl45_read(bp, phy,
4158 ext_phy_type,
4159 ext_phy_addr,
4160 MDIO_PMA_DEVAD, 3805 MDIO_PMA_DEVAD,
4161 MDIO_PMA_REG_RX_ALARM, &tmp1); 3806 MDIO_PMA_REG_RX_ALARM, &tmp1);
4162 3807
@@ -4164,19 +3809,13 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4164 if (params->req_line_speed == SPEED_1000) { 3809 if (params->req_line_speed == SPEED_1000) {
4165 3810
4166 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 3811 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4167 bnx2x_cl45_write(bp, params->port, 3812 bnx2x_cl45_write(bp, phy,
4168 ext_phy_type,
4169 ext_phy_addr,
4170 MDIO_PMA_DEVAD, 3813 MDIO_PMA_DEVAD,
4171 MDIO_PMA_REG_CTRL, 0x40); 3814 MDIO_PMA_REG_CTRL, 0x40);
4172 bnx2x_cl45_write(bp, params->port, 3815 bnx2x_cl45_write(bp, phy,
4173 ext_phy_type,
4174 ext_phy_addr,
4175 MDIO_PMA_DEVAD, 3816 MDIO_PMA_DEVAD,
4176 MDIO_PMA_REG_10G_CTRL2, 0xD); 3817 MDIO_PMA_REG_10G_CTRL2, 0xD);
4177 bnx2x_cl45_read(bp, params->port, 3818 bnx2x_cl45_read(bp, phy,
4178 ext_phy_type,
4179 ext_phy_addr,
4180 MDIO_PMA_DEVAD, 3819 MDIO_PMA_DEVAD,
4181 MDIO_PMA_REG_10G_CTRL2, &tmp1); 3820 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4182 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 3821 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
@@ -4189,28 +3828,22 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4189 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 3828 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
4190 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 3829 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4191 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 3830 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
4192 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3831 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4193 ext_phy_addr, MDIO_AN_DEVAD, 3832 MDIO_AN_REG_8727_MISC_CTRL, 0);
4194 MDIO_PMA_REG_8727_MISC_CTRL, 0); 3833 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4195 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4196 ext_phy_addr, MDIO_AN_DEVAD,
4197 MDIO_AN_REG_CL37_AN, 0x1300); 3834 MDIO_AN_REG_CL37_AN, 0x1300);
4198 } else { 3835 } else {
4199 /* Since the 8727 has only single reset pin, 3836 /* Since the 8727 has only single reset pin,
4200 need to set the 10G registers although it is 3837 need to set the 10G registers although it is
4201 default */ 3838 default */
4202 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3839 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4203 ext_phy_addr, MDIO_AN_DEVAD,
4204 MDIO_AN_REG_8727_MISC_CTRL, 3840 MDIO_AN_REG_8727_MISC_CTRL,
4205 0x0020); 3841 0x0020);
4206 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3842 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4207 ext_phy_addr, MDIO_AN_DEVAD,
4208 MDIO_AN_REG_CL37_AN, 0x0100); 3843 MDIO_AN_REG_CL37_AN, 0x0100);
4209 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3844 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
4210 ext_phy_addr, MDIO_PMA_DEVAD,
4211 MDIO_PMA_REG_CTRL, 0x2040); 3845 MDIO_PMA_REG_CTRL, 0x2040);
4212 bnx2x_cl45_write(bp, params->port, ext_phy_type, 3846 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
4213 ext_phy_addr, MDIO_PMA_DEVAD,
4214 MDIO_PMA_REG_10G_CTRL2, 0x0008); 3847 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4215 } 3848 }
4216 3849
@@ -4218,9 +3851,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4218 * to 100Khz since some DACs(direct attached cables) do 3851 * to 100Khz since some DACs(direct attached cables) do
4219 * not work at 400Khz. 3852 * not work at 400Khz.
4220 */ 3853 */
4221 bnx2x_cl45_write(bp, params->port, 3854 bnx2x_cl45_write(bp, phy,
4222 ext_phy_type,
4223 ext_phy_addr,
4224 MDIO_PMA_DEVAD, 3855 MDIO_PMA_DEVAD,
4225 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 3856 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4226 0xa001); 3857 0xa001);
@@ -4232,16 +3863,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4232 "TX_CTRL2 0x%x\n", 3863 "TX_CTRL2 0x%x\n",
4233 params->xgxs_config_tx[0], 3864 params->xgxs_config_tx[0],
4234 params->xgxs_config_tx[1]); 3865 params->xgxs_config_tx[1]);
4235 bnx2x_cl45_write(bp, params->port, 3866 bnx2x_cl45_write(bp, phy,
4236 ext_phy_type,
4237 ext_phy_addr,
4238 MDIO_PMA_DEVAD, 3867 MDIO_PMA_DEVAD,
4239 MDIO_PMA_REG_8727_TX_CTRL1, 3868 MDIO_PMA_REG_8727_TX_CTRL1,
4240 params->xgxs_config_tx[0]); 3869 params->xgxs_config_tx[0]);
4241 3870
4242 bnx2x_cl45_write(bp, params->port, 3871 bnx2x_cl45_write(bp, phy,
4243 ext_phy_type,
4244 ext_phy_addr,
4245 MDIO_PMA_DEVAD, 3872 MDIO_PMA_DEVAD,
4246 MDIO_PMA_REG_8727_TX_CTRL2, 3873 MDIO_PMA_REG_8727_TX_CTRL2,
4247 params->xgxs_config_tx[1]); 3874 params->xgxs_config_tx[1]);
@@ -4256,40 +3883,30 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4256 DP(NETIF_MSG_LINK, 3883 DP(NETIF_MSG_LINK,
4257 "Setting the SFX7101 LASI indication\n"); 3884 "Setting the SFX7101 LASI indication\n");
4258 3885
4259 bnx2x_cl45_write(bp, params->port, 3886 bnx2x_cl45_write(bp, phy,
4260 ext_phy_type,
4261 ext_phy_addr,
4262 MDIO_PMA_DEVAD, 3887 MDIO_PMA_DEVAD,
4263 MDIO_PMA_REG_LASI_CTRL, 0x1); 3888 MDIO_PMA_REG_LASI_CTRL, 0x1);
4264 DP(NETIF_MSG_LINK, 3889 DP(NETIF_MSG_LINK,
4265 "Setting the SFX7101 LED to blink on traffic\n"); 3890 "Setting the SFX7101 LED to blink on traffic\n");
4266 bnx2x_cl45_write(bp, params->port, 3891 bnx2x_cl45_write(bp, phy,
4267 ext_phy_type,
4268 ext_phy_addr,
4269 MDIO_PMA_DEVAD, 3892 MDIO_PMA_DEVAD,
4270 MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 3893 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4271 3894
4272 bnx2x_ext_phy_set_pause(params, vars); 3895 bnx2x_ext_phy_set_pause(params, phy, vars);
4273 /* Restart autoneg */ 3896 /* Restart autoneg */
4274 bnx2x_cl45_read(bp, params->port, 3897 bnx2x_cl45_read(bp, phy,
4275 ext_phy_type,
4276 ext_phy_addr,
4277 MDIO_AN_DEVAD, 3898 MDIO_AN_DEVAD,
4278 MDIO_AN_REG_CTRL, &val); 3899 MDIO_AN_REG_CTRL, &val);
4279 val |= 0x200; 3900 val |= 0x200;
4280 bnx2x_cl45_write(bp, params->port, 3901 bnx2x_cl45_write(bp, phy,
4281 ext_phy_type,
4282 ext_phy_addr,
4283 MDIO_AN_DEVAD, 3902 MDIO_AN_DEVAD,
4284 MDIO_AN_REG_CTRL, val); 3903 MDIO_AN_REG_CTRL, val);
4285 3904
4286 /* Save spirom version */ 3905 /* Save spirom version */
4287 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3906 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
4288 ext_phy_addr, MDIO_PMA_DEVAD,
4289 MDIO_PMA_REG_7101_VER1, &fw_ver1); 3907 MDIO_PMA_REG_7101_VER1, &fw_ver1);
4290 3908
4291 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3909 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
4292 ext_phy_addr, MDIO_PMA_DEVAD,
4293 MDIO_PMA_REG_7101_VER2, &fw_ver2); 3910 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4294 3911
4295 bnx2x_save_spirom_version(params->bp, params->port, 3912 bnx2x_save_spirom_version(params->bp, params->port,
@@ -4307,34 +3924,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4307 u16 autoneg_val, an_1000_val, an_10_100_val, temp; 3924 u16 autoneg_val, an_1000_val, an_10_100_val, temp;
4308 temp = vars->line_speed; 3925 temp = vars->line_speed;
4309 vars->line_speed = SPEED_10000; 3926 vars->line_speed = SPEED_10000;
4310 bnx2x_set_autoneg(params, vars, 0); 3927 bnx2x_set_autoneg(phy, params, vars, 0);
4311 bnx2x_program_serdes(params, vars); 3928 bnx2x_program_serdes(phy, params, vars);
4312 vars->line_speed = temp; 3929 vars->line_speed = temp;
4313 3930
4314 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 3931 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4315 1 << NIG_LATCH_BC_ENABLE_MI_INT); 3932 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4316 3933
4317 bnx2x_cl45_write(bp, params->port, 3934 bnx2x_cl45_write(bp, phy,
4318 ext_phy_type,
4319 ext_phy_addr,
4320 MDIO_PMA_DEVAD, 3935 MDIO_PMA_DEVAD,
4321 MDIO_PMA_REG_CTRL, 0x0000); 3936 MDIO_PMA_REG_CTRL, 0x0000);
4322 3937
4323 bnx2x_8481_set_led(params, ext_phy_type, ext_phy_addr); 3938 bnx2x_8481_set_led(bp, phy);
4324 3939
4325 bnx2x_cl45_read(bp, params->port, 3940 bnx2x_cl45_read(bp, phy,
4326 ext_phy_type,
4327 ext_phy_addr,
4328 MDIO_AN_DEVAD, 3941 MDIO_AN_DEVAD,
4329 MDIO_AN_REG_8481_1000T_CTRL, 3942 MDIO_AN_REG_8481_1000T_CTRL,
4330 &an_1000_val); 3943 &an_1000_val);
4331 bnx2x_ext_phy_set_pause(params, vars); 3944 bnx2x_ext_phy_set_pause(params, phy, vars);
4332 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3945 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
4333 ext_phy_addr, MDIO_AN_DEVAD,
4334 MDIO_AN_REG_8481_LEGACY_AN_ADV, 3946 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4335 &an_10_100_val); 3947 &an_10_100_val);
4336 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3948 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
4337 ext_phy_addr, MDIO_AN_DEVAD,
4338 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 3949 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4339 &autoneg_val); 3950 &autoneg_val);
4340 /* Disable forced speed */ 3951 /* Disable forced speed */
@@ -4354,9 +3965,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4354 } else 3965 } else
4355 an_1000_val &= ~((1<<8) | (1<<9)); 3966 an_1000_val &= ~((1<<8) | (1<<9));
4356 3967
4357 bnx2x_cl45_write(bp, params->port, 3968 bnx2x_cl45_write(bp, phy,
4358 ext_phy_type,
4359 ext_phy_addr,
4360 MDIO_AN_DEVAD, 3969 MDIO_AN_DEVAD,
4361 MDIO_AN_REG_8481_1000T_CTRL, 3970 MDIO_AN_REG_8481_1000T_CTRL,
4362 an_1000_val); 3971 an_1000_val);
@@ -4393,9 +4002,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4393 if (params->req_line_speed == SPEED_100) { 4002 if (params->req_line_speed == SPEED_100) {
4394 autoneg_val |= (1<<13); 4003 autoneg_val |= (1<<13);
4395 /* Enabled AUTO-MDIX when autoneg is disabled */ 4004 /* Enabled AUTO-MDIX when autoneg is disabled */
4396 bnx2x_cl45_write(bp, params->port, 4005 bnx2x_cl45_write(bp, phy,
4397 ext_phy_type,
4398 ext_phy_addr,
4399 MDIO_AN_DEVAD, 4006 MDIO_AN_DEVAD,
4400 MDIO_AN_REG_8481_AUX_CTRL, 4007 MDIO_AN_REG_8481_AUX_CTRL,
4401 (1<<15 | 1<<9 | 7<<0)); 4008 (1<<15 | 1<<9 | 7<<0));
@@ -4403,18 +4010,14 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4403 } 4010 }
4404 if (params->req_line_speed == SPEED_10) { 4011 if (params->req_line_speed == SPEED_10) {
4405 /* Enabled AUTO-MDIX when autoneg is disabled */ 4012 /* Enabled AUTO-MDIX when autoneg is disabled */
4406 bnx2x_cl45_write(bp, params->port, 4013 bnx2x_cl45_write(bp, phy,
4407 ext_phy_type,
4408 ext_phy_addr,
4409 MDIO_AN_DEVAD, 4014 MDIO_AN_DEVAD,
4410 MDIO_AN_REG_8481_AUX_CTRL, 4015 MDIO_AN_REG_8481_AUX_CTRL,
4411 (1<<15 | 1<<9 | 7<<0)); 4016 (1<<15 | 1<<9 | 7<<0));
4412 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 4017 DP(NETIF_MSG_LINK, "Setting 10M force\n");
4413 } 4018 }
4414 4019
4415 bnx2x_cl45_write(bp, params->port, 4020 bnx2x_cl45_write(bp, phy,
4416 ext_phy_type,
4417 ext_phy_addr,
4418 MDIO_AN_DEVAD, 4021 MDIO_AN_DEVAD,
4419 MDIO_AN_REG_8481_LEGACY_AN_ADV, 4022 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4420 an_10_100_val); 4023 an_10_100_val);
@@ -4422,9 +4025,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4422 if (params->req_duplex == DUPLEX_FULL) 4025 if (params->req_duplex == DUPLEX_FULL)
4423 autoneg_val |= (1<<8); 4026 autoneg_val |= (1<<8);
4424 4027
4425 bnx2x_cl45_write(bp, params->port, 4028 bnx2x_cl45_write(bp, phy,
4426 ext_phy_type,
4427 ext_phy_addr,
4428 MDIO_AN_DEVAD, 4029 MDIO_AN_DEVAD,
4429 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 4030 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4430 autoneg_val); 4031 autoneg_val);
@@ -4436,74 +4037,49 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
4436 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 4037 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4437 /* Restart autoneg for 10G*/ 4038 /* Restart autoneg for 10G*/
4438 4039
4439 bnx2x_cl45_write(bp, params->port, 4040 bnx2x_cl45_write(bp, phy,
4440 ext_phy_type,
4441 ext_phy_addr,
4442 MDIO_AN_DEVAD, 4041 MDIO_AN_DEVAD,
4443 MDIO_AN_REG_CTRL, 4042 MDIO_AN_REG_CTRL,
4444 0x3200); 4043 0x3200);
4445 4044
4446 } else if (params->req_line_speed != SPEED_10 && 4045 } else if (params->req_line_speed != SPEED_10 &&
4447 params->req_line_speed != SPEED_100) 4046 params->req_line_speed != SPEED_100)
4448 bnx2x_cl45_write(bp, params->port, 4047 bnx2x_cl45_write(bp, phy,
4449 ext_phy_type,
4450 ext_phy_addr,
4451 MDIO_AN_DEVAD, 4048 MDIO_AN_DEVAD,
4452 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 4049 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
4453 1); 4050 1);
4454 4051
4455 /* Save spirom version */ 4052 /* Save spirom version */
4456 bnx2x_save_8481_spirom_version(bp, params->port, 4053 bnx2x_save_8481_spirom_version(phy, params,
4457 ext_phy_addr, 4054 params->shmem_base);
4458 params->shmem_base);
4459 break; 4055 break;
4460 } 4056 }
4461 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 4057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4462 DP(NETIF_MSG_LINK, 4058 DP(NETIF_MSG_LINK,
4463 "XGXS PHY Failure detected 0x%x\n", 4059 "XGXS PHY Failure detected 0x%x\n",
4464 params->ext_phy_config); 4060 phy->type);
4465 rc = -EINVAL; 4061 rc = -EINVAL;
4466 break; 4062 break;
4467 default:
4468 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4469 params->ext_phy_config);
4470 rc = -EINVAL;
4471 break;
4472 }
4473
4474 } else { /* SerDes */
4475
4476 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4477 switch (ext_phy_type) {
4478 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4479 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4480 break;
4481
4482 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4483 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4484 break;
4485 4063
4486 default: 4064 default:
4487 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", 4065 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4488 params->ext_phy_config); 4066 phy->type);
4489 break; 4067 break;
4490 } 4068 }
4491 } 4069 }
4492 return rc; 4070 return rc;
4493} 4071}
4494 4072
4495static void bnx2x_8727_handle_mod_abs(struct link_params *params) 4073static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
4074 struct link_params *params)
4496{ 4075{
4497 struct bnx2x *bp = params->bp; 4076 struct bnx2x *bp = params->bp;
4498 u16 mod_abs, rx_alarm_status; 4077 u16 mod_abs, rx_alarm_status;
4499 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4500 u32 val = REG_RD(bp, params->shmem_base + 4078 u32 val = REG_RD(bp, params->shmem_base +
4501 offsetof(struct shmem_region, dev_info. 4079 offsetof(struct shmem_region, dev_info.
4502 port_feature_config[params->port]. 4080 port_feature_config[params->port].
4503 config)); 4081 config));
4504 bnx2x_cl45_read(bp, params->port, 4082 bnx2x_cl45_read(bp, phy,
4505 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4506 ext_phy_addr,
4507 MDIO_PMA_DEVAD, 4083 MDIO_PMA_DEVAD,
4508 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 4084 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4509 if (mod_abs & (1<<8)) { 4085 if (mod_abs & (1<<8)) {
@@ -4519,17 +4095,13 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4519 When the EDC is off it locks onto a reference clock and 4095 When the EDC is off it locks onto a reference clock and
4520 avoids becoming 'lost'.*/ 4096 avoids becoming 'lost'.*/
4521 mod_abs &= ~((1<<8)|(1<<9)); 4097 mod_abs &= ~((1<<8)|(1<<9));
4522 bnx2x_cl45_write(bp, params->port, 4098 bnx2x_cl45_write(bp, phy,
4523 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4524 ext_phy_addr,
4525 MDIO_PMA_DEVAD, 4099 MDIO_PMA_DEVAD,
4526 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 4100 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4527 4101
4528 /* Clear RX alarm since it stays up as long as 4102 /* Clear RX alarm since it stays up as long as
4529 the mod_abs wasn't changed */ 4103 the mod_abs wasn't changed */
4530 bnx2x_cl45_read(bp, params->port, 4104 bnx2x_cl45_read(bp, phy,
4531 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4532 ext_phy_addr,
4533 MDIO_PMA_DEVAD, 4105 MDIO_PMA_DEVAD,
4534 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 4106 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4535 4107
@@ -4547,9 +4119,7 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4547 this signal will then correctly indicate the presence or 4119 this signal will then correctly indicate the presence or
4548 absence of the Rx signal. (bit 9) */ 4120 absence of the Rx signal. (bit 9) */
4549 mod_abs |= ((1<<8)|(1<<9)); 4121 mod_abs |= ((1<<8)|(1<<9));
4550 bnx2x_cl45_write(bp, params->port, 4122 bnx2x_cl45_write(bp, phy,
4551 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4552 ext_phy_addr,
4553 MDIO_PMA_DEVAD, 4123 MDIO_PMA_DEVAD,
4554 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 4124 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4555 4125
@@ -4557,22 +4127,17 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4557 the mod_abs wasn't changed. This is need to be done 4127 the mod_abs wasn't changed. This is need to be done
4558 before calling the module detection, otherwise it will clear 4128 before calling the module detection, otherwise it will clear
4559 the link update alarm */ 4129 the link update alarm */
4560 bnx2x_cl45_read(bp, params->port, 4130 bnx2x_cl45_read(bp, phy,
4561 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4562 ext_phy_addr,
4563 MDIO_PMA_DEVAD, 4131 MDIO_PMA_DEVAD,
4564 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 4132 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4565 4133
4566 4134
4567 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 4135 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4568 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 4136 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4569 bnx2x_sfp_set_transmitter(bp, params->port, 4137 bnx2x_sfp_set_transmitter(bp, phy, 0);
4570 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4571 ext_phy_addr, 0);
4572 4138
4573 if (bnx2x_wait_for_sfp_module_initialized(params) 4139 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
4574 == 0) 4140 bnx2x_sfp_module_detection(phy, params);
4575 bnx2x_sfp_module_detection(params);
4576 else 4141 else
4577 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 4142 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4578 } 4143 }
@@ -4584,22 +4149,18 @@ static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4584} 4149}
4585 4150
4586 4151
4587static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, 4152static u8 bnx2x_ext_phy_is_link_up(struct bnx2x_phy *phy,
4153 struct link_params *params,
4588 struct link_vars *vars, 4154 struct link_vars *vars,
4589 u8 is_mi_int) 4155 u8 is_mi_int)
4590{ 4156{
4591 struct bnx2x *bp = params->bp; 4157 struct bnx2x *bp = params->bp;
4592 u32 ext_phy_type;
4593 u8 ext_phy_addr;
4594 u16 val1 = 0, val2; 4158 u16 val1 = 0, val2;
4595 u16 rx_sd, pcs_status; 4159 u16 rx_sd, pcs_status;
4596 u8 ext_phy_link_up = 0; 4160 u8 ext_phy_link_up = 0;
4597 u8 port = params->port;
4598 4161
4599 if (vars->phy_flags & PHY_XGXS_FLAG) { 4162 if (vars->phy_flags & PHY_XGXS_FLAG) {
4600 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config); 4163 switch (phy->type) {
4601 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4602 switch (ext_phy_type) {
4603 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 4164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4604 DP(NETIF_MSG_LINK, "XGXS Direct\n"); 4165 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4605 ext_phy_link_up = 1; 4166 ext_phy_link_up = 1;
@@ -4607,29 +4168,24 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4607 4168
4608 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 4169 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4609 DP(NETIF_MSG_LINK, "XGXS 8705\n"); 4170 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4610 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4171 bnx2x_cl45_read(bp, phy,
4611 ext_phy_addr,
4612 MDIO_WIS_DEVAD, 4172 MDIO_WIS_DEVAD,
4613 MDIO_WIS_REG_LASI_STATUS, &val1); 4173 MDIO_WIS_REG_LASI_STATUS, &val1);
4614 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 4174 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4615 4175
4616 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4176 bnx2x_cl45_read(bp, phy,
4617 ext_phy_addr,
4618 MDIO_WIS_DEVAD, 4177 MDIO_WIS_DEVAD,
4619 MDIO_WIS_REG_LASI_STATUS, &val1); 4178 MDIO_WIS_REG_LASI_STATUS, &val1);
4620 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 4179 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4621 4180
4622 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4181 bnx2x_cl45_read(bp, phy,
4623 ext_phy_addr,
4624 MDIO_PMA_DEVAD, 4182 MDIO_PMA_DEVAD,
4625 MDIO_PMA_REG_RX_SD, &rx_sd); 4183 MDIO_PMA_REG_RX_SD, &rx_sd);
4626 4184
4627 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4185 bnx2x_cl45_read(bp, phy,
4628 ext_phy_addr,
4629 1, 4186 1,
4630 0xc809, &val1); 4187 0xc809, &val1);
4631 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4188 bnx2x_cl45_read(bp, phy,
4632 ext_phy_addr,
4633 1, 4189 1,
4634 0xc809, &val1); 4190 0xc809, &val1);
4635 4191
@@ -4644,36 +4200,29 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4644 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 4200 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4645 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 4201 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4646 /* Clear RX Alarm*/ 4202 /* Clear RX Alarm*/
4647 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4203 bnx2x_cl45_read(bp, phy,
4648 ext_phy_addr,
4649 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, 4204 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4650 &val2); 4205 &val2);
4651 /* clear LASI indication*/ 4206 /* clear LASI indication*/
4652 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4207 bnx2x_cl45_read(bp, phy,
4653 ext_phy_addr,
4654 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, 4208 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4655 &val1); 4209 &val1);
4656 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4210 bnx2x_cl45_read(bp, phy,
4657 ext_phy_addr,
4658 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, 4211 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4659 &val2); 4212 &val2);
4660 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->" 4213 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4661 "0x%x\n", val1, val2); 4214 "0x%x\n", val1, val2);
4662 4215
4663 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4216 bnx2x_cl45_read(bp, phy,
4664 ext_phy_addr,
4665 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, 4217 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4666 &rx_sd); 4218 &rx_sd);
4667 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4219 bnx2x_cl45_read(bp, phy,
4668 ext_phy_addr,
4669 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, 4220 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4670 &pcs_status); 4221 &pcs_status);
4671 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4222 bnx2x_cl45_read(bp, phy,
4672 ext_phy_addr,
4673 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, 4223 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4674 &val2); 4224 &val2);
4675 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4225 bnx2x_cl45_read(bp, phy,
4676 ext_phy_addr,
4677 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, 4226 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4678 &val2); 4227 &val2);
4679 4228
@@ -4687,13 +4236,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4687 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) || 4236 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4688 (val2 & (1<<1))); 4237 (val2 & (1<<1)));
4689 if (ext_phy_link_up) { 4238 if (ext_phy_link_up) {
4690 if (ext_phy_type == 4239 if (phy->type ==
4691 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 4240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4692 /* If transmitter is disabled, 4241 /* If transmitter is disabled,
4693 ignore false link up indication */ 4242 ignore false link up indication */
4694 bnx2x_cl45_read(bp, params->port, 4243 bnx2x_cl45_read(bp, phy,
4695 ext_phy_type,
4696 ext_phy_addr,
4697 MDIO_PMA_DEVAD, 4244 MDIO_PMA_DEVAD,
4698 MDIO_PMA_REG_PHY_IDENTIFIER, 4245 MDIO_PMA_REG_PHY_IDENTIFIER,
4699 &val1); 4246 &val1);
@@ -4716,18 +4263,14 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4716 u16 link_status = 0; 4263 u16 link_status = 0;
4717 u16 rx_alarm_status; 4264 u16 rx_alarm_status;
4718 /* Check the LASI */ 4265 /* Check the LASI */
4719 bnx2x_cl45_read(bp, params->port, 4266 bnx2x_cl45_read(bp, phy,
4720 ext_phy_type,
4721 ext_phy_addr,
4722 MDIO_PMA_DEVAD, 4267 MDIO_PMA_DEVAD,
4723 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 4268 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4724 4269
4725 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 4270 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4726 rx_alarm_status); 4271 rx_alarm_status);
4727 4272
4728 bnx2x_cl45_read(bp, params->port, 4273 bnx2x_cl45_read(bp, phy,
4729 ext_phy_type,
4730 ext_phy_addr,
4731 MDIO_PMA_DEVAD, 4274 MDIO_PMA_DEVAD,
4732 MDIO_PMA_REG_LASI_STATUS, &val1); 4275 MDIO_PMA_REG_LASI_STATUS, &val1);
4733 4276
@@ -4736,9 +4279,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4736 val1); 4279 val1);
4737 4280
4738 /* Clear MSG-OUT */ 4281 /* Clear MSG-OUT */
4739 bnx2x_cl45_read(bp, params->port, 4282 bnx2x_cl45_read(bp, phy,
4740 ext_phy_type,
4741 ext_phy_addr,
4742 MDIO_PMA_DEVAD, 4283 MDIO_PMA_DEVAD,
4743 MDIO_PMA_REG_M8051_MSGOUT_REG, 4284 MDIO_PMA_REG_M8051_MSGOUT_REG,
4744 &val1); 4285 &val1);
@@ -4751,9 +4292,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4751 FEATURE_CONFIG_BCM8727_NOC) && 4292 FEATURE_CONFIG_BCM8727_NOC) &&
4752 !(rx_alarm_status & (1<<5))) { 4293 !(rx_alarm_status & (1<<5))) {
4753 /* Check over-current using 8727 GPIO0 input*/ 4294 /* Check over-current using 8727 GPIO0 input*/
4754 bnx2x_cl45_read(bp, params->port, 4295 bnx2x_cl45_read(bp, phy,
4755 ext_phy_type,
4756 ext_phy_addr,
4757 MDIO_PMA_DEVAD, 4296 MDIO_PMA_DEVAD,
4758 MDIO_PMA_REG_8727_GPIO_CTRL, 4297 MDIO_PMA_REG_8727_GPIO_CTRL,
4759 &val1); 4298 &val1);
@@ -4769,31 +4308,23 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4769 * Disable all RX_ALARMs except for 4308 * Disable all RX_ALARMs except for
4770 * mod_abs 4309 * mod_abs
4771 */ 4310 */
4772 bnx2x_cl45_write(bp, params->port, 4311 bnx2x_cl45_write(bp, phy,
4773 ext_phy_type,
4774 ext_phy_addr,
4775 MDIO_PMA_DEVAD, 4312 MDIO_PMA_DEVAD,
4776 MDIO_PMA_REG_RX_ALARM_CTRL, 4313 MDIO_PMA_REG_RX_ALARM_CTRL,
4777 (1<<5)); 4314 (1<<5));
4778 4315
4779 bnx2x_cl45_read(bp, params->port, 4316 bnx2x_cl45_read(bp, phy,
4780 ext_phy_type,
4781 ext_phy_addr,
4782 MDIO_PMA_DEVAD, 4317 MDIO_PMA_DEVAD,
4783 MDIO_PMA_REG_PHY_IDENTIFIER, 4318 MDIO_PMA_REG_PHY_IDENTIFIER,
4784 &val1); 4319 &val1);
4785 /* Wait for module_absent_event */ 4320 /* Wait for module_absent_event */
4786 val1 |= (1<<8); 4321 val1 |= (1<<8);
4787 bnx2x_cl45_write(bp, params->port, 4322 bnx2x_cl45_write(bp, phy,
4788 ext_phy_type,
4789 ext_phy_addr,
4790 MDIO_PMA_DEVAD, 4323 MDIO_PMA_DEVAD,
4791 MDIO_PMA_REG_PHY_IDENTIFIER, 4324 MDIO_PMA_REG_PHY_IDENTIFIER,
4792 val1); 4325 val1);
4793 /* Clear RX alarm */ 4326 /* Clear RX alarm */
4794 bnx2x_cl45_read(bp, params->port, 4327 bnx2x_cl45_read(bp, phy,
4795 ext_phy_type,
4796 ext_phy_addr,
4797 MDIO_PMA_DEVAD, 4328 MDIO_PMA_DEVAD,
4798 MDIO_PMA_REG_RX_ALARM, 4329 MDIO_PMA_REG_RX_ALARM,
4799 &rx_alarm_status); 4330 &rx_alarm_status);
@@ -4803,11 +4334,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4803 4334
4804 /* When module absent bit is set, check module */ 4335 /* When module absent bit is set, check module */
4805 if (rx_alarm_status & (1<<5)) { 4336 if (rx_alarm_status & (1<<5)) {
4806 bnx2x_8727_handle_mod_abs(params); 4337 bnx2x_8727_handle_mod_abs(phy, params);
4807 /* Enable all mod_abs and link detection bits */ 4338 /* Enable all mod_abs and link detection bits */
4808 bnx2x_cl45_write(bp, params->port, 4339 bnx2x_cl45_write(bp, phy,
4809 ext_phy_type,
4810 ext_phy_addr,
4811 MDIO_PMA_DEVAD, 4340 MDIO_PMA_DEVAD,
4812 MDIO_PMA_REG_RX_ALARM_CTRL, 4341 MDIO_PMA_REG_RX_ALARM_CTRL,
4813 ((1<<5) | (1<<2))); 4342 ((1<<5) | (1<<2)));
@@ -4815,9 +4344,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4815 4344
4816 /* If transmitter is disabled, 4345 /* If transmitter is disabled,
4817 ignore false link up indication */ 4346 ignore false link up indication */
4818 bnx2x_cl45_read(bp, params->port, 4347 bnx2x_cl45_read(bp, phy,
4819 ext_phy_type,
4820 ext_phy_addr,
4821 MDIO_PMA_DEVAD, 4348 MDIO_PMA_DEVAD,
4822 MDIO_PMA_REG_PHY_IDENTIFIER, 4349 MDIO_PMA_REG_PHY_IDENTIFIER,
4823 &val1); 4350 &val1);
@@ -4827,9 +4354,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4827 break; 4354 break;
4828 } 4355 }
4829 4356
4830 bnx2x_cl45_read(bp, params->port, 4357 bnx2x_cl45_read(bp, phy,
4831 ext_phy_type,
4832 ext_phy_addr,
4833 MDIO_PMA_DEVAD, 4358 MDIO_PMA_DEVAD,
4834 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 4359 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4835 &link_status); 4360 &link_status);
@@ -4862,16 +4387,12 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4862 u16 link_status = 0; 4387 u16 link_status = 0;
4863 u16 an1000_status = 0; 4388 u16 an1000_status = 0;
4864 4389
4865 if (ext_phy_type == 4390 if (phy->type ==
4866 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { 4391 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4867 bnx2x_cl45_read(bp, params->port, 4392 bnx2x_cl45_read(bp, phy,
4868 ext_phy_type,
4869 ext_phy_addr,
4870 MDIO_PCS_DEVAD, 4393 MDIO_PCS_DEVAD,
4871 MDIO_PCS_REG_LASI_STATUS, &val1); 4394 MDIO_PCS_REG_LASI_STATUS, &val1);
4872 bnx2x_cl45_read(bp, params->port, 4395 bnx2x_cl45_read(bp, phy,
4873 ext_phy_type,
4874 ext_phy_addr,
4875 MDIO_PCS_DEVAD, 4396 MDIO_PCS_DEVAD,
4876 MDIO_PCS_REG_LASI_STATUS, &val2); 4397 MDIO_PCS_REG_LASI_STATUS, &val2);
4877 DP(NETIF_MSG_LINK, 4398 DP(NETIF_MSG_LINK,
@@ -4881,101 +4402,77 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4881 /* In 8073, port1 is directed through emac0 and 4402 /* In 8073, port1 is directed through emac0 and
4882 * port0 is directed through emac1 4403 * port0 is directed through emac1
4883 */ 4404 */
4884 bnx2x_cl45_read(bp, params->port, 4405 bnx2x_cl45_read(bp, phy,
4885 ext_phy_type,
4886 ext_phy_addr,
4887 MDIO_PMA_DEVAD, 4406 MDIO_PMA_DEVAD,
4888 MDIO_PMA_REG_LASI_STATUS, &val1); 4407 MDIO_PMA_REG_LASI_STATUS, &val1);
4889 4408
4890 DP(NETIF_MSG_LINK, 4409 DP(NETIF_MSG_LINK,
4891 "8703 LASI status 0x%x\n", 4410 "8703 LASI status 0x%x\n",
4892 val1); 4411 val1);
4893 }
4894 4412
4413 }
4895 /* clear the interrupt LASI status register */ 4414 /* clear the interrupt LASI status register */
4896 bnx2x_cl45_read(bp, params->port, 4415 bnx2x_cl45_read(bp, phy,
4897 ext_phy_type,
4898 ext_phy_addr,
4899 MDIO_PCS_DEVAD, 4416 MDIO_PCS_DEVAD,
4900 MDIO_PCS_REG_STATUS, &val2); 4417 MDIO_PCS_REG_STATUS, &val2);
4901 bnx2x_cl45_read(bp, params->port, 4418 bnx2x_cl45_read(bp, phy,
4902 ext_phy_type,
4903 ext_phy_addr,
4904 MDIO_PCS_DEVAD, 4419 MDIO_PCS_DEVAD,
4905 MDIO_PCS_REG_STATUS, &val1); 4420 MDIO_PCS_REG_STATUS, &val1);
4906 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", 4421 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4907 val2, val1); 4422 val2, val1);
4908 /* Clear MSG-OUT */ 4423 /* Clear MSG-OUT */
4909 bnx2x_cl45_read(bp, params->port, 4424 bnx2x_cl45_read(bp, phy,
4910 ext_phy_type,
4911 ext_phy_addr,
4912 MDIO_PMA_DEVAD, 4425 MDIO_PMA_DEVAD,
4913 MDIO_PMA_REG_M8051_MSGOUT_REG, 4426 MDIO_PMA_REG_M8051_MSGOUT_REG,
4914 &val1); 4427 &val1);
4915 4428
4916 /* Check the LASI */ 4429 /* Check the LASI */
4917 bnx2x_cl45_read(bp, params->port, 4430 bnx2x_cl45_read(bp, phy,
4918 ext_phy_type,
4919 ext_phy_addr,
4920 MDIO_PMA_DEVAD, 4431 MDIO_PMA_DEVAD,
4921 MDIO_PMA_REG_RX_ALARM, &val2); 4432 MDIO_PMA_REG_RX_ALARM, &val2);
4922 4433
4923 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 4434 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4924 4435
4925 /* Check the link status */ 4436 /* Check the link status */
4926 bnx2x_cl45_read(bp, params->port, 4437 bnx2x_cl45_read(bp, phy,
4927 ext_phy_type,
4928 ext_phy_addr,
4929 MDIO_PCS_DEVAD, 4438 MDIO_PCS_DEVAD,
4930 MDIO_PCS_REG_STATUS, &val2); 4439 MDIO_PCS_REG_STATUS, &val2);
4931 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 4440 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4932 4441
4933 bnx2x_cl45_read(bp, params->port, 4442 bnx2x_cl45_read(bp, phy,
4934 ext_phy_type,
4935 ext_phy_addr,
4936 MDIO_PMA_DEVAD, 4443 MDIO_PMA_DEVAD,
4937 MDIO_PMA_REG_STATUS, &val2); 4444 MDIO_PMA_REG_STATUS, &val2);
4938 bnx2x_cl45_read(bp, params->port, 4445 bnx2x_cl45_read(bp, phy,
4939 ext_phy_type,
4940 ext_phy_addr,
4941 MDIO_PMA_DEVAD, 4446 MDIO_PMA_DEVAD,
4942 MDIO_PMA_REG_STATUS, &val1); 4447 MDIO_PMA_REG_STATUS, &val1);
4943 ext_phy_link_up = ((val1 & 4) == 4); 4448 ext_phy_link_up = ((val1 & 4) == 4);
4944 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 4449 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4945 if (ext_phy_type == 4450 if (phy->type ==
4946 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 4451 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4947 4452
4948 if (ext_phy_link_up && 4453 if (ext_phy_link_up &&
4949 ((params->req_line_speed != 4454 ((params->req_line_speed !=
4950 SPEED_10000))) { 4455 SPEED_10000))) {
4951 if (bnx2x_bcm8073_xaui_wa(params) 4456 if (bnx2x_8073_xaui_wa(bp, phy)
4952 != 0) { 4457 != 0) {
4953 ext_phy_link_up = 0; 4458 ext_phy_link_up = 0;
4954 break; 4459 break;
4955 } 4460 }
4956 } 4461 }
4957 bnx2x_cl45_read(bp, params->port, 4462 bnx2x_cl45_read(bp, phy,
4958 ext_phy_type,
4959 ext_phy_addr,
4960 MDIO_AN_DEVAD, 4463 MDIO_AN_DEVAD,
4961 MDIO_AN_REG_LINK_STATUS, 4464 MDIO_AN_REG_LINK_STATUS,
4962 &an1000_status); 4465 &an1000_status);
4963 bnx2x_cl45_read(bp, params->port, 4466 bnx2x_cl45_read(bp, phy,
4964 ext_phy_type,
4965 ext_phy_addr,
4966 MDIO_AN_DEVAD, 4467 MDIO_AN_DEVAD,
4967 MDIO_AN_REG_LINK_STATUS, 4468 MDIO_AN_REG_LINK_STATUS,
4968 &an1000_status); 4469 &an1000_status);
4969 4470
4970 /* Check the link status on 1.1.2 */ 4471 /* Check the link status on 1.1.2 */
4971 bnx2x_cl45_read(bp, params->port, 4472 bnx2x_cl45_read(bp, phy,
4972 ext_phy_type,
4973 ext_phy_addr,
4974 MDIO_PMA_DEVAD, 4473 MDIO_PMA_DEVAD,
4975 MDIO_PMA_REG_STATUS, &val2); 4474 MDIO_PMA_REG_STATUS, &val2);
4976 bnx2x_cl45_read(bp, params->port, 4475 bnx2x_cl45_read(bp, phy,
4977 ext_phy_type,
4978 ext_phy_addr,
4979 MDIO_PMA_DEVAD, 4476 MDIO_PMA_DEVAD,
4980 MDIO_PMA_REG_STATUS, &val1); 4477 MDIO_PMA_REG_STATUS, &val1);
4981 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 4478 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
@@ -4985,7 +4482,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4985 ext_phy_link_up = (((val1 & 4) == 4) || 4482 ext_phy_link_up = (((val1 & 4) == 4) ||
4986 (an1000_status & (1<<1))); 4483 (an1000_status & (1<<1)));
4987 if (ext_phy_link_up && 4484 if (ext_phy_link_up &&
4988 bnx2x_8073_is_snr_needed(params)) { 4485 bnx2x_8073_is_snr_needed(bp, phy)) {
4989 /* The SNR will improve about 2dbby 4486 /* The SNR will improve about 2dbby
4990 changing the BW and FEE main tap.*/ 4487 changing the BW and FEE main tap.*/
4991 4488
@@ -4993,23 +4490,19 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4993 tap is set before restart AN */ 4490 tap is set before restart AN */
4994 /* Change PLL Bandwidth in EDC 4491 /* Change PLL Bandwidth in EDC
4995 register */ 4492 register */
4996 bnx2x_cl45_write(bp, port, ext_phy_type, 4493 bnx2x_cl45_write(bp, phy,
4997 ext_phy_addr,
4998 MDIO_PMA_DEVAD, 4494 MDIO_PMA_DEVAD,
4999 MDIO_PMA_REG_PLL_BANDWIDTH, 4495 MDIO_PMA_REG_PLL_BANDWIDTH,
5000 0x26BC); 4496 0x26BC);
5001 4497
5002 /* Change CDR Bandwidth in EDC 4498 /* Change CDR Bandwidth in EDC
5003 register */ 4499 register */
5004 bnx2x_cl45_write(bp, port, ext_phy_type, 4500 bnx2x_cl45_write(bp, phy,
5005 ext_phy_addr,
5006 MDIO_PMA_DEVAD, 4501 MDIO_PMA_DEVAD,
5007 MDIO_PMA_REG_CDR_BANDWIDTH, 4502 MDIO_PMA_REG_CDR_BANDWIDTH,
5008 0x0333); 4503 0x0333);
5009 } 4504 }
5010 bnx2x_cl45_read(bp, params->port, 4505 bnx2x_cl45_read(bp, phy,
5011 ext_phy_type,
5012 ext_phy_addr,
5013 MDIO_PMA_DEVAD, 4506 MDIO_PMA_DEVAD,
5014 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 4507 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
5015 &link_status); 4508 &link_status);
@@ -5045,15 +4538,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5045 } 4538 }
5046 } else { 4539 } else {
5047 /* See if 1G link is up for the 8072 */ 4540 /* See if 1G link is up for the 8072 */
5048 bnx2x_cl45_read(bp, params->port, 4541 bnx2x_cl45_read(bp, phy,
5049 ext_phy_type,
5050 ext_phy_addr,
5051 MDIO_AN_DEVAD, 4542 MDIO_AN_DEVAD,
5052 MDIO_AN_REG_LINK_STATUS, 4543 MDIO_AN_REG_LINK_STATUS,
5053 &an1000_status); 4544 &an1000_status);
5054 bnx2x_cl45_read(bp, params->port, 4545 bnx2x_cl45_read(bp, phy,
5055 ext_phy_type,
5056 ext_phy_addr,
5057 MDIO_AN_DEVAD, 4546 MDIO_AN_DEVAD,
5058 MDIO_AN_REG_LINK_STATUS, 4547 MDIO_AN_REG_LINK_STATUS,
5059 &an1000_status); 4548 &an1000_status);
@@ -5072,27 +4561,22 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5072 } 4561 }
5073 } 4562 }
5074 4563
5075
5076 break; 4564 break;
5077 } 4565 }
5078 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 4566 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5079 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4567 bnx2x_cl45_read(bp, phy,
5080 ext_phy_addr,
5081 MDIO_PMA_DEVAD, 4568 MDIO_PMA_DEVAD,
5082 MDIO_PMA_REG_LASI_STATUS, &val2); 4569 MDIO_PMA_REG_LASI_STATUS, &val2);
5083 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4570 bnx2x_cl45_read(bp, phy,
5084 ext_phy_addr,
5085 MDIO_PMA_DEVAD, 4571 MDIO_PMA_DEVAD,
5086 MDIO_PMA_REG_LASI_STATUS, &val1); 4572 MDIO_PMA_REG_LASI_STATUS, &val1);
5087 DP(NETIF_MSG_LINK, 4573 DP(NETIF_MSG_LINK,
5088 "10G-base-T LASI status 0x%x->0x%x\n", 4574 "10G-base-T LASI status 0x%x->0x%x\n",
5089 val2, val1); 4575 val2, val1);
5090 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4576 bnx2x_cl45_read(bp, phy,
5091 ext_phy_addr,
5092 MDIO_PMA_DEVAD, 4577 MDIO_PMA_DEVAD,
5093 MDIO_PMA_REG_STATUS, &val2); 4578 MDIO_PMA_REG_STATUS, &val2);
5094 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4579 bnx2x_cl45_read(bp, phy,
5095 ext_phy_addr,
5096 MDIO_PMA_DEVAD, 4580 MDIO_PMA_DEVAD,
5097 MDIO_PMA_REG_STATUS, &val1); 4581 MDIO_PMA_REG_STATUS, &val1);
5098 DP(NETIF_MSG_LINK, 4582 DP(NETIF_MSG_LINK,
@@ -5103,9 +4587,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5103 * print the AN outcome of the SFX7101 PHY 4587 * print the AN outcome of the SFX7101 PHY
5104 */ 4588 */
5105 if (ext_phy_link_up) { 4589 if (ext_phy_link_up) {
5106 bnx2x_cl45_read(bp, params->port, 4590 bnx2x_cl45_read(bp, phy,
5107 ext_phy_type,
5108 ext_phy_addr,
5109 MDIO_AN_DEVAD, 4591 MDIO_AN_DEVAD,
5110 MDIO_AN_REG_MASTER_STATUS, 4592 MDIO_AN_REG_MASTER_STATUS,
5111 &val2); 4593 &val2);
@@ -5120,13 +4602,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5120 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 4602 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5121 /* Check 10G-BaseT link status */ 4603 /* Check 10G-BaseT link status */
5122 /* Check PMD signal ok */ 4604 /* Check PMD signal ok */
5123 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4605 bnx2x_cl45_read(bp, phy,
5124 ext_phy_addr,
5125 MDIO_AN_DEVAD, 4606 MDIO_AN_DEVAD,
5126 0xFFFA, 4607 0xFFFA,
5127 &val1); 4608 &val1);
5128 bnx2x_cl45_read(bp, params->port, ext_phy_type, 4609 bnx2x_cl45_read(bp, phy,
5129 ext_phy_addr,
5130 MDIO_PMA_DEVAD, 4610 MDIO_PMA_DEVAD,
5131 MDIO_PMA_REG_8481_PMD_SIGNAL, 4611 MDIO_PMA_REG_8481_PMD_SIGNAL,
5132 &val2); 4612 &val2);
@@ -5141,17 +4621,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5141 4621
5142 /* Enable expansion register 0x42 4622 /* Enable expansion register 0x42
5143 (Operation mode status) */ 4623 (Operation mode status) */
5144 bnx2x_cl45_write(bp, params->port, 4624 bnx2x_cl45_write(bp, phy,
5145 ext_phy_type,
5146 ext_phy_addr,
5147 MDIO_AN_DEVAD, 4625 MDIO_AN_DEVAD,
5148 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 4626 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5149 0xf42); 4627 0xf42);
5150 4628
5151 /* Get legacy speed operation status */ 4629 /* Get legacy speed operation status */
5152 bnx2x_cl45_read(bp, params->port, 4630 bnx2x_cl45_read(bp, phy,
5153 ext_phy_type,
5154 ext_phy_addr,
5155 MDIO_AN_DEVAD, 4631 MDIO_AN_DEVAD,
5156 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 4632 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5157 &legacy_status); 4633 &legacy_status);
@@ -5187,48 +4663,27 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
5187 } 4663 }
5188 break; 4664 break;
5189 default: 4665 default:
5190 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", 4666 DP(NETIF_MSG_LINK,
5191 params->ext_phy_config); 4667 "BAD SerDes ext_phy_config 0x%x\n",
4668 phy->type);
5192 ext_phy_link_up = 0; 4669 ext_phy_link_up = 0;
5193 break; 4670 break;
5194 } 4671 }
4672 }
4673
5195 /* Set SGMII mode for external phy */ 4674 /* Set SGMII mode for external phy */
5196 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 4675 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5197 if (vars->line_speed < SPEED_1000) 4676 if (vars->line_speed < SPEED_1000)
5198 vars->phy_flags |= PHY_SGMII_FLAG; 4677 vars->phy_flags |= PHY_SGMII_FLAG;
5199 else 4678 else
5200 vars->phy_flags &= ~PHY_SGMII_FLAG; 4679 vars->phy_flags &= ~PHY_SGMII_FLAG;
5201 } 4680 }
5202 4681
5203 } else { /* SerDes */
5204 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5205 switch (ext_phy_type) {
5206 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5207 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5208 ext_phy_link_up = 1;
5209 break;
5210
5211 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5212 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5213 ext_phy_link_up = 1;
5214 break;
5215
5216 default:
5217 DP(NETIF_MSG_LINK,
5218 "BAD SerDes ext_phy_config 0x%x\n",
5219 params->ext_phy_config);
5220 ext_phy_link_up = 0;
5221 break;
5222 }
5223 }
5224
5225 return ext_phy_link_up; 4682 return ext_phy_link_up;
5226} 4683}
5227
5228static void bnx2x_link_int_enable(struct link_params *params) 4684static void bnx2x_link_int_enable(struct link_params *params)
5229{ 4685{
5230 u8 port = params->port; 4686 u8 port = params->port;
5231 u32 ext_phy_type;
5232 u32 mask; 4687 u32 mask;
5233 struct bnx2x *bp = params->bp; 4688 struct bnx2x *bp = params->bp;
5234 4689
@@ -5239,11 +4694,9 @@ static void bnx2x_link_int_enable(struct link_params *params)
5239 mask = (NIG_MASK_XGXS0_LINK10G | 4694 mask = (NIG_MASK_XGXS0_LINK10G |
5240 NIG_MASK_XGXS0_LINK_STATUS); 4695 NIG_MASK_XGXS0_LINK_STATUS);
5241 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 4696 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5242 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 4697 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5243 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4698 params->phy[INT_PHY].type !=
5244 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 4699 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5245 (ext_phy_type !=
5246 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5247 mask |= NIG_MASK_MI_INT; 4700 mask |= NIG_MASK_MI_INT;
5248 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 4701 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5249 } 4702 }
@@ -5251,11 +4704,9 @@ static void bnx2x_link_int_enable(struct link_params *params)
5251 } else { /* SerDes */ 4704 } else { /* SerDes */
5252 mask = NIG_MASK_SERDES0_LINK_STATUS; 4705 mask = NIG_MASK_SERDES0_LINK_STATUS;
5253 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 4706 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5254 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); 4707 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5255 if ((ext_phy_type != 4708 params->phy[INT_PHY].type !=
5256 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && 4709 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5257 (ext_phy_type !=
5258 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5259 mask |= NIG_MASK_MI_INT; 4710 mask |= NIG_MASK_MI_INT;
5260 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 4711 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5261 } 4712 }
@@ -5311,6 +4762,7 @@ static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5311 (latch_status & 0xfffe) | (latch_status & 1)); 4762 (latch_status & 0xfffe) | (latch_status & 1));
5312 } 4763 }
5313} 4764}
4765
5314/* 4766/*
5315 * link management 4767 * link management
5316 */ 4768 */
@@ -5327,9 +4779,9 @@ static void bnx2x_link_int_ack(struct link_params *params,
5327 (NIG_STATUS_XGXS0_LINK10G | 4779 (NIG_STATUS_XGXS0_LINK10G |
5328 NIG_STATUS_XGXS0_LINK_STATUS | 4780 NIG_STATUS_XGXS0_LINK_STATUS |
5329 NIG_STATUS_SERDES0_LINK_STATUS)); 4781 NIG_STATUS_SERDES0_LINK_STATUS));
5330 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) 4782 if ((params->phy[EXT_PHY1].type
5331 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) || 4783 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5332 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) 4784 (params->phy[EXT_PHY1].type
5333 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) { 4785 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
5334 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); 4786 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5335 } 4787 }
@@ -5421,7 +4873,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5421 4873
5422 status = 0; 4874 status = 0;
5423 /* reset the returned value to zero */ 4875 /* reset the returned value to zero */
5424 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 4876 ext_phy_type = params->phy[EXT_PHY1].type;
5425 switch (ext_phy_type) { 4877 switch (ext_phy_type) {
5426 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 4878 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5427 4879
@@ -5465,8 +4917,8 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5465 return status; 4917 return status;
5466} 4918}
5467 4919
5468static void bnx2x_set_xgxs_loopback(struct link_params *params, 4920static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5469 struct link_vars *vars, 4921 struct link_params *params,
5470 u8 is_10g) 4922 u8 is_10g)
5471{ 4923{
5472 u8 port = params->port; 4924 u8 port = params->port;
@@ -5483,59 +4935,49 @@ static void bnx2x_set_xgxs_loopback(struct link_params *params,
5483 4935
5484 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5); 4936 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5485 4937
5486 bnx2x_cl45_write(bp, port, 0, 4938 bnx2x_cl45_write(bp, phy,
5487 params->phy_addr,
5488 5, 4939 5,
5489 (MDIO_REG_BANK_AER_BLOCK + 4940 (MDIO_REG_BANK_AER_BLOCK +
5490 (MDIO_AER_BLOCK_AER_REG & 0xf)), 4941 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5491 0x2800); 4942 0x2800);
5492 4943
5493 bnx2x_cl45_write(bp, port, 0, 4944 bnx2x_cl45_write(bp, phy,
5494 params->phy_addr,
5495 5, 4945 5,
5496 (MDIO_REG_BANK_CL73_IEEEB0 + 4946 (MDIO_REG_BANK_CL73_IEEEB0 +
5497 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 4947 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5498 0x6041); 4948 0x6041);
5499 msleep(200); 4949 msleep(200);
5500 /* set aer mmd back */ 4950 /* set aer mmd back */
5501 bnx2x_set_aer_mmd(params, vars); 4951 bnx2x_set_aer_mmd(params, phy);
5502 4952
5503 /* and md_devad */ 4953 /* and md_devad */
5504 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 4954 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5505 md_devad); 4955 md_devad);
5506 4956
5507 } else { 4957 } else {
5508 u16 mii_control; 4958 u16 mii_ctrl;
5509
5510 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 4959 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5511 4960 bnx2x_cl45_read(bp, phy, 5,
5512 CL45_RD_OVER_CL22(bp, port, 4961 (MDIO_REG_BANK_COMBO_IEEE0 +
5513 params->phy_addr, 4962 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5514 MDIO_REG_BANK_COMBO_IEEE0, 4963 &mii_ctrl);
5515 MDIO_COMBO_IEEE0_MII_CONTROL, 4964 bnx2x_cl45_write(bp, phy, 5,
5516 &mii_control); 4965 (MDIO_REG_BANK_COMBO_IEEE0 +
5517 4966 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5518 CL45_WR_OVER_CL22(bp, port, 4967 mii_ctrl |
5519 params->phy_addr, 4968 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5520 MDIO_REG_BANK_COMBO_IEEE0,
5521 MDIO_COMBO_IEEE0_MII_CONTROL,
5522 (mii_control |
5523 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5524 } 4969 }
5525} 4970}
5526 4971
5527 4972static void bnx2x_ext_phy_loopback(struct bnx2x_phy *phy,
5528static void bnx2x_ext_phy_loopback(struct link_params *params) 4973 struct link_params *params)
5529{ 4974{
5530 struct bnx2x *bp = params->bp; 4975 struct bnx2x *bp = params->bp;
5531 u8 ext_phy_addr;
5532 u32 ext_phy_type;
5533 4976
5534 if (params->switch_cfg == SWITCH_CFG_10G) { 4977 if (params->switch_cfg == SWITCH_CFG_10G) {
5535 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 4978
5536 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
5537 /* CL37 Autoneg Enabled */ 4979 /* CL37 Autoneg Enabled */
5538 switch (ext_phy_type) { 4980 switch (phy->type) {
5539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 4981 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN: 4982 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5541 DP(NETIF_MSG_LINK, 4983 DP(NETIF_MSG_LINK,
@@ -5549,16 +4991,14 @@ static void bnx2x_ext_phy_loopback(struct link_params *params)
5549 break; 4991 break;
5550 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 4992 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5551 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 4993 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5552 bnx2x_cl45_write(bp, params->port, ext_phy_type, 4994 bnx2x_cl45_write(bp, phy,
5553 ext_phy_addr,
5554 MDIO_PMA_DEVAD, 4995 MDIO_PMA_DEVAD,
5555 MDIO_PMA_REG_CTRL, 4996 MDIO_PMA_REG_CTRL,
5556 0x0001); 4997 0x0001);
5557 break; 4998 break;
5558 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 4999 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5559 /* SFX7101_XGXS_TEST1 */ 5000 /* SFX7101_XGXS_TEST1 */
5560 bnx2x_cl45_write(bp, params->port, ext_phy_type, 5001 bnx2x_cl45_write(bp, phy,
5561 ext_phy_addr,
5562 MDIO_XS_DEVAD, 5002 MDIO_XS_DEVAD,
5563 MDIO_XS_SFX7101_XGXS_TEST1, 5003 MDIO_XS_SFX7101_XGXS_TEST1,
5564 0x100); 5004 0x100);
@@ -5569,21 +5009,13 @@ static void bnx2x_ext_phy_loopback(struct link_params *params)
5569 5009
5570 break; 5010 break;
5571 } /* switch external PHY type */ 5011 } /* switch external PHY type */
5572 } else {
5573 /* serdes */
5574 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5575 ext_phy_addr = (params->ext_phy_config &
5576 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5577 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5578 } 5012 }
5579} 5013}
5580
5581
5582/* 5014/*
5583 *------------------------------------------------------------------------ 5015 *------------------------------------------------------------------------
5584 * bnx2x_override_led_value - 5016 * bnx2x_override_led_value -
5585 * 5017 *
5586 * Override the led value of the requsted led 5018 * Override the led value of the requested led
5587 * 5019 *
5588 *------------------------------------------------------------------------ 5020 *------------------------------------------------------------------------
5589 */ 5021 */
@@ -5702,7 +5134,6 @@ u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
5702 u8 rc = 0; 5134 u8 rc = 0;
5703 u32 tmp; 5135 u32 tmp;
5704 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 5136 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5705 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5706 struct bnx2x *bp = params->bp; 5137 struct bnx2x *bp = params->bp;
5707 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 5138 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5708 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 5139 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
@@ -5718,7 +5149,7 @@ u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
5718 break; 5149 break;
5719 5150
5720 case LED_MODE_OPER: 5151 case LED_MODE_OPER:
5721 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5152 if (SINGLE_MEDIA_DIRECT(params)) {
5722 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 5153 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5723 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 5154 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5724 } else { 5155 } else {
@@ -5768,14 +5199,13 @@ u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5768 struct bnx2x *bp = params->bp; 5199 struct bnx2x *bp = params->bp;
5769 u16 gp_status = 0; 5200 u16 gp_status = 0;
5770 5201
5771 CL45_RD_OVER_CL22(bp, params->port, 5202 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
5772 params->phy_addr,
5773 MDIO_REG_BANK_GP_STATUS, 5203 MDIO_REG_BANK_GP_STATUS,
5774 MDIO_GP_STATUS_TOP_AN_STATUS1, 5204 MDIO_GP_STATUS_TOP_AN_STATUS1,
5775 &gp_status); 5205 &gp_status);
5776 /* link is up only if both local phy and external phy are up */ 5206 /* link is up only if both local phy and external phy are up */
5777 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) && 5207 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
5778 bnx2x_ext_phy_is_link_up(params, vars, 1)) 5208 bnx2x_ext_phy_is_link_up(&params->phy[EXT_PHY1], params, vars, 1))
5779 return 0; 5209 return 0;
5780 5210
5781 return -ESRCH; 5211 return -ESRCH;
@@ -5788,27 +5218,29 @@ static u8 bnx2x_link_initialize(struct link_params *params,
5788 u8 port = params->port; 5218 u8 port = params->port;
5789 u8 rc = 0; 5219 u8 rc = 0;
5790 u8 non_ext_phy; 5220 u8 non_ext_phy;
5791 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 5221 struct bnx2x_phy *ext_phy = &params->phy[EXT_PHY1];
5792 5222 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
5793 /* Activate the external PHY */ 5223 /* Activate the external PHY */
5794 bnx2x_ext_phy_reset(params, vars); 5224 bnx2x_ext_phy_reset(ext_phy, params, vars);
5795 5225
5796 bnx2x_set_aer_mmd(params, vars); 5226 bnx2x_set_aer_mmd(params, int_phy);
5797 5227
5798 if (vars->phy_flags & PHY_XGXS_FLAG) 5228 if (vars->phy_flags & PHY_XGXS_FLAG)
5799 bnx2x_set_master_ln(params); 5229 bnx2x_set_master_ln(params, int_phy);
5800 5230
5801 rc = bnx2x_reset_unicore(params); 5231 rc = bnx2x_reset_unicore(params, int_phy,
5232 int_phy->type ==
5233 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT);
5802 /* reset the SerDes and wait for reset bit return low */ 5234 /* reset the SerDes and wait for reset bit return low */
5803 if (rc != 0) 5235 if (rc != 0)
5804 return rc; 5236 return rc;
5805 5237
5806 bnx2x_set_aer_mmd(params, vars); 5238 bnx2x_set_aer_mmd(params, int_phy);
5807 5239
5808 /* setting the masterLn_def again after the reset */ 5240 /* setting the masterLn_def again after the reset */
5809 if (vars->phy_flags & PHY_XGXS_FLAG) { 5241 if (vars->phy_flags & PHY_XGXS_FLAG) {
5810 bnx2x_set_master_ln(params); 5242 bnx2x_set_master_ln(params, int_phy);
5811 bnx2x_set_swap_lanes(params); 5243 bnx2x_set_swap_lanes(params, int_phy);
5812 } 5244 }
5813 5245
5814 if (vars->phy_flags & PHY_XGXS_FLAG) { 5246 if (vars->phy_flags & PHY_XGXS_FLAG) {
@@ -5832,20 +5264,21 @@ static u8 bnx2x_link_initialize(struct link_params *params,
5832 req_line_speed*/ 5264 req_line_speed*/
5833 vars->line_speed = params->req_line_speed; 5265 vars->line_speed = params->req_line_speed;
5834 5266
5835 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc); 5267 bnx2x_calc_ieee_aneg_adv(int_phy, params, &vars->ieee_fc);
5836 5268
5837 /* init ext phy and enable link state int */ 5269 /* init ext phy and enable link state int */
5838 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || 5270 non_ext_phy = ((ext_phy->type ==
5271 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
5839 (params->loopback_mode == LOOPBACK_XGXS_10)); 5272 (params->loopback_mode == LOOPBACK_XGXS_10));
5840 5273
5841 if (non_ext_phy || 5274 if (non_ext_phy ||
5842 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 5275 (ext_phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5843 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) || 5276 (ext_phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
5844 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) || 5277 (ext_phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5845 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 5278 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5846 if (params->req_line_speed == SPEED_AUTO_NEG) 5279 if (vars->line_speed == SPEED_AUTO_NEG)
5847 bnx2x_set_parallel_detection(params, vars->phy_flags); 5280 bnx2x_set_parallel_detection(int_phy, params);
5848 bnx2x_init_internal_phy(params, vars, non_ext_phy); 5281 bnx2x_init_internal_phy(int_phy, params, vars);
5849 } 5282 }
5850 5283
5851 if (!non_ext_phy) 5284 if (!non_ext_phy)
@@ -5857,10 +5290,8 @@ static u8 bnx2x_link_initialize(struct link_params *params,
5857 NIG_STATUS_SERDES0_LINK_STATUS)); 5290 NIG_STATUS_SERDES0_LINK_STATUS));
5858 5291
5859 return rc; 5292 return rc;
5860
5861} 5293}
5862 5294
5863
5864u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 5295u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5865{ 5296{
5866 struct bnx2x *bp = params->bp; 5297 struct bnx2x *bp = params->bp;
@@ -5877,10 +5308,28 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5877 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5308 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5878 vars->mac_type = MAC_TYPE_NONE; 5309 vars->mac_type = MAC_TYPE_NONE;
5879 5310
5880 if (params->switch_cfg == SWITCH_CFG_1G) 5311 if (params->switch_cfg == SWITCH_CFG_1G) {
5312 params->phy[INT_PHY].type =
5313 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT;
5881 vars->phy_flags = PHY_SERDES_FLAG; 5314 vars->phy_flags = PHY_SERDES_FLAG;
5882 else 5315 } else {
5316 params->phy[INT_PHY].type =
5317 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT;
5883 vars->phy_flags = PHY_XGXS_FLAG; 5318 vars->phy_flags = PHY_XGXS_FLAG;
5319 }
5320 params->phy[INT_PHY].mdio_ctrl =
5321 bnx2x_get_emac_base(bp,
5322 params->phy[INT_PHY].type, params->port);
5323 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
5324 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5325 params->phy[EXT_PHY1].type =
5326 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5327 params->phy[EXT_PHY1].addr =
5328 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
5329 params->phy[EXT_PHY1].mdio_ctrl =
5330 bnx2x_get_emac_base(bp, params->phy[EXT_PHY1].type,
5331 params->port);
5332 }
5884 5333
5885 /* disable attentions */ 5334 /* disable attentions */
5886 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 5335 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
@@ -5951,6 +5400,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5951 vars->phy_flags = PHY_XGXS_FLAG; 5400 vars->phy_flags = PHY_XGXS_FLAG;
5952 5401
5953 bnx2x_phy_deassert(params, vars->phy_flags); 5402 bnx2x_phy_deassert(params, vars->phy_flags);
5403
5954 /* set bmac loopback */ 5404 /* set bmac loopback */
5955 bnx2x_bmac_enable(params, vars, 1); 5405 bnx2x_bmac_enable(params, vars, 1);
5956 5406
@@ -5989,7 +5439,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5989 NIG_REG_XGXS0_CTRL_PHY_ADDR+ 5439 NIG_REG_XGXS0_CTRL_PHY_ADDR+
5990 params->port*0x18); 5440 params->port*0x18);
5991 params->phy_addr = (u8)val; 5441 params->phy_addr = (u8)val;
5992 5442 params->phy[INT_PHY].addr = (u8)val;
5993 bnx2x_phy_deassert(params, vars->phy_flags); 5443 bnx2x_phy_deassert(params, vars->phy_flags);
5994 bnx2x_link_initialize(params, vars); 5444 bnx2x_link_initialize(params, vars);
5995 5445
@@ -5999,11 +5449,14 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5999 5449
6000 if (params->loopback_mode == LOOPBACK_XGXS_10) { 5450 if (params->loopback_mode == LOOPBACK_XGXS_10) {
6001 /* set 10G XGXS loopback */ 5451 /* set 10G XGXS loopback */
6002 bnx2x_set_xgxs_loopback(params, vars, 1); 5452 bnx2x_set_xgxs_loopback(&params->phy[INT_PHY],
5453 params, 1);
6003 } else { 5454 } else {
6004 /* set external phy loopback */ 5455 /* set external phy loopback */
6005 bnx2x_ext_phy_loopback(params); 5456 bnx2x_ext_phy_loopback(&params->phy[INT_PHY],
5457 params);
6006 } 5458 }
5459
6007 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 5460 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6008 params->port*4, 0); 5461 params->port*4, 0);
6009 5462
@@ -6041,7 +5494,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6041 return -EINVAL; 5494 return -EINVAL;
6042 } 5495 }
6043 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr); 5496 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
6044 5497 params->phy[INT_PHY].addr = params->phy_addr;
6045 bnx2x_link_initialize(params, vars); 5498 bnx2x_link_initialize(params, vars);
6046 msleep(30); 5499 msleep(30);
6047 bnx2x_link_int_enable(params); 5500 bnx2x_link_int_enable(params);
@@ -6049,13 +5502,13 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6049 return 0; 5502 return 0;
6050} 5503}
6051 5504
6052static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6053{
6054 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6055 5505
5506static void bnx2x_8726_reset_phy(struct bnx2x *bp,
5507 struct bnx2x_phy *phy)
5508{
5509 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy\n");
6056 /* Set serial boot control for external load */ 5510 /* Set serial boot control for external load */
6057 bnx2x_cl45_write(bp, port, 5511 bnx2x_cl45_write(bp, phy,
6058 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6059 MDIO_PMA_DEVAD, 5512 MDIO_PMA_DEVAD,
6060 MDIO_PMA_REG_GEN_CTRL, 0x0001); 5513 MDIO_PMA_REG_GEN_CTRL, 0x0001);
6061} 5514}
@@ -6064,9 +5517,9 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6064 u8 reset_ext_phy) 5517 u8 reset_ext_phy)
6065{ 5518{
6066 struct bnx2x *bp = params->bp; 5519 struct bnx2x *bp = params->bp;
6067 u32 ext_phy_config = params->ext_phy_config; 5520
6068 u8 port = params->port; 5521 u8 port = params->port;
6069 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 5522
6070 u32 val = REG_RD(bp, params->shmem_base + 5523 u32 val = REG_RD(bp, params->shmem_base +
6071 offsetof(struct shmem_region, dev_info. 5524 offsetof(struct shmem_region, dev_info.
6072 port_feature_config[params->port]. 5525 port_feature_config[params->port].
@@ -6101,7 +5554,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6101 /* clear link led */ 5554 /* clear link led */
6102 bnx2x_set_led(params, LED_MODE_OFF, 0); 5555 bnx2x_set_led(params, LED_MODE_OFF, 0);
6103 if (reset_ext_phy) { 5556 if (reset_ext_phy) {
6104 switch (ext_phy_type) { 5557 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5558 switch (phy->type) {
6105 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 5559 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6106 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 5560 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6107 break; 5561 break;
@@ -6110,13 +5564,9 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6110 { 5564 {
6111 5565
6112 /* Disable Transmitter */ 5566 /* Disable Transmitter */
6113 u8 ext_phy_addr =
6114 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6115 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 5567 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6116 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 5568 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6117 bnx2x_sfp_set_transmitter(bp, port, 5569 bnx2x_sfp_set_transmitter(bp, phy, 0);
6118 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6119 ext_phy_addr, 0);
6120 break; 5570 break;
6121 } 5571 }
6122 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 5572 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
@@ -6129,10 +5579,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6129 break; 5579 break;
6130 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 5580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6131 { 5581 {
6132 u8 ext_phy_addr =
6133 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6134 /* Set soft reset */ 5582 /* Set soft reset */
6135 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); 5583 bnx2x_8726_reset_phy(bp, phy);
6136 break; 5584 break;
6137 } 5585 }
6138 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 5586 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
@@ -6170,6 +5618,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6170 return 0; 5618 return 0;
6171} 5619}
6172 5620
5621
6173static u8 bnx2x_update_link_down(struct link_params *params, 5622static u8 bnx2x_update_link_down(struct link_params *params,
6174 struct link_vars *vars) 5623 struct link_vars *vars)
6175{ 5624{
@@ -6222,11 +5671,10 @@ static u8 bnx2x_update_link_up(struct link_params *params,
6222 bnx2x_emac_enable(params, vars, 0); 5671 bnx2x_emac_enable(params, vars, 0);
6223 5672
6224 /* AN complete? */ 5673 /* AN complete? */
6225 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 5674 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6226 if (!(vars->phy_flags & 5675 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6227 PHY_SGMII_FLAG)) 5676 SINGLE_MEDIA_DIRECT(params))
6228 bnx2x_set_gmii_tx_driver(params); 5677 bnx2x_set_gmii_tx_driver(params);
6229 }
6230 } 5678 }
6231 5679
6232 /* PBF - link up */ 5680 /* PBF - link up */
@@ -6261,7 +5709,7 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6261 u16 gp_status; 5709 u16 gp_status;
6262 u8 link_10g; 5710 u8 link_10g;
6263 u8 ext_phy_link_up, rc = 0; 5711 u8 ext_phy_link_up, rc = 0;
6264 u32 ext_phy_type; 5712 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6265 u8 is_mi_int = 0; 5713 u8 is_mi_int = 0;
6266 5714
6267 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 5715 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
@@ -6283,13 +5731,13 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6283 /* disable emac */ 5731 /* disable emac */
6284 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 5732 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6285 5733
6286 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
6287
6288 /* Check external link change only for non-direct */ 5734 /* Check external link change only for non-direct */
6289 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int); 5735 ext_phy_link_up = bnx2x_ext_phy_is_link_up(&params->phy[EXT_PHY1],
5736 params, vars,
5737 is_mi_int);
6290 5738
6291 /* Read gp_status */ 5739 /* Read gp_status */
6292 CL45_RD_OVER_CL22(bp, port, params->phy_addr, 5740 CL45_RD_OVER_CL22(bp, int_phy,
6293 MDIO_REG_BANK_GP_STATUS, 5741 MDIO_REG_BANK_GP_STATUS,
6294 MDIO_GP_STATUS_TOP_AN_STATUS1, 5742 MDIO_GP_STATUS_TOP_AN_STATUS1,
6295 &gp_status); 5743 &gp_status);
@@ -6316,12 +5764,12 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6316 the xgxs link would probably become up again without the need to 5764 the xgxs link would probably become up again without the need to
6317 initialize it*/ 5765 initialize it*/
6318 5766
6319 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && 5767 if ((int_phy->type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6320 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) && 5768 (int_phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6321 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) && 5769 (int_phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
6322 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) && 5770 (int_phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6323 (ext_phy_link_up && !vars->phy_link_up)) 5771 (int_phy->type && !vars->phy_link_up))
6324 bnx2x_init_internal_phy(params, vars, 0); 5772 bnx2x_init_internal_phy(int_phy, params, vars);
6325 5773
6326 /* link is up only if both local phy and external phy are up */ 5774 /* link is up only if both local phy and external phy are up */
6327 vars->link_up = (ext_phy_link_up && vars->phy_link_up); 5775 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
@@ -6334,19 +5782,65 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6334 return rc; 5782 return rc;
6335} 5783}
6336 5784
5785static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
5786 u8 phy_index, u8 port)
5787{
5788 u32 ext_phy_config = 0;
5789 switch (phy_index) {
5790 case EXT_PHY1:
5791 ext_phy_config = REG_RD(bp, shmem_base +
5792 offsetof(struct shmem_region,
5793 dev_info.port_hw_config[port].external_phy_config));
5794 break;
5795 default:
5796 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
5797 return -EINVAL;
5798 }
5799
5800 return ext_phy_config;
5801}
5802
5803static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
5804 u8 phy_index,
5805 u32 shmem_base,
5806 u8 port,
5807 struct bnx2x_phy *phy)
5808{
5809 u32 ext_phy_config;
5810
5811 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
5812 phy_index, port);
5813 phy->type = XGXS_EXT_PHY_TYPE(ext_phy_config);
5814 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
5815 phy->mdio_ctrl = bnx2x_get_emac_base(bp, phy->type, port);
5816 return 0;
5817}
5818
5819static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
5820 u8 port, struct bnx2x_phy *phy)
5821{
5822 u8 status = 0;
5823 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base,
5824 port, phy);
5825 return status;
5826}
5827
6337static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base) 5828static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6338{ 5829{
6339 u8 ext_phy_addr[PORT_MAX]; 5830 struct bnx2x_phy phy[PORT_MAX];
5831 struct bnx2x_phy *phy_blk[PORT_MAX];
6340 u16 val; 5832 u16 val;
6341 s8 port; 5833 s8 port;
6342 5834
6343 /* PART1 - Reset both phys */ 5835 /* PART1 - Reset both phys */
6344 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 5836 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6345 /* Extract the ext phy address for the port */ 5837 /* Extract the ext phy address for the port */
6346 u32 ext_phy_config = REG_RD(bp, shmem_base + 5838 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6347 offsetof(struct shmem_region, 5839 port, &phy[port]) !=
6348 dev_info.port_hw_config[port].external_phy_config)); 5840 0) {
6349 5841 DP(NETIF_MSG_LINK, "populate_phy failed\n");
5842 return -EINVAL;
5843 }
6350 /* disable attentions */ 5844 /* disable attentions */
6351 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 5845 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6352 (NIG_MASK_XGXS0_LINK_STATUS | 5846 (NIG_MASK_XGXS0_LINK_STATUS |
@@ -6354,17 +5848,13 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6354 NIG_MASK_SERDES0_LINK_STATUS | 5848 NIG_MASK_SERDES0_LINK_STATUS |
6355 NIG_MASK_MI_INT)); 5849 NIG_MASK_MI_INT));
6356 5850
6357 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
6358
6359 /* Need to take the phy out of low power mode in order 5851 /* Need to take the phy out of low power mode in order
6360 to write to access its registers */ 5852 to write to access its registers */
6361 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 5853 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6362 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 5854 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6363 5855
6364 /* Reset the phy */ 5856 /* Reset the phy */
6365 bnx2x_cl45_write(bp, port, 5857 bnx2x_cl45_write(bp, &phy[port],
6366 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6367 ext_phy_addr[port],
6368 MDIO_PMA_DEVAD, 5858 MDIO_PMA_DEVAD,
6369 MDIO_PMA_REG_CTRL, 5859 MDIO_PMA_REG_CTRL,
6370 1<<15); 5860 1<<15);
@@ -6373,15 +5863,22 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6373 /* Add delay of 150ms after reset */ 5863 /* Add delay of 150ms after reset */
6374 msleep(150); 5864 msleep(150);
6375 5865
5866 if (phy[PORT_0].addr & 0x1) {
5867 phy_blk[PORT_0] = &(phy[PORT_1]);
5868 phy_blk[PORT_1] = &(phy[PORT_0]);
5869 } else {
5870 phy_blk[PORT_0] = &(phy[PORT_0]);
5871 phy_blk[PORT_1] = &(phy[PORT_1]);
5872 }
5873
6376 /* PART2 - Download firmware to both phys */ 5874 /* PART2 - Download firmware to both phys */
6377 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 5875 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6378 u16 fw_ver1; 5876 u16 fw_ver1;
6379 5877
6380 bnx2x_bcm8073_external_rom_boot(bp, port, 5878 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
6381 ext_phy_addr[port], shmem_base); 5879 port, shmem_base);
6382 5880
6383 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 5881 bnx2x_cl45_read(bp, phy_blk[port],
6384 ext_phy_addr[port],
6385 MDIO_PMA_DEVAD, 5882 MDIO_PMA_DEVAD,
6386 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 5883 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6387 if (fw_ver1 == 0 || fw_ver1 == 0x4321) { 5884 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
@@ -6393,16 +5890,12 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6393 } 5890 }
6394 5891
6395 /* Only set bit 10 = 1 (Tx power down) */ 5892 /* Only set bit 10 = 1 (Tx power down) */
6396 bnx2x_cl45_read(bp, port, 5893 bnx2x_cl45_read(bp, phy_blk[port],
6397 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6398 ext_phy_addr[port],
6399 MDIO_PMA_DEVAD, 5894 MDIO_PMA_DEVAD,
6400 MDIO_PMA_REG_TX_POWER_DOWN, &val); 5895 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6401 5896
6402 /* Phase1 of TX_POWER_DOWN reset */ 5897 /* Phase1 of TX_POWER_DOWN reset */
6403 bnx2x_cl45_write(bp, port, 5898 bnx2x_cl45_write(bp, phy_blk[port],
6404 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6405 ext_phy_addr[port],
6406 MDIO_PMA_DEVAD, 5899 MDIO_PMA_DEVAD,
6407 MDIO_PMA_REG_TX_POWER_DOWN, 5900 MDIO_PMA_REG_TX_POWER_DOWN,
6408 (val | 1<<10)); 5901 (val | 1<<10));
@@ -6416,28 +5909,20 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6416 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 5909 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6417 /* Phase2 of POWER_DOWN_RESET */ 5910 /* Phase2 of POWER_DOWN_RESET */
6418 /* Release bit 10 (Release Tx power down) */ 5911 /* Release bit 10 (Release Tx power down) */
6419 bnx2x_cl45_read(bp, port, 5912 bnx2x_cl45_read(bp, phy_blk[port],
6420 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6421 ext_phy_addr[port],
6422 MDIO_PMA_DEVAD, 5913 MDIO_PMA_DEVAD,
6423 MDIO_PMA_REG_TX_POWER_DOWN, &val); 5914 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6424 5915
6425 bnx2x_cl45_write(bp, port, 5916 bnx2x_cl45_write(bp, phy_blk[port],
6426 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6427 ext_phy_addr[port],
6428 MDIO_PMA_DEVAD, 5917 MDIO_PMA_DEVAD,
6429 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 5918 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6430 msleep(15); 5919 msleep(15);
6431 5920
6432 /* Read modify write the SPI-ROM version select register */ 5921 /* Read modify write the SPI-ROM version select register */
6433 bnx2x_cl45_read(bp, port, 5922 bnx2x_cl45_read(bp, phy_blk[port],
6434 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6435 ext_phy_addr[port],
6436 MDIO_PMA_DEVAD, 5923 MDIO_PMA_DEVAD,
6437 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 5924 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6438 bnx2x_cl45_write(bp, port, 5925 bnx2x_cl45_write(bp, phy_blk[port],
6439 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6440 ext_phy_addr[port],
6441 MDIO_PMA_DEVAD, 5926 MDIO_PMA_DEVAD,
6442 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 5927 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6443 5928
@@ -6446,14 +5931,14 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6446 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 5931 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6447 } 5932 }
6448 return 0; 5933 return 0;
6449
6450} 5934}
6451 5935
6452static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base) 5936static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6453{ 5937{
6454 u8 ext_phy_addr[PORT_MAX];
6455 s8 port, first_port, i; 5938 s8 port, first_port, i;
6456 u32 swap_val, swap_override; 5939 u32 swap_val, swap_override;
5940 struct bnx2x_phy phy[PORT_MAX];
5941 struct bnx2x_phy *phy_blk[PORT_MAX];
6457 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n"); 5942 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6458 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 5943 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6459 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 5944 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
@@ -6469,10 +5954,12 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6469 /* PART1 - Reset both phys */ 5954 /* PART1 - Reset both phys */
6470 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) { 5955 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6471 /* Extract the ext phy address for the port */ 5956 /* Extract the ext phy address for the port */
6472 u32 ext_phy_config = REG_RD(bp, shmem_base + 5957 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6473 offsetof(struct shmem_region, 5958 port, &phy[port]) !=
6474 dev_info.port_hw_config[port].external_phy_config)); 5959 0) {
6475 5960 DP(NETIF_MSG_LINK, "populate phy failed\n");
5961 return -EINVAL;
5962 }
6476 /* disable attentions */ 5963 /* disable attentions */
6477 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 5964 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6478 (NIG_MASK_XGXS0_LINK_STATUS | 5965 (NIG_MASK_XGXS0_LINK_STATUS |
@@ -6480,12 +5967,9 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6480 NIG_MASK_SERDES0_LINK_STATUS | 5967 NIG_MASK_SERDES0_LINK_STATUS |
6481 NIG_MASK_MI_INT)); 5968 NIG_MASK_MI_INT));
6482 5969
6483 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
6484 5970
6485 /* Reset the phy */ 5971 /* Reset the phy */
6486 bnx2x_cl45_write(bp, port, 5972 bnx2x_cl45_write(bp, &phy[port],
6487 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6488 ext_phy_addr[port],
6489 MDIO_PMA_DEVAD, 5973 MDIO_PMA_DEVAD,
6490 MDIO_PMA_REG_CTRL, 5974 MDIO_PMA_REG_CTRL,
6491 1<<15); 5975 1<<15);
@@ -6493,16 +5977,20 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6493 5977
6494 /* Add delay of 150ms after reset */ 5978 /* Add delay of 150ms after reset */
6495 msleep(150); 5979 msleep(150);
6496 5980 if (phy[PORT_0].addr & 0x1) {
5981 phy_blk[PORT_0] = &(phy[PORT_1]);
5982 phy_blk[PORT_1] = &(phy[PORT_0]);
5983 } else {
5984 phy_blk[PORT_0] = &(phy[PORT_0]);
5985 phy_blk[PORT_1] = &(phy[PORT_1]);
5986 }
6497 /* PART2 - Download firmware to both phys */ 5987 /* PART2 - Download firmware to both phys */
6498 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) { 5988 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6499 u16 fw_ver1; 5989 u16 fw_ver1;
6500 5990
6501 bnx2x_bcm8727_external_rom_boot(bp, port, 5991 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
6502 ext_phy_addr[port], shmem_base); 5992 port, shmem_base);
6503 5993 bnx2x_cl45_read(bp, phy_blk[port],
6504 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6505 ext_phy_addr[port],
6506 MDIO_PMA_DEVAD, 5994 MDIO_PMA_DEVAD,
6507 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 5995 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6508 if (fw_ver1 == 0 || fw_ver1 == 0x4321) { 5996 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
@@ -6517,13 +6005,11 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6517 return 0; 6005 return 0;
6518} 6006}
6519 6007
6520
6521static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base) 6008static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6522{ 6009{
6523 u8 ext_phy_addr;
6524 u32 val; 6010 u32 val;
6525 s8 port; 6011 s8 port;
6526 6012 struct bnx2x_phy phy;
6527 /* Use port1 because of the static port-swap */ 6013 /* Use port1 because of the static port-swap */
6528 /* Enable the module detection interrupt */ 6014 /* Enable the module detection interrupt */
6529 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 6015 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
@@ -6535,15 +6021,17 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6535 msleep(5); 6021 msleep(5);
6536 for (port = 0; port < PORT_MAX; port++) { 6022 for (port = 0; port < PORT_MAX; port++) {
6537 /* Extract the ext phy address for the port */ 6023 /* Extract the ext phy address for the port */
6538 u32 ext_phy_config = REG_RD(bp, shmem_base + 6024 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base,
6539 offsetof(struct shmem_region, 6025 port, &phy) !=
6540 dev_info.port_hw_config[port].external_phy_config)); 6026 0) {
6027 DP(NETIF_MSG_LINK, "populate phy failed\n");
6028 return -EINVAL;
6029 }
6541 6030
6542 ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 6031 /* Reset phy*/
6543 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n", 6032 bnx2x_cl45_write(bp, &phy,
6544 ext_phy_addr); 6033 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6545 6034
6546 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6547 6035
6548 /* Set fault module detected LED on */ 6036 /* Set fault module detected LED on */
6549 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 6037 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
@@ -6594,29 +6082,23 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6594 return rc; 6082 return rc;
6595} 6083}
6596 6084
6597void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) 6085void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6598{ 6086{
6599 u16 val, cnt; 6087 u16 val, cnt;
6600 6088
6601 bnx2x_cl45_read(bp, port, 6089 bnx2x_cl45_read(bp, phy,
6602 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6603 phy_addr,
6604 MDIO_PMA_DEVAD, 6090 MDIO_PMA_DEVAD,
6605 MDIO_PMA_REG_7101_RESET, &val); 6091 MDIO_PMA_REG_7101_RESET, &val);
6606 6092
6607 for (cnt = 0; cnt < 10; cnt++) { 6093 for (cnt = 0; cnt < 10; cnt++) {
6608 msleep(50); 6094 msleep(50);
6609 /* Writes a self-clearing reset */ 6095 /* Writes a self-clearing reset */
6610 bnx2x_cl45_write(bp, port, 6096 bnx2x_cl45_write(bp, phy,
6611 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6612 phy_addr,
6613 MDIO_PMA_DEVAD, 6097 MDIO_PMA_DEVAD,
6614 MDIO_PMA_REG_7101_RESET, 6098 MDIO_PMA_REG_7101_RESET,
6615 (val | (1<<15))); 6099 (val | (1<<15)));
6616 /* Wait for clear */ 6100 /* Wait for clear */
6617 bnx2x_cl45_read(bp, port, 6101 bnx2x_cl45_read(bp, phy,
6618 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6619 phy_addr,
6620 MDIO_PMA_DEVAD, 6102 MDIO_PMA_DEVAD,
6621 MDIO_PMA_REG_7101_RESET, &val); 6103 MDIO_PMA_REG_7101_RESET, &val);
6622 6104
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 11:22:27 -0500