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authorYaniv Rosner <yanivr@broadcom.com>2011-01-30 23:21:34 -0500
committerDavid S. Miller <davem@davemloft.net>2011-01-31 16:22:40 -0500
commitcd88ccee1da3626d1c40dfcff8617b2c83271365 (patch)
treea1a3ea95c3f8e57a637d0121270b8db6c1027fa8 /drivers/net/bnx2x/bnx2x_link.c
parent5403c8a29521a6eb02f9283dbbe0184527f8f42b (diff)
bnx2x: Fix line indentation
This patch contains cosmetic changes only to fix code alignment, and update copyright comment year Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c1226
1 files changed, 591 insertions, 635 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index dd1210fddfff..e992d40e2462 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -1,4 +1,4 @@
1/* Copyright 2008-2009 Broadcom Corporation 1/* Copyright 2008-2011 Broadcom Corporation
2 * 2 *
3 * Unless you and Broadcom execute a separate written software license 3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you 4 * agreement governing use of this software, this software is licensed to you
@@ -28,12 +28,13 @@
28 28
29/********************************************************/ 29/********************************************************/
30#define ETH_HLEN 14 30#define ETH_HLEN 14
31#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */ 31/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
32#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
32#define ETH_MIN_PACKET_SIZE 60 33#define ETH_MIN_PACKET_SIZE 60
33#define ETH_MAX_PACKET_SIZE 1500 34#define ETH_MAX_PACKET_SIZE 1500
34#define ETH_MAX_JUMBO_PACKET_SIZE 9600 35#define ETH_MAX_JUMBO_PACKET_SIZE 9600
35#define MDIO_ACCESS_TIMEOUT 1000 36#define MDIO_ACCESS_TIMEOUT 1000
36#define BMAC_CONTROL_RX_ENABLE 2 37#define BMAC_CONTROL_RX_ENABLE 2
37 38
38/***********************************************************/ 39/***********************************************************/
39/* Shortcut definitions */ 40/* Shortcut definitions */
@@ -79,7 +80,7 @@
79 80
80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
82#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83#define AUTONEG_PARALLEL \ 84#define AUTONEG_PARALLEL \
84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
85#define AUTONEG_SGMII_FIBER_AUTODET \ 86#define AUTONEG_SGMII_FIBER_AUTODET \
@@ -112,10 +113,10 @@
112#define GP_STATUS_10G_KX4 \ 113#define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114 115
115#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 116#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 117#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 118#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 119#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 120#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 121#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 122#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
@@ -123,18 +124,18 @@
123#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 124#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 125#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 126#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 127#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 128#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD 129#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD 130#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD 131#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD 132#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD 133#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD 134#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD 135#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD 136#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD 137#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD 138#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138 139
139#define PHY_XGXS_FLAG 0x1 140#define PHY_XGXS_FLAG 0x1
140#define PHY_SGMII_FLAG 0x2 141#define PHY_SGMII_FLAG 0x2
@@ -142,7 +143,7 @@
142 143
143/* */ 144/* */
144#define SFP_EEPROM_CON_TYPE_ADDR 0x2 145#define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 146 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 147 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 148
148 149
@@ -153,15 +154,15 @@
153 154
154#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 155#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 157 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
157 158
158#define SFP_EEPROM_OPTIONS_ADDR 0x40 159#define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 160 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160#define SFP_EEPROM_OPTIONS_SIZE 2 161#define SFP_EEPROM_OPTIONS_SIZE 2
161 162
162#define EDC_MODE_LINEAR 0x0022 163#define EDC_MODE_LINEAR 0x0022
163#define EDC_MODE_LIMITING 0x0044 164#define EDC_MODE_LIMITING 0x0044
164#define EDC_MODE_PASSIVE_DAC 0x0055 165#define EDC_MODE_PASSIVE_DAC 0x0055
165 166
166 167
167#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 168#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
@@ -329,8 +330,7 @@ void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
329 if ((0 == total_bw) || 330 if ((0 == total_bw) ||
330 (0 == cos0_bw) || 331 (0 == cos0_bw) ||
331 (0 == cos1_bw)) { 332 (0 == cos1_bw)) {
332 DP(NETIF_MSG_LINK, 333 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
333 "bnx2x_ets_bw_limit: Total BW can't be zero\n");
334 return; 334 return;
335 } 335 }
336 336
@@ -471,7 +471,7 @@ void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
471/* MAC/PBF section */ 471/* MAC/PBF section */
472/******************************************************************/ 472/******************************************************************/
473static void bnx2x_emac_init(struct link_params *params, 473static void bnx2x_emac_init(struct link_params *params,
474 struct link_vars *vars) 474 struct link_vars *vars)
475{ 475{
476 /* reset and unreset the emac core */ 476 /* reset and unreset the emac core */
477 struct bnx2x *bp = params->bp; 477 struct bnx2x *bp = params->bp;
@@ -481,10 +481,10 @@ static void bnx2x_emac_init(struct link_params *params,
481 u16 timeout; 481 u16 timeout;
482 482
483 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 483 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
484 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 484 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
485 udelay(5); 485 udelay(5);
486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
487 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 487 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
488 488
489 /* init emac - use read-modify-write */ 489 /* init emac - use read-modify-write */
490 /* self clear reset */ 490 /* self clear reset */
@@ -515,7 +515,7 @@ static void bnx2x_emac_init(struct link_params *params,
515} 515}
516 516
517static u8 bnx2x_emac_enable(struct link_params *params, 517static u8 bnx2x_emac_enable(struct link_params *params,
518 struct link_vars *vars, u8 lb) 518 struct link_vars *vars, u8 lb)
519{ 519{
520 struct bnx2x *bp = params->bp; 520 struct bnx2x *bp = params->bp;
521 u8 port = params->port; 521 u8 port = params->port;
@@ -531,8 +531,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
531 if (CHIP_REV_IS_EMUL(bp)) { 531 if (CHIP_REV_IS_EMUL(bp)) {
532 /* Use lane 1 (of lanes 0-3) */ 532 /* Use lane 1 (of lanes 0-3) */
533 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 533 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + 534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
535 port*4, 1);
536 } 535 }
537 /* for fpga */ 536 /* for fpga */
538 else 537 else
@@ -542,40 +541,35 @@ static u8 bnx2x_emac_enable(struct link_params *params,
542 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n"); 541 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
543 542
544 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 543 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
545 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 544 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
546 0);
547 } else 545 } else
548 /* ASIC */ 546 /* ASIC */
549 if (vars->phy_flags & PHY_XGXS_FLAG) { 547 if (vars->phy_flags & PHY_XGXS_FLAG) {
550 u32 ser_lane = ((params->lane_config & 548 u32 ser_lane = ((params->lane_config &
551 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 549 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
552 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 550 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
553 551
554 DP(NETIF_MSG_LINK, "XGXS\n"); 552 DP(NETIF_MSG_LINK, "XGXS\n");
555 /* select the master lanes (out of 0-3) */ 553 /* select the master lanes (out of 0-3) */
556 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + 554 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
557 port*4, ser_lane);
558 /* select XGXS */ 555 /* select XGXS */
559 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + 556 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
560 port*4, 1);
561 557
562 } else { /* SerDes */ 558 } else { /* SerDes */
563 DP(NETIF_MSG_LINK, "SerDes\n"); 559 DP(NETIF_MSG_LINK, "SerDes\n");
564 /* select SerDes */ 560 /* select SerDes */
565 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + 561 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
566 port*4, 0);
567 } 562 }
568 563
569 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 564 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
570 EMAC_RX_MODE_RESET); 565 EMAC_RX_MODE_RESET);
571 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 566 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
572 EMAC_TX_MODE_RESET); 567 EMAC_TX_MODE_RESET);
573 568
574 if (CHIP_REV_IS_SLOW(bp)) { 569 if (CHIP_REV_IS_SLOW(bp)) {
575 /* config GMII mode */ 570 /* config GMII mode */
576 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 571 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
577 EMAC_WR(bp, EMAC_REG_EMAC_MODE, 572 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
578 (val | EMAC_MODE_PORT_GMII));
579 } else { /* ASIC */ 573 } else { /* ASIC */
580 /* pause enable/disable */ 574 /* pause enable/disable */
581 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 575 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
@@ -668,9 +662,8 @@ static u8 bnx2x_emac_enable(struct link_params *params,
668 662
669 if (CHIP_REV_IS_EMUL(bp)) { 663 if (CHIP_REV_IS_EMUL(bp)) {
670 /* take the BigMac out of reset */ 664 /* take the BigMac out of reset */
671 REG_WR(bp, 665 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
672 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 666 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
673 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
674 667
675 /* enable access for bmac registers */ 668 /* enable access for bmac registers */
676 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 669 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
@@ -731,8 +724,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
731 val |= (1<<5); 724 val |= (1<<5);
732 wb_data[0] = val; 725 wb_data[0] = val;
733 wb_data[1] = 0; 726 wb_data[1] = 0;
734 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, 727 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
735 wb_data, 2);
736 udelay(30); 728 udelay(30);
737 729
738 /* Tx control */ 730 /* Tx control */
@@ -781,7 +773,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
781 wb_data[0] = val; 773 wb_data[0] = val;
782 wb_data[1] = 0; 774 wb_data[1] = 0;
783 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 775 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
784 wb_data, 2); 776 wb_data, 2);
785 777
786 /* mac control */ 778 /* mac control */
787 val = 0x3; /* Enable RX and TX */ 779 val = 0x3; /* Enable RX and TX */
@@ -795,8 +787,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
795 787
796 wb_data[0] = val; 788 wb_data[0] = val;
797 wb_data[1] = 0; 789 wb_data[1] = 0;
798 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, 790 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
799 wb_data, 2);
800} 791}
801 792
802static void bnx2x_update_pfc_brb(struct link_params *params, 793static void bnx2x_update_pfc_brb(struct link_params *params,
@@ -1035,7 +1026,7 @@ void bnx2x_update_pfc(struct link_params *params,
1035 1026
1036static u8 bnx2x_bmac1_enable(struct link_params *params, 1027static u8 bnx2x_bmac1_enable(struct link_params *params,
1037 struct link_vars *vars, 1028 struct link_vars *vars,
1038 u8 is_lb) 1029 u8 is_lb)
1039{ 1030{
1040 struct bnx2x *bp = params->bp; 1031 struct bnx2x *bp = params->bp;
1041 u8 port = params->port; 1032 u8 port = params->port;
@@ -1049,9 +1040,8 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
1049 /* XGXS control */ 1040 /* XGXS control */
1050 wb_data[0] = 0x3c; 1041 wb_data[0] = 0x3c;
1051 wb_data[1] = 0; 1042 wb_data[1] = 0;
1052 REG_WR_DMAE(bp, bmac_addr + 1043 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1053 BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 1044 wb_data, 2);
1054 wb_data, 2);
1055 1045
1056 /* tx MAC SA */ 1046 /* tx MAC SA */
1057 wb_data[0] = ((params->mac_addr[2] << 24) | 1047 wb_data[0] = ((params->mac_addr[2] << 24) |
@@ -1060,8 +1050,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
1060 params->mac_addr[5]); 1050 params->mac_addr[5]);
1061 wb_data[1] = ((params->mac_addr[0] << 8) | 1051 wb_data[1] = ((params->mac_addr[0] << 8) |
1062 params->mac_addr[1]); 1052 params->mac_addr[1]);
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, 1053 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1064 wb_data, 2);
1065 1054
1066 /* mac control */ 1055 /* mac control */
1067 val = 0x3; 1056 val = 0x3;
@@ -1071,28 +1060,24 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
1071 } 1060 }
1072 wb_data[0] = val; 1061 wb_data[0] = val;
1073 wb_data[1] = 0; 1062 wb_data[1] = 0;
1074 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, 1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1075 wb_data, 2);
1076 1064
1077 /* set rx mtu */ 1065 /* set rx mtu */
1078 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 1066 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1079 wb_data[1] = 0; 1067 wb_data[1] = 0;
1080 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, 1068 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1081 wb_data, 2);
1082 1069
1083 bnx2x_update_pfc_bmac1(params, vars); 1070 bnx2x_update_pfc_bmac1(params, vars);
1084 1071
1085 /* set tx mtu */ 1072 /* set tx mtu */
1086 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 1073 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1087 wb_data[1] = 0; 1074 wb_data[1] = 0;
1088 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, 1075 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1089 wb_data, 2);
1090 1076
1091 /* set cnt max size */ 1077 /* set cnt max size */
1092 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 1078 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1093 wb_data[1] = 0; 1079 wb_data[1] = 0;
1094 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, 1080 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1095 wb_data, 2);
1096 1081
1097 /* configure safc */ 1082 /* configure safc */
1098 wb_data[0] = 0x1000200; 1083 wb_data[0] = 0x1000200;
@@ -1103,8 +1088,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
1103 if (CHIP_REV_IS_EMUL(bp)) { 1088 if (CHIP_REV_IS_EMUL(bp)) {
1104 wb_data[0] = 0xf000; 1089 wb_data[0] = 0xf000;
1105 wb_data[1] = 0; 1090 wb_data[1] = 0;
1106 REG_WR_DMAE(bp, 1091 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1107 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1108 wb_data, 2); 1092 wb_data, 2);
1109 } 1093 }
1110 1094
@@ -1126,16 +1110,14 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,
1126 1110
1127 wb_data[0] = 0; 1111 wb_data[0] = 0;
1128 wb_data[1] = 0; 1112 wb_data[1] = 0;
1129 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, 1113 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1130 wb_data, 2);
1131 udelay(30); 1114 udelay(30);
1132 1115
1133 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 1116 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1134 wb_data[0] = 0x3c; 1117 wb_data[0] = 0x3c;
1135 wb_data[1] = 0; 1118 wb_data[1] = 0;
1136 REG_WR_DMAE(bp, bmac_addr + 1119 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1137 BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 1120 wb_data, 2);
1138 wb_data, 2);
1139 1121
1140 udelay(30); 1122 udelay(30);
1141 1123
@@ -1147,7 +1129,7 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,
1147 wb_data[1] = ((params->mac_addr[0] << 8) | 1129 wb_data[1] = ((params->mac_addr[0] << 8) |
1148 params->mac_addr[1]); 1130 params->mac_addr[1]);
1149 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 1131 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1150 wb_data, 2); 1132 wb_data, 2);
1151 1133
1152 udelay(30); 1134 udelay(30);
1153 1135
@@ -1155,27 +1137,24 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,
1155 wb_data[0] = 0x1000200; 1137 wb_data[0] = 0x1000200;
1156 wb_data[1] = 0; 1138 wb_data[1] = 0;
1157 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 1139 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1158 wb_data, 2); 1140 wb_data, 2);
1159 udelay(30); 1141 udelay(30);
1160 1142
1161 /* set rx mtu */ 1143 /* set rx mtu */
1162 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 1144 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1163 wb_data[1] = 0; 1145 wb_data[1] = 0;
1164 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, 1146 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1165 wb_data, 2);
1166 udelay(30); 1147 udelay(30);
1167 1148
1168 /* set tx mtu */ 1149 /* set tx mtu */
1169 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 1150 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1170 wb_data[1] = 0; 1151 wb_data[1] = 0;
1171 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, 1152 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1172 wb_data, 2);
1173 udelay(30); 1153 udelay(30);
1174 /* set cnt max size */ 1154 /* set cnt max size */
1175 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 1155 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1176 wb_data[1] = 0; 1156 wb_data[1] = 0;
1177 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, 1157 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1178 wb_data, 2);
1179 udelay(30); 1158 udelay(30);
1180 bnx2x_update_pfc_bmac2(params, vars, is_lb); 1159 bnx2x_update_pfc_bmac2(params, vars, is_lb);
1181 1160
@@ -1191,11 +1170,11 @@ static u8 bnx2x_bmac_enable(struct link_params *params,
1191 u32 val; 1170 u32 val;
1192 /* reset and unreset the BigMac */ 1171 /* reset and unreset the BigMac */
1193 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1172 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1194 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1173 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1195 msleep(1); 1174 msleep(1);
1196 1175
1197 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1176 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1198 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1177 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1199 1178
1200 /* enable access for bmac registers */ 1179 /* enable access for bmac registers */
1201 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 1180 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
@@ -1230,15 +1209,14 @@ static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1230 struct bnx2x *bp = params->bp; 1209 struct bnx2x *bp = params->bp;
1231 1210
1232 REG_WR(bp, params->shmem_base + 1211 REG_WR(bp, params->shmem_base +
1233 offsetof(struct shmem_region, 1212 offsetof(struct shmem_region,
1234 port_mb[params->port].link_status), 1213 port_mb[params->port].link_status), link_status);
1235 link_status);
1236} 1214}
1237 1215
1238static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) 1216static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1239{ 1217{
1240 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 1218 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1241 NIG_REG_INGRESS_BMAC0_MEM; 1219 NIG_REG_INGRESS_BMAC0_MEM;
1242 u32 wb_data[2]; 1220 u32 wb_data[2];
1243 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 1221 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1244 1222
@@ -1250,12 +1228,12 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1250 if (CHIP_IS_E2(bp)) { 1228 if (CHIP_IS_E2(bp)) {
1251 /* Clear Rx Enable bit in BMAC_CONTROL register */ 1229 /* Clear Rx Enable bit in BMAC_CONTROL register */
1252 REG_RD_DMAE(bp, bmac_addr + 1230 REG_RD_DMAE(bp, bmac_addr +
1253 BIGMAC2_REGISTER_BMAC_CONTROL, 1231 BIGMAC2_REGISTER_BMAC_CONTROL,
1254 wb_data, 2); 1232 wb_data, 2);
1255 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 1233 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1256 REG_WR_DMAE(bp, bmac_addr + 1234 REG_WR_DMAE(bp, bmac_addr +
1257 BIGMAC2_REGISTER_BMAC_CONTROL, 1235 BIGMAC2_REGISTER_BMAC_CONTROL,
1258 wb_data, 2); 1236 wb_data, 2);
1259 } else { 1237 } else {
1260 /* Clear Rx Enable bit in BMAC_CONTROL register */ 1238 /* Clear Rx Enable bit in BMAC_CONTROL register */
1261 REG_RD_DMAE(bp, bmac_addr + 1239 REG_RD_DMAE(bp, bmac_addr +
@@ -1271,7 +1249,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1271} 1249}
1272 1250
1273static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 1251static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1274 u32 line_speed) 1252 u32 line_speed)
1275{ 1253{
1276 struct bnx2x *bp = params->bp; 1254 struct bnx2x *bp = params->bp;
1277 u8 port = params->port; 1255 u8 port = params->port;
@@ -1308,7 +1286,7 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1308 /* update threshold */ 1286 /* update threshold */
1309 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 1287 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1310 /* update init credit */ 1288 /* update init credit */
1311 init_crd = 778; /* (800-18-4) */ 1289 init_crd = 778; /* (800-18-4) */
1312 1290
1313 } else { 1291 } else {
1314 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 1292 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
@@ -1414,8 +1392,7 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1414 for (i = 0; i < 50; i++) { 1392 for (i = 0; i < 50; i++) {
1415 udelay(10); 1393 udelay(10);
1416 1394
1417 tmp = REG_RD(bp, phy->mdio_ctrl + 1395 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1418 EMAC_REG_EMAC_MDIO_COMM);
1419 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 1396 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1420 udelay(5); 1397 udelay(5);
1421 break; 1398 break;
@@ -1435,7 +1412,7 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1435 udelay(10); 1412 udelay(10);
1436 1413
1437 tmp = REG_RD(bp, phy->mdio_ctrl + 1414 tmp = REG_RD(bp, phy->mdio_ctrl +
1438 EMAC_REG_EMAC_MDIO_COMM); 1415 EMAC_REG_EMAC_MDIO_COMM);
1439 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 1416 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1440 udelay(5); 1417 udelay(5);
1441 break; 1418 break;
@@ -1466,7 +1443,7 @@ u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1466 1443
1467 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 1444 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1468 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL | 1445 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1469 EMAC_MDIO_MODE_CLOCK_CNT)); 1446 EMAC_MDIO_MODE_CLOCK_CNT));
1470 val |= (EMAC_MDIO_MODE_CLAUSE_45 | 1447 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1471 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); 1448 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1472 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); 1449 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
@@ -1505,7 +1482,7 @@ u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1505 udelay(10); 1482 udelay(10);
1506 1483
1507 val = REG_RD(bp, phy->mdio_ctrl + 1484 val = REG_RD(bp, phy->mdio_ctrl +
1508 EMAC_REG_EMAC_MDIO_COMM); 1485 EMAC_REG_EMAC_MDIO_COMM);
1509 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 1486 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1510 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 1487 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1511 break; 1488 break;
@@ -1576,16 +1553,15 @@ static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1576 aer_val = 0x3800 + offset - 1; 1553 aer_val = 0x3800 + offset - 1;
1577 else 1554 else
1578 aer_val = 0x3800 + offset; 1555 aer_val = 0x3800 + offset;
1579 CL45_WR_OVER_CL22(bp, phy, 1556 CL45_WR_OVER_CL22(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1580 MDIO_REG_BANK_AER_BLOCK, 1557 MDIO_AER_BLOCK_AER_REG, aer_val);
1581 MDIO_AER_BLOCK_AER_REG, aer_val);
1582} 1558}
1583static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp, 1559static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1584 struct bnx2x_phy *phy) 1560 struct bnx2x_phy *phy)
1585{ 1561{
1586 CL45_WR_OVER_CL22(bp, phy, 1562 CL45_WR_OVER_CL22(bp, phy,
1587 MDIO_REG_BANK_AER_BLOCK, 1563 MDIO_REG_BANK_AER_BLOCK,
1588 MDIO_AER_BLOCK_AER_REG, 0x3800); 1564 MDIO_AER_BLOCK_AER_REG, 0x3800);
1589} 1565}
1590 1566
1591/******************************************************************/ 1567/******************************************************************/
@@ -1621,9 +1597,8 @@ static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1621 1597
1622 bnx2x_set_serdes_access(bp, port); 1598 bnx2x_set_serdes_access(bp, port);
1623 1599
1624 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + 1600 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1625 port*0x10, 1601 DEFAULT_PHY_DEV_ADDR);
1626 DEFAULT_PHY_DEV_ADDR);
1627} 1602}
1628 1603
1629static void bnx2x_xgxs_deassert(struct link_params *params) 1604static void bnx2x_xgxs_deassert(struct link_params *params)
@@ -1641,23 +1616,22 @@ static void bnx2x_xgxs_deassert(struct link_params *params)
1641 udelay(500); 1616 udelay(500);
1642 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 1617 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1643 1618
1644 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + 1619 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1645 port*0x18, 0);
1646 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 1620 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1647 params->phy[INT_PHY].def_md_devad); 1621 params->phy[INT_PHY].def_md_devad);
1648} 1622}
1649 1623
1650 1624
1651void bnx2x_link_status_update(struct link_params *params, 1625void bnx2x_link_status_update(struct link_params *params,
1652 struct link_vars *vars) 1626 struct link_vars *vars)
1653{ 1627{
1654 struct bnx2x *bp = params->bp; 1628 struct bnx2x *bp = params->bp;
1655 u8 link_10g; 1629 u8 link_10g;
1656 u8 port = params->port; 1630 u8 port = params->port;
1657 1631
1658 vars->link_status = REG_RD(bp, params->shmem_base + 1632 vars->link_status = REG_RD(bp, params->shmem_base +
1659 offsetof(struct shmem_region, 1633 offsetof(struct shmem_region,
1660 port_mb[port].link_status)); 1634 port_mb[port].link_status));
1661 1635
1662 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 1636 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1663 1637
@@ -1667,7 +1641,7 @@ void bnx2x_link_status_update(struct link_params *params,
1667 vars->phy_link_up = 1; 1641 vars->phy_link_up = 1;
1668 vars->duplex = DUPLEX_FULL; 1642 vars->duplex = DUPLEX_FULL;
1669 switch (vars->link_status & 1643 switch (vars->link_status &
1670 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 1644 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1671 case LINK_10THD: 1645 case LINK_10THD:
1672 vars->duplex = DUPLEX_HALF; 1646 vars->duplex = DUPLEX_HALF;
1673 /* fall thru */ 1647 /* fall thru */
@@ -1779,20 +1753,20 @@ static void bnx2x_set_master_ln(struct link_params *params,
1779{ 1753{
1780 struct bnx2x *bp = params->bp; 1754 struct bnx2x *bp = params->bp;
1781 u16 new_master_ln, ser_lane; 1755 u16 new_master_ln, ser_lane;
1782 ser_lane = ((params->lane_config & 1756 ser_lane = ((params->lane_config &
1783 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1757 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1784 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1758 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1785 1759
1786 /* set the master_ln for AN */ 1760 /* set the master_ln for AN */
1787 CL45_RD_OVER_CL22(bp, phy, 1761 CL45_RD_OVER_CL22(bp, phy,
1788 MDIO_REG_BANK_XGXS_BLOCK2, 1762 MDIO_REG_BANK_XGXS_BLOCK2,
1789 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 1763 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1790 &new_master_ln); 1764 &new_master_ln);
1791 1765
1792 CL45_WR_OVER_CL22(bp, phy, 1766 CL45_WR_OVER_CL22(bp, phy,
1793 MDIO_REG_BANK_XGXS_BLOCK2 , 1767 MDIO_REG_BANK_XGXS_BLOCK2 ,
1794 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 1768 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1795 (new_master_ln | ser_lane)); 1769 (new_master_ln | ser_lane));
1796} 1770}
1797 1771
1798static u8 bnx2x_reset_unicore(struct link_params *params, 1772static u8 bnx2x_reset_unicore(struct link_params *params,
@@ -1804,15 +1778,15 @@ static u8 bnx2x_reset_unicore(struct link_params *params,
1804 u16 i; 1778 u16 i;
1805 1779
1806 CL45_RD_OVER_CL22(bp, phy, 1780 CL45_RD_OVER_CL22(bp, phy,
1807 MDIO_REG_BANK_COMBO_IEEE0, 1781 MDIO_REG_BANK_COMBO_IEEE0,
1808 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 1782 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1809 1783
1810 /* reset the unicore */ 1784 /* reset the unicore */
1811 CL45_WR_OVER_CL22(bp, phy, 1785 CL45_WR_OVER_CL22(bp, phy,
1812 MDIO_REG_BANK_COMBO_IEEE0, 1786 MDIO_REG_BANK_COMBO_IEEE0,
1813 MDIO_COMBO_IEEE0_MII_CONTROL, 1787 MDIO_COMBO_IEEE0_MII_CONTROL,
1814 (mii_control | 1788 (mii_control |
1815 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 1789 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1816 if (set_serdes) 1790 if (set_serdes)
1817 bnx2x_set_serdes_access(bp, params->port); 1791 bnx2x_set_serdes_access(bp, params->port);
1818 1792
@@ -1822,9 +1796,9 @@ static u8 bnx2x_reset_unicore(struct link_params *params,
1822 1796
1823 /* the reset erased the previous bank value */ 1797 /* the reset erased the previous bank value */
1824 CL45_RD_OVER_CL22(bp, phy, 1798 CL45_RD_OVER_CL22(bp, phy,
1825 MDIO_REG_BANK_COMBO_IEEE0, 1799 MDIO_REG_BANK_COMBO_IEEE0,
1826 MDIO_COMBO_IEEE0_MII_CONTROL, 1800 MDIO_COMBO_IEEE0_MII_CONTROL,
1827 &mii_control); 1801 &mii_control);
1828 1802
1829 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 1803 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1830 udelay(5); 1804 udelay(5);
@@ -1846,38 +1820,38 @@ static void bnx2x_set_swap_lanes(struct link_params *params,
1846 u16 ser_lane, rx_lane_swap, tx_lane_swap; 1820 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1847 1821
1848 ser_lane = ((params->lane_config & 1822 ser_lane = ((params->lane_config &
1849 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1823 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1850 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1824 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1851 rx_lane_swap = ((params->lane_config & 1825 rx_lane_swap = ((params->lane_config &
1852 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 1826 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1853 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 1827 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1854 tx_lane_swap = ((params->lane_config & 1828 tx_lane_swap = ((params->lane_config &
1855 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 1829 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1856 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 1830 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1857 1831
1858 if (rx_lane_swap != 0x1b) { 1832 if (rx_lane_swap != 0x1b) {
1859 CL45_WR_OVER_CL22(bp, phy, 1833 CL45_WR_OVER_CL22(bp, phy,
1860 MDIO_REG_BANK_XGXS_BLOCK2, 1834 MDIO_REG_BANK_XGXS_BLOCK2,
1861 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 1835 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1862 (rx_lane_swap | 1836 (rx_lane_swap |
1863 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 1837 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1864 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 1838 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1865 } else { 1839 } else {
1866 CL45_WR_OVER_CL22(bp, phy, 1840 CL45_WR_OVER_CL22(bp, phy,
1867 MDIO_REG_BANK_XGXS_BLOCK2, 1841 MDIO_REG_BANK_XGXS_BLOCK2,
1868 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 1842 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1869 } 1843 }
1870 1844
1871 if (tx_lane_swap != 0x1b) { 1845 if (tx_lane_swap != 0x1b) {
1872 CL45_WR_OVER_CL22(bp, phy, 1846 CL45_WR_OVER_CL22(bp, phy,
1873 MDIO_REG_BANK_XGXS_BLOCK2, 1847 MDIO_REG_BANK_XGXS_BLOCK2,
1874 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 1848 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1875 (tx_lane_swap | 1849 (tx_lane_swap |
1876 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 1850 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1877 } else { 1851 } else {
1878 CL45_WR_OVER_CL22(bp, phy, 1852 CL45_WR_OVER_CL22(bp, phy,
1879 MDIO_REG_BANK_XGXS_BLOCK2, 1853 MDIO_REG_BANK_XGXS_BLOCK2,
1880 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 1854 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1881 } 1855 }
1882} 1856}
1883 1857
@@ -1887,9 +1861,9 @@ static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1887 struct bnx2x *bp = params->bp; 1861 struct bnx2x *bp = params->bp;
1888 u16 control2; 1862 u16 control2;
1889 CL45_RD_OVER_CL22(bp, phy, 1863 CL45_RD_OVER_CL22(bp, phy,
1890 MDIO_REG_BANK_SERDES_DIGITAL, 1864 MDIO_REG_BANK_SERDES_DIGITAL,
1891 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1865 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1892 &control2); 1866 &control2);
1893 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 1867 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1894 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 1868 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1895 else 1869 else
@@ -1897,9 +1871,9 @@ static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1897 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 1871 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1898 phy->speed_cap_mask, control2); 1872 phy->speed_cap_mask, control2);
1899 CL45_WR_OVER_CL22(bp, phy, 1873 CL45_WR_OVER_CL22(bp, phy,
1900 MDIO_REG_BANK_SERDES_DIGITAL, 1874 MDIO_REG_BANK_SERDES_DIGITAL,
1901 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 1875 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1902 control2); 1876 control2);
1903 1877
1904 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 1878 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1905 (phy->speed_cap_mask & 1879 (phy->speed_cap_mask &
@@ -1907,45 +1881,45 @@ static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1907 DP(NETIF_MSG_LINK, "XGXS\n"); 1881 DP(NETIF_MSG_LINK, "XGXS\n");
1908 1882
1909 CL45_WR_OVER_CL22(bp, phy, 1883 CL45_WR_OVER_CL22(bp, phy,
1910 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1884 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1911 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 1885 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1912 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 1886 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1913 1887
1914 CL45_RD_OVER_CL22(bp, phy, 1888 CL45_RD_OVER_CL22(bp, phy,
1915 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1889 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1916 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 1890 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1917 &control2); 1891 &control2);
1918 1892
1919 1893
1920 control2 |= 1894 control2 |=
1921 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 1895 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1922 1896
1923 CL45_WR_OVER_CL22(bp, phy, 1897 CL45_WR_OVER_CL22(bp, phy,
1924 MDIO_REG_BANK_10G_PARALLEL_DETECT, 1898 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1925 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 1899 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1926 control2); 1900 control2);
1927 1901
1928 /* Disable parallel detection of HiG */ 1902 /* Disable parallel detection of HiG */
1929 CL45_WR_OVER_CL22(bp, phy, 1903 CL45_WR_OVER_CL22(bp, phy,
1930 MDIO_REG_BANK_XGXS_BLOCK2, 1904 MDIO_REG_BANK_XGXS_BLOCK2,
1931 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 1905 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1932 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 1906 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1933 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 1907 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1934 } 1908 }
1935} 1909}
1936 1910
1937static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 1911static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1938 struct link_params *params, 1912 struct link_params *params,
1939 struct link_vars *vars, 1913 struct link_vars *vars,
1940 u8 enable_cl73) 1914 u8 enable_cl73)
1941{ 1915{
1942 struct bnx2x *bp = params->bp; 1916 struct bnx2x *bp = params->bp;
1943 u16 reg_val; 1917 u16 reg_val;
1944 1918
1945 /* CL37 Autoneg */ 1919 /* CL37 Autoneg */
1946 CL45_RD_OVER_CL22(bp, phy, 1920 CL45_RD_OVER_CL22(bp, phy,
1947 MDIO_REG_BANK_COMBO_IEEE0, 1921 MDIO_REG_BANK_COMBO_IEEE0,
1948 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 1922 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1949 1923
1950 /* CL37 Autoneg Enabled */ 1924 /* CL37 Autoneg Enabled */
1951 if (vars->line_speed == SPEED_AUTO_NEG) 1925 if (vars->line_speed == SPEED_AUTO_NEG)
@@ -1955,14 +1929,14 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1955 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 1929 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1956 1930
1957 CL45_WR_OVER_CL22(bp, phy, 1931 CL45_WR_OVER_CL22(bp, phy,
1958 MDIO_REG_BANK_COMBO_IEEE0, 1932 MDIO_REG_BANK_COMBO_IEEE0,
1959 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 1933 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1960 1934
1961 /* Enable/Disable Autodetection */ 1935 /* Enable/Disable Autodetection */
1962 1936
1963 CL45_RD_OVER_CL22(bp, phy, 1937 CL45_RD_OVER_CL22(bp, phy,
1964 MDIO_REG_BANK_SERDES_DIGITAL, 1938 MDIO_REG_BANK_SERDES_DIGITAL,
1965 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val); 1939 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1966 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 1940 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1967 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 1941 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1968 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 1942 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
@@ -1972,13 +1946,13 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1972 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1946 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1973 1947
1974 CL45_WR_OVER_CL22(bp, phy, 1948 CL45_WR_OVER_CL22(bp, phy,
1975 MDIO_REG_BANK_SERDES_DIGITAL, 1949 MDIO_REG_BANK_SERDES_DIGITAL,
1976 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 1950 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1977 1951
1978 /* Enable TetonII and BAM autoneg */ 1952 /* Enable TetonII and BAM autoneg */
1979 CL45_RD_OVER_CL22(bp, phy, 1953 CL45_RD_OVER_CL22(bp, phy,
1980 MDIO_REG_BANK_BAM_NEXT_PAGE, 1954 MDIO_REG_BANK_BAM_NEXT_PAGE,
1981 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1955 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982 &reg_val); 1956 &reg_val);
1983 if (vars->line_speed == SPEED_AUTO_NEG) { 1957 if (vars->line_speed == SPEED_AUTO_NEG) {
1984 /* Enable BAM aneg Mode and TetonII aneg Mode */ 1958 /* Enable BAM aneg Mode and TetonII aneg Mode */
@@ -1990,16 +1964,16 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1990 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 1964 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1991 } 1965 }
1992 CL45_WR_OVER_CL22(bp, phy, 1966 CL45_WR_OVER_CL22(bp, phy,
1993 MDIO_REG_BANK_BAM_NEXT_PAGE, 1967 MDIO_REG_BANK_BAM_NEXT_PAGE,
1994 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1968 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1995 reg_val); 1969 reg_val);
1996 1970
1997 if (enable_cl73) { 1971 if (enable_cl73) {
1998 /* Enable Cl73 FSM status bits */ 1972 /* Enable Cl73 FSM status bits */
1999 CL45_WR_OVER_CL22(bp, phy, 1973 CL45_WR_OVER_CL22(bp, phy,
2000 MDIO_REG_BANK_CL73_USERB0, 1974 MDIO_REG_BANK_CL73_USERB0,
2001 MDIO_CL73_USERB0_CL73_UCTRL, 1975 MDIO_CL73_USERB0_CL73_UCTRL,
2002 0xe); 1976 0xe);
2003 1977
2004 /* Enable BAM Station Manager*/ 1978 /* Enable BAM Station Manager*/
2005 CL45_WR_OVER_CL22(bp, phy, 1979 CL45_WR_OVER_CL22(bp, phy,
@@ -2011,9 +1985,9 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2011 1985
2012 /* Advertise CL73 link speeds */ 1986 /* Advertise CL73 link speeds */
2013 CL45_RD_OVER_CL22(bp, phy, 1987 CL45_RD_OVER_CL22(bp, phy,
2014 MDIO_REG_BANK_CL73_IEEEB1, 1988 MDIO_REG_BANK_CL73_IEEEB1,
2015 MDIO_CL73_IEEEB1_AN_ADV2, 1989 MDIO_CL73_IEEEB1_AN_ADV2,
2016 &reg_val); 1990 &reg_val);
2017 if (phy->speed_cap_mask & 1991 if (phy->speed_cap_mask &
2018 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 1992 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2019 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 1993 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
@@ -2022,9 +1996,9 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2022 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 1996 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2023 1997
2024 CL45_WR_OVER_CL22(bp, phy, 1998 CL45_WR_OVER_CL22(bp, phy,
2025 MDIO_REG_BANK_CL73_IEEEB1, 1999 MDIO_REG_BANK_CL73_IEEEB1,
2026 MDIO_CL73_IEEEB1_AN_ADV2, 2000 MDIO_CL73_IEEEB1_AN_ADV2,
2027 reg_val); 2001 reg_val);
2028 2002
2029 /* CL73 Autoneg Enabled */ 2003 /* CL73 Autoneg Enabled */
2030 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 2004 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
@@ -2033,36 +2007,36 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2033 reg_val = 0; 2007 reg_val = 0;
2034 2008
2035 CL45_WR_OVER_CL22(bp, phy, 2009 CL45_WR_OVER_CL22(bp, phy,
2036 MDIO_REG_BANK_CL73_IEEEB0, 2010 MDIO_REG_BANK_CL73_IEEEB0,
2037 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 2011 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2038} 2012}
2039 2013
2040/* program SerDes, forced speed */ 2014/* program SerDes, forced speed */
2041static void bnx2x_program_serdes(struct bnx2x_phy *phy, 2015static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2042 struct link_params *params, 2016 struct link_params *params,
2043 struct link_vars *vars) 2017 struct link_vars *vars)
2044{ 2018{
2045 struct bnx2x *bp = params->bp; 2019 struct bnx2x *bp = params->bp;
2046 u16 reg_val; 2020 u16 reg_val;
2047 2021
2048 /* program duplex, disable autoneg and sgmii*/ 2022 /* program duplex, disable autoneg and sgmii*/
2049 CL45_RD_OVER_CL22(bp, phy, 2023 CL45_RD_OVER_CL22(bp, phy,
2050 MDIO_REG_BANK_COMBO_IEEE0, 2024 MDIO_REG_BANK_COMBO_IEEE0,
2051 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 2025 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2052 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 2026 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2053 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 2027 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2054 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 2028 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2055 if (phy->req_duplex == DUPLEX_FULL) 2029 if (phy->req_duplex == DUPLEX_FULL)
2056 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 2030 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2057 CL45_WR_OVER_CL22(bp, phy, 2031 CL45_WR_OVER_CL22(bp, phy,
2058 MDIO_REG_BANK_COMBO_IEEE0, 2032 MDIO_REG_BANK_COMBO_IEEE0,
2059 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 2033 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2060 2034
2061 /* program speed 2035 /* program speed
2062 - needed only if the speed is greater than 1G (2.5G or 10G) */ 2036 - needed only if the speed is greater than 1G (2.5G or 10G) */
2063 CL45_RD_OVER_CL22(bp, phy, 2037 CL45_RD_OVER_CL22(bp, phy,
2064 MDIO_REG_BANK_SERDES_DIGITAL, 2038 MDIO_REG_BANK_SERDES_DIGITAL,
2065 MDIO_SERDES_DIGITAL_MISC1, &reg_val); 2039 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2066 /* clearing the speed value before setting the right speed */ 2040 /* clearing the speed value before setting the right speed */
2067 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 2041 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2068 2042
@@ -2084,8 +2058,8 @@ static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2084 } 2058 }
2085 2059
2086 CL45_WR_OVER_CL22(bp, phy, 2060 CL45_WR_OVER_CL22(bp, phy,
2087 MDIO_REG_BANK_SERDES_DIGITAL, 2061 MDIO_REG_BANK_SERDES_DIGITAL,
2088 MDIO_SERDES_DIGITAL_MISC1, reg_val); 2062 MDIO_SERDES_DIGITAL_MISC1, reg_val);
2089 2063
2090} 2064}
2091 2065
@@ -2103,12 +2077,12 @@ static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2103 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2077 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2104 val |= MDIO_OVER_1G_UP1_10G; 2078 val |= MDIO_OVER_1G_UP1_10G;
2105 CL45_WR_OVER_CL22(bp, phy, 2079 CL45_WR_OVER_CL22(bp, phy,
2106 MDIO_REG_BANK_OVER_1G, 2080 MDIO_REG_BANK_OVER_1G,
2107 MDIO_OVER_1G_UP1, val); 2081 MDIO_OVER_1G_UP1, val);
2108 2082
2109 CL45_WR_OVER_CL22(bp, phy, 2083 CL45_WR_OVER_CL22(bp, phy,
2110 MDIO_REG_BANK_OVER_1G, 2084 MDIO_REG_BANK_OVER_1G,
2111 MDIO_OVER_1G_UP3, 0x400); 2085 MDIO_OVER_1G_UP3, 0x400);
2112} 2086}
2113 2087
2114static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 2088static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
@@ -2121,17 +2095,14 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2121 2095
2122 switch (phy->req_flow_ctrl) { 2096 switch (phy->req_flow_ctrl) {
2123 case BNX2X_FLOW_CTRL_AUTO: 2097 case BNX2X_FLOW_CTRL_AUTO:
2124 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { 2098 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2125 *ieee_fc |= 2099 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 2100 else
2127 } else {
2128 *ieee_fc |= 2101 *ieee_fc |=
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 2102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2130 }
2131 break; 2103 break;
2132 case BNX2X_FLOW_CTRL_TX: 2104 case BNX2X_FLOW_CTRL_TX:
2133 *ieee_fc |= 2105 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2134 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2135 break; 2106 break;
2136 2107
2137 case BNX2X_FLOW_CTRL_RX: 2108 case BNX2X_FLOW_CTRL_RX:
@@ -2149,23 +2120,23 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2149 2120
2150static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy, 2121static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2151 struct link_params *params, 2122 struct link_params *params,
2152 u16 ieee_fc) 2123 u16 ieee_fc)
2153{ 2124{
2154 struct bnx2x *bp = params->bp; 2125 struct bnx2x *bp = params->bp;
2155 u16 val; 2126 u16 val;
2156 /* for AN, we are always publishing full duplex */ 2127 /* for AN, we are always publishing full duplex */
2157 2128
2158 CL45_WR_OVER_CL22(bp, phy, 2129 CL45_WR_OVER_CL22(bp, phy,
2159 MDIO_REG_BANK_COMBO_IEEE0, 2130 MDIO_REG_BANK_COMBO_IEEE0,
2160 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 2131 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2161 CL45_RD_OVER_CL22(bp, phy, 2132 CL45_RD_OVER_CL22(bp, phy,
2162 MDIO_REG_BANK_CL73_IEEEB1, 2133 MDIO_REG_BANK_CL73_IEEEB1,
2163 MDIO_CL73_IEEEB1_AN_ADV1, &val); 2134 MDIO_CL73_IEEEB1_AN_ADV1, &val);
2164 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 2135 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2165 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 2136 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2166 CL45_WR_OVER_CL22(bp, phy, 2137 CL45_WR_OVER_CL22(bp, phy,
2167 MDIO_REG_BANK_CL73_IEEEB1, 2138 MDIO_REG_BANK_CL73_IEEEB1,
2168 MDIO_CL73_IEEEB1_AN_ADV1, val); 2139 MDIO_CL73_IEEEB1_AN_ADV1, val);
2169} 2140}
2170 2141
2171static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 2142static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
@@ -2180,37 +2151,37 @@ static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2180 2151
2181 if (enable_cl73) { 2152 if (enable_cl73) {
2182 CL45_RD_OVER_CL22(bp, phy, 2153 CL45_RD_OVER_CL22(bp, phy,
2183 MDIO_REG_BANK_CL73_IEEEB0, 2154 MDIO_REG_BANK_CL73_IEEEB0,
2184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 2155 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2185 &mii_control); 2156 &mii_control);
2186 2157
2187 CL45_WR_OVER_CL22(bp, phy, 2158 CL45_WR_OVER_CL22(bp, phy,
2188 MDIO_REG_BANK_CL73_IEEEB0, 2159 MDIO_REG_BANK_CL73_IEEEB0,
2189 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 2160 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2190 (mii_control | 2161 (mii_control |
2191 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 2162 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2192 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 2163 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2193 } else { 2164 } else {
2194 2165
2195 CL45_RD_OVER_CL22(bp, phy, 2166 CL45_RD_OVER_CL22(bp, phy,
2196 MDIO_REG_BANK_COMBO_IEEE0, 2167 MDIO_REG_BANK_COMBO_IEEE0,
2197 MDIO_COMBO_IEEE0_MII_CONTROL, 2168 MDIO_COMBO_IEEE0_MII_CONTROL,
2198 &mii_control); 2169 &mii_control);
2199 DP(NETIF_MSG_LINK, 2170 DP(NETIF_MSG_LINK,
2200 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 2171 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2201 mii_control); 2172 mii_control);
2202 CL45_WR_OVER_CL22(bp, phy, 2173 CL45_WR_OVER_CL22(bp, phy,
2203 MDIO_REG_BANK_COMBO_IEEE0, 2174 MDIO_REG_BANK_COMBO_IEEE0,
2204 MDIO_COMBO_IEEE0_MII_CONTROL, 2175 MDIO_COMBO_IEEE0_MII_CONTROL,
2205 (mii_control | 2176 (mii_control |
2206 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 2177 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2207 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 2178 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2208 } 2179 }
2209} 2180}
2210 2181
2211static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 2182static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2212 struct link_params *params, 2183 struct link_params *params,
2213 struct link_vars *vars) 2184 struct link_vars *vars)
2214{ 2185{
2215 struct bnx2x *bp = params->bp; 2186 struct bnx2x *bp = params->bp;
2216 u16 control1; 2187 u16 control1;
@@ -2218,18 +2189,18 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2218 /* in SGMII mode, the unicore is always slave */ 2189 /* in SGMII mode, the unicore is always slave */
2219 2190
2220 CL45_RD_OVER_CL22(bp, phy, 2191 CL45_RD_OVER_CL22(bp, phy,
2221 MDIO_REG_BANK_SERDES_DIGITAL, 2192 MDIO_REG_BANK_SERDES_DIGITAL,
2222 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 2193 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2223 &control1); 2194 &control1);
2224 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 2195 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2225 /* set sgmii mode (and not fiber) */ 2196 /* set sgmii mode (and not fiber) */
2226 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 2197 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2227 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 2198 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2228 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 2199 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2229 CL45_WR_OVER_CL22(bp, phy, 2200 CL45_WR_OVER_CL22(bp, phy,
2230 MDIO_REG_BANK_SERDES_DIGITAL, 2201 MDIO_REG_BANK_SERDES_DIGITAL,
2231 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 2202 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2232 control1); 2203 control1);
2233 2204
2234 /* if forced speed */ 2205 /* if forced speed */
2235 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 2206 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
@@ -2237,9 +2208,9 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2237 u16 mii_control; 2208 u16 mii_control;
2238 2209
2239 CL45_RD_OVER_CL22(bp, phy, 2210 CL45_RD_OVER_CL22(bp, phy,
2240 MDIO_REG_BANK_COMBO_IEEE0, 2211 MDIO_REG_BANK_COMBO_IEEE0,
2241 MDIO_COMBO_IEEE0_MII_CONTROL, 2212 MDIO_COMBO_IEEE0_MII_CONTROL,
2242 &mii_control); 2213 &mii_control);
2243 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 2214 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2244 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 2215 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2245 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 2216 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
@@ -2268,9 +2239,9 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2268 mii_control |= 2239 mii_control |=
2269 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 2240 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2270 CL45_WR_OVER_CL22(bp, phy, 2241 CL45_WR_OVER_CL22(bp, phy,
2271 MDIO_REG_BANK_COMBO_IEEE0, 2242 MDIO_REG_BANK_COMBO_IEEE0,
2272 MDIO_COMBO_IEEE0_MII_CONTROL, 2243 MDIO_COMBO_IEEE0_MII_CONTROL,
2273 mii_control); 2244 mii_control);
2274 2245
2275 } else { /* AN mode */ 2246 } else { /* AN mode */
2276 /* enable and restart AN */ 2247 /* enable and restart AN */
@@ -2285,19 +2256,19 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2285 2256
2286static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 2257static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2287{ /* LD LP */ 2258{ /* LD LP */
2288 switch (pause_result) { /* ASYM P ASYM P */ 2259 switch (pause_result) { /* ASYM P ASYM P */
2289 case 0xb: /* 1 0 1 1 */ 2260 case 0xb: /* 1 0 1 1 */
2290 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 2261 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2291 break; 2262 break;
2292 2263
2293 case 0xe: /* 1 1 1 0 */ 2264 case 0xe: /* 1 1 1 0 */
2294 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 2265 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2295 break; 2266 break;
2296 2267
2297 case 0x5: /* 0 1 0 1 */ 2268 case 0x5: /* 0 1 0 1 */
2298 case 0x7: /* 0 1 1 1 */ 2269 case 0x7: /* 0 1 1 1 */
2299 case 0xd: /* 1 1 0 1 */ 2270 case 0xd: /* 1 1 0 1 */
2300 case 0xf: /* 1 1 1 1 */ 2271 case 0xf: /* 1 1 1 1 */
2301 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 2272 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2302 break; 2273 break;
2303 2274
@@ -2318,13 +2289,13 @@ static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2318 if (phy->req_line_speed != SPEED_AUTO_NEG) 2289 if (phy->req_line_speed != SPEED_AUTO_NEG)
2319 return 0; 2290 return 0;
2320 CL45_RD_OVER_CL22(bp, phy, 2291 CL45_RD_OVER_CL22(bp, phy,
2321 MDIO_REG_BANK_SERDES_DIGITAL, 2292 MDIO_REG_BANK_SERDES_DIGITAL,
2322 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 2293 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2323 &status2_1000x); 2294 &status2_1000x);
2324 CL45_RD_OVER_CL22(bp, phy, 2295 CL45_RD_OVER_CL22(bp, phy,
2325 MDIO_REG_BANK_SERDES_DIGITAL, 2296 MDIO_REG_BANK_SERDES_DIGITAL,
2326 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 2297 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2327 &status2_1000x); 2298 &status2_1000x);
2328 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 2299 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2329 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 2300 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2330 params->port); 2301 params->port);
@@ -2332,9 +2303,9 @@ static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2332 } 2303 }
2333 2304
2334 CL45_RD_OVER_CL22(bp, phy, 2305 CL45_RD_OVER_CL22(bp, phy,
2335 MDIO_REG_BANK_10G_PARALLEL_DETECT, 2306 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2336 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 2307 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2337 &pd_10g); 2308 &pd_10g);
2338 2309
2339 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 2310 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2340 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 2311 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
@@ -2374,13 +2345,13 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2374 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 2345 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2375 2346
2376 CL45_RD_OVER_CL22(bp, phy, 2347 CL45_RD_OVER_CL22(bp, phy,
2377 MDIO_REG_BANK_CL73_IEEEB1, 2348 MDIO_REG_BANK_CL73_IEEEB1,
2378 MDIO_CL73_IEEEB1_AN_ADV1, 2349 MDIO_CL73_IEEEB1_AN_ADV1,
2379 &ld_pause); 2350 &ld_pause);
2380 CL45_RD_OVER_CL22(bp, phy, 2351 CL45_RD_OVER_CL22(bp, phy,
2381 MDIO_REG_BANK_CL73_IEEEB1, 2352 MDIO_REG_BANK_CL73_IEEEB1,
2382 MDIO_CL73_IEEEB1_AN_LP_ADV1, 2353 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2383 &lp_pause); 2354 &lp_pause);
2384 pause_result = (ld_pause & 2355 pause_result = (ld_pause &
2385 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) 2356 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2386 >> 8; 2357 >> 8;
@@ -2391,17 +2362,17 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2391 pause_result); 2362 pause_result);
2392 } else { 2363 } else {
2393 CL45_RD_OVER_CL22(bp, phy, 2364 CL45_RD_OVER_CL22(bp, phy,
2394 MDIO_REG_BANK_COMBO_IEEE0, 2365 MDIO_REG_BANK_COMBO_IEEE0,
2395 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 2366 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2396 &ld_pause); 2367 &ld_pause);
2397 CL45_RD_OVER_CL22(bp, phy, 2368 CL45_RD_OVER_CL22(bp, phy,
2398 MDIO_REG_BANK_COMBO_IEEE0, 2369 MDIO_REG_BANK_COMBO_IEEE0,
2399 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 2370 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2400 &lp_pause); 2371 &lp_pause);
2401 pause_result = (ld_pause & 2372 pause_result = (ld_pause &
2402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 2373 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2403 pause_result |= (lp_pause & 2374 pause_result |= (lp_pause &
2404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 2375 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2405 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", 2376 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2406 pause_result); 2377 pause_result);
2407 } 2378 }
@@ -2418,24 +2389,24 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2418 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 2389 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2419 /* Step 1: Make sure signal is detected */ 2390 /* Step 1: Make sure signal is detected */
2420 CL45_RD_OVER_CL22(bp, phy, 2391 CL45_RD_OVER_CL22(bp, phy,
2421 MDIO_REG_BANK_RX0, 2392 MDIO_REG_BANK_RX0,
2422 MDIO_RX0_RX_STATUS, 2393 MDIO_RX0_RX_STATUS,
2423 &rx_status); 2394 &rx_status);
2424 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 2395 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2425 (MDIO_RX0_RX_STATUS_SIGDET)) { 2396 (MDIO_RX0_RX_STATUS_SIGDET)) {
2426 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 2397 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2427 "rx_status(0x80b0) = 0x%x\n", rx_status); 2398 "rx_status(0x80b0) = 0x%x\n", rx_status);
2428 CL45_WR_OVER_CL22(bp, phy, 2399 CL45_WR_OVER_CL22(bp, phy,
2429 MDIO_REG_BANK_CL73_IEEEB0, 2400 MDIO_REG_BANK_CL73_IEEEB0,
2430 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 2401 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2431 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 2402 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2432 return; 2403 return;
2433 } 2404 }
2434 /* Step 2: Check CL73 state machine */ 2405 /* Step 2: Check CL73 state machine */
2435 CL45_RD_OVER_CL22(bp, phy, 2406 CL45_RD_OVER_CL22(bp, phy,
2436 MDIO_REG_BANK_CL73_USERB0, 2407 MDIO_REG_BANK_CL73_USERB0,
2437 MDIO_CL73_USERB0_CL73_USTAT1, 2408 MDIO_CL73_USERB0_CL73_USTAT1,
2438 &ustat_val); 2409 &ustat_val);
2439 if ((ustat_val & 2410 if ((ustat_val &
2440 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 2411 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2441 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 2412 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
@@ -2448,9 +2419,9 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2448 /* Step 3: Check CL37 Message Pages received to indicate LP 2419 /* Step 3: Check CL37 Message Pages received to indicate LP
2449 supports only CL37 */ 2420 supports only CL37 */
2450 CL45_RD_OVER_CL22(bp, phy, 2421 CL45_RD_OVER_CL22(bp, phy,
2451 MDIO_REG_BANK_REMOTE_PHY, 2422 MDIO_REG_BANK_REMOTE_PHY,
2452 MDIO_REMOTE_PHY_MISC_RX_STATUS, 2423 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2453 &cl37_fsm_recieved); 2424 &cl37_fsm_recieved);
2454 if ((cl37_fsm_recieved & 2425 if ((cl37_fsm_recieved &
2455 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 2426 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2456 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 2427 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
@@ -2466,9 +2437,9 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2466 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */ 2437 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
2467 /* Disable CL73 */ 2438 /* Disable CL73 */
2468 CL45_WR_OVER_CL22(bp, phy, 2439 CL45_WR_OVER_CL22(bp, phy,
2469 MDIO_REG_BANK_CL73_IEEEB0, 2440 MDIO_REG_BANK_CL73_IEEEB0,
2470 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 2441 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2471 0); 2442 0);
2472 /* Restart CL37 autoneg */ 2443 /* Restart CL37 autoneg */
2473 bnx2x_restart_autoneg(phy, params, 0); 2444 bnx2x_restart_autoneg(phy, params, 0);
2474 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 2445 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
@@ -2493,14 +2464,14 @@ static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2493 struct link_vars *vars) 2464 struct link_vars *vars)
2494{ 2465{
2495 struct bnx2x *bp = params->bp; 2466 struct bnx2x *bp = params->bp;
2496 u16 new_line_speed , gp_status; 2467 u16 new_line_speed, gp_status;
2497 u8 rc = 0; 2468 u8 rc = 0;
2498 2469
2499 /* Read gp_status */ 2470 /* Read gp_status */
2500 CL45_RD_OVER_CL22(bp, phy, 2471 CL45_RD_OVER_CL22(bp, phy,
2501 MDIO_REG_BANK_GP_STATUS, 2472 MDIO_REG_BANK_GP_STATUS,
2502 MDIO_GP_STATUS_TOP_AN_STATUS1, 2473 MDIO_GP_STATUS_TOP_AN_STATUS1,
2503 &gp_status); 2474 &gp_status);
2504 2475
2505 if (phy->req_line_speed == SPEED_AUTO_NEG) 2476 if (phy->req_line_speed == SPEED_AUTO_NEG)
2506 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 2477 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
@@ -2638,8 +2609,8 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2638 2609
2639 /* read precomp */ 2610 /* read precomp */
2640 CL45_RD_OVER_CL22(bp, phy, 2611 CL45_RD_OVER_CL22(bp, phy,
2641 MDIO_REG_BANK_OVER_1G, 2612 MDIO_REG_BANK_OVER_1G,
2642 MDIO_OVER_1G_LP_UP2, &lp_up2); 2613 MDIO_OVER_1G_LP_UP2, &lp_up2);
2643 2614
2644 /* bits [10:7] at lp_up2, positioned at [15:12] */ 2615 /* bits [10:7] at lp_up2, positioned at [15:12] */
2645 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 2616 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
@@ -2652,8 +2623,8 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2652 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 2623 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2653 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 2624 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2654 CL45_RD_OVER_CL22(bp, phy, 2625 CL45_RD_OVER_CL22(bp, phy,
2655 bank, 2626 bank,
2656 MDIO_TX0_TX_DRIVER, &tx_driver); 2627 MDIO_TX0_TX_DRIVER, &tx_driver);
2657 2628
2658 /* replace tx_driver bits [15:12] */ 2629 /* replace tx_driver bits [15:12] */
2659 if (lp_up2 != 2630 if (lp_up2 !=
@@ -2661,8 +2632,8 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2661 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 2632 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2662 tx_driver |= lp_up2; 2633 tx_driver |= lp_up2;
2663 CL45_WR_OVER_CL22(bp, phy, 2634 CL45_WR_OVER_CL22(bp, phy,
2664 bank, 2635 bank,
2665 MDIO_TX0_TX_DRIVER, tx_driver); 2636 MDIO_TX0_TX_DRIVER, tx_driver);
2666 } 2637 }
2667 } 2638 }
2668} 2639}
@@ -2676,10 +2647,10 @@ static u8 bnx2x_emac_program(struct link_params *params,
2676 2647
2677 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 2648 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2678 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 2649 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2679 EMAC_REG_EMAC_MODE, 2650 EMAC_REG_EMAC_MODE,
2680 (EMAC_MODE_25G_MODE | 2651 (EMAC_MODE_25G_MODE |
2681 EMAC_MODE_PORT_MII_10M | 2652 EMAC_MODE_PORT_MII_10M |
2682 EMAC_MODE_HALF_DUPLEX)); 2653 EMAC_MODE_HALF_DUPLEX));
2683 switch (vars->line_speed) { 2654 switch (vars->line_speed) {
2684 case SPEED_10: 2655 case SPEED_10:
2685 mode |= EMAC_MODE_PORT_MII_10M; 2656 mode |= EMAC_MODE_PORT_MII_10M;
@@ -2707,8 +2678,8 @@ static u8 bnx2x_emac_program(struct link_params *params,
2707 if (vars->duplex == DUPLEX_HALF) 2678 if (vars->duplex == DUPLEX_HALF)
2708 mode |= EMAC_MODE_HALF_DUPLEX; 2679 mode |= EMAC_MODE_HALF_DUPLEX;
2709 bnx2x_bits_en(bp, 2680 bnx2x_bits_en(bp,
2710 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 2681 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2711 mode); 2682 mode);
2712 2683
2713 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 2684 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2714 return 0; 2685 return 0;
@@ -2754,7 +2725,7 @@ static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2754 /* forced speed requested? */ 2725 /* forced speed requested? */
2755 if (vars->line_speed != SPEED_AUTO_NEG || 2726 if (vars->line_speed != SPEED_AUTO_NEG ||
2756 (SINGLE_MEDIA_DIRECT(params) && 2727 (SINGLE_MEDIA_DIRECT(params) &&
2757 params->loopback_mode == LOOPBACK_EXT)) { 2728 params->loopback_mode == LOOPBACK_EXT)) {
2758 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 2729 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2759 2730
2760 /* disable autoneg */ 2731 /* disable autoneg */
@@ -2771,7 +2742,7 @@ static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2771 2742
2772 /* program duplex & pause advertisement (for aneg) */ 2743 /* program duplex & pause advertisement (for aneg) */
2773 bnx2x_set_ieee_aneg_advertisment(phy, params, 2744 bnx2x_set_ieee_aneg_advertisment(phy, params,
2774 vars->ieee_fc); 2745 vars->ieee_fc);
2775 2746
2776 /* enable autoneg */ 2747 /* enable autoneg */
2777 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 2748 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
@@ -2933,13 +2904,13 @@ static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2933 2904
2934 /* For all latched-signal=up : Re-Arm Latch signals */ 2905 /* For all latched-signal=up : Re-Arm Latch signals */
2935 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 2906 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2936 (latch_status & 0xfffe) | (latch_status & 1)); 2907 (latch_status & 0xfffe) | (latch_status & 1));
2937 } 2908 }
2938 /* For all latched-signal=up,Write original_signal to status */ 2909 /* For all latched-signal=up,Write original_signal to status */
2939} 2910}
2940 2911
2941static void bnx2x_link_int_ack(struct link_params *params, 2912static void bnx2x_link_int_ack(struct link_params *params,
2942 struct link_vars *vars, u8 is_10g) 2913 struct link_vars *vars, u8 is_10g)
2943{ 2914{
2944 struct bnx2x *bp = params->bp; 2915 struct bnx2x *bp = params->bp;
2945 u8 port = params->port; 2916 u8 port = params->port;
@@ -2947,9 +2918,9 @@ static void bnx2x_link_int_ack(struct link_params *params,
2947 /* first reset all status 2918 /* first reset all status
2948 * we assume only one line will be change at a time */ 2919 * we assume only one line will be change at a time */
2949 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 2920 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950 (NIG_STATUS_XGXS0_LINK10G | 2921 (NIG_STATUS_XGXS0_LINK10G |
2951 NIG_STATUS_XGXS0_LINK_STATUS | 2922 NIG_STATUS_XGXS0_LINK_STATUS |
2952 NIG_STATUS_SERDES0_LINK_STATUS)); 2923 NIG_STATUS_SERDES0_LINK_STATUS));
2953 if (vars->phy_link_up) { 2924 if (vars->phy_link_up) {
2954 if (is_10g) { 2925 if (is_10g) {
2955 /* Disable the 10G link interrupt 2926 /* Disable the 10G link interrupt
@@ -3059,8 +3030,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3059 } 3030 }
3060 if ((params->num_phys == MAX_PHYS) && 3031 if ((params->num_phys == MAX_PHYS) &&
3061 (params->phy[EXT_PHY2].ver_addr != 0)) { 3032 (params->phy[EXT_PHY2].ver_addr != 0)) {
3062 spirom_ver = REG_RD(bp, 3033 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3063 params->phy[EXT_PHY2].ver_addr);
3064 if (params->phy[EXT_PHY2].format_fw_ver) { 3034 if (params->phy[EXT_PHY2].format_fw_ver) {
3065 *ver_p = '/'; 3035 *ver_p = '/';
3066 ver_p++; 3036 ver_p++;
@@ -3089,29 +3059,27 @@ static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3089 3059
3090 /* change the uni_phy_addr in the nig */ 3060 /* change the uni_phy_addr in the nig */
3091 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 3061 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3092 port*0x18)); 3062 port*0x18));
3093 3063
3094 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5); 3064 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3095 3065
3096 bnx2x_cl45_write(bp, phy, 3066 bnx2x_cl45_write(bp, phy,
3097 5, 3067 5,
3098 (MDIO_REG_BANK_AER_BLOCK + 3068 (MDIO_REG_BANK_AER_BLOCK +
3099 (MDIO_AER_BLOCK_AER_REG & 0xf)), 3069 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3100 0x2800); 3070 0x2800);
3101 3071
3102 bnx2x_cl45_write(bp, phy, 3072 bnx2x_cl45_write(bp, phy,
3103 5, 3073 5,
3104 (MDIO_REG_BANK_CL73_IEEEB0 + 3074 (MDIO_REG_BANK_CL73_IEEEB0 +
3105 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 3075 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3106 0x6041); 3076 0x6041);
3107 msleep(200); 3077 msleep(200);
3108 /* set aer mmd back */ 3078 /* set aer mmd back */
3109 bnx2x_set_aer_mmd_xgxs(params, phy); 3079 bnx2x_set_aer_mmd_xgxs(params, phy);
3110 3080
3111 /* and md_devad */ 3081 /* and md_devad */
3112 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 3082 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3113 md_devad);
3114
3115 } else { 3083 } else {
3116 u16 mii_ctrl; 3084 u16 mii_ctrl;
3117 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 3085 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
@@ -3152,7 +3120,7 @@ u8 bnx2x_set_led(struct link_params *params,
3152 case LED_MODE_OFF: 3120 case LED_MODE_OFF:
3153 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 3121 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 3122 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155 SHARED_HW_CFG_LED_MAC1); 3123 SHARED_HW_CFG_LED_MAC1);
3156 3124
3157 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 3125 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3158 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); 3126 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
@@ -3190,20 +3158,17 @@ u8 bnx2x_set_led(struct link_params *params,
3190 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 3158 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3191 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 3159 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3192 } else { 3160 } else {
3193 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 3161 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3194 hw_led_mode);
3195 } 3162 }
3196 3163
3197 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + 3164 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3198 port*4, 0);
3199 /* Set blinking rate to ~15.9Hz */ 3165 /* Set blinking rate to ~15.9Hz */
3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 3166 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3201 LED_BLINK_RATE_VAL); 3167 LED_BLINK_RATE_VAL);
3202 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 3168 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3203 port*4, 1); 3169 port*4, 1);
3204 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 3170 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3205 EMAC_WR(bp, EMAC_REG_EMAC_LED, 3171 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3206 (tmp & (~EMAC_LED_OVERRIDE)));
3207 3172
3208 if (CHIP_IS_E1(bp) && 3173 if (CHIP_IS_E1(bp) &&
3209 ((speed == SPEED_2500) || 3174 ((speed == SPEED_2500) ||
@@ -3213,11 +3178,11 @@ u8 bnx2x_set_led(struct link_params *params,
3213 /* On Everest 1 Ax chip versions for speeds less than 3178 /* On Everest 1 Ax chip versions for speeds less than
3214 10G LED scheme is different */ 3179 10G LED scheme is different */
3215 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 3180 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3216 + port*4, 1); 3181 + port*4, 1);
3217 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 3182 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3218 port*4, 0); 3183 port*4, 0);
3219 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 3184 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3220 port*4, 1); 3185 port*4, 1);
3221 } 3186 }
3222 break; 3187 break;
3223 3188
@@ -3244,9 +3209,9 @@ u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3244 struct link_vars temp_vars; 3209 struct link_vars temp_vars;
3245 3210
3246 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY], 3211 CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
3247 MDIO_REG_BANK_GP_STATUS, 3212 MDIO_REG_BANK_GP_STATUS,
3248 MDIO_GP_STATUS_TOP_AN_STATUS1, 3213 MDIO_GP_STATUS_TOP_AN_STATUS1,
3249 &gp_status); 3214 &gp_status);
3250 /* link is up only if both local phy and external phy are up */ 3215 /* link is up only if both local phy and external phy are up */
3251 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 3216 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3252 return -ESRCH; 3217 return -ESRCH;
@@ -3358,9 +3323,8 @@ static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3358 struct link_params *params) 3323 struct link_params *params)
3359{ 3324{
3360 /* reset the SerDes/XGXS */ 3325 /* reset the SerDes/XGXS */
3361 REG_WR(params->bp, GRCBASE_MISC + 3326 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3362 MISC_REGISTERS_RESET_REG_3_CLEAR, 3327 (0x1ff << (params->port*16)));
3363 (0x1ff << (params->port*16)));
3364} 3328}
3365 3329
3366static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 3330static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
@@ -3374,11 +3338,11 @@ static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3374 else 3338 else
3375 gpio_port = params->port; 3339 gpio_port = params->port;
3376 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 3340 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3377 MISC_REGISTERS_GPIO_OUTPUT_LOW, 3341 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3378 gpio_port); 3342 gpio_port);
3379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 3343 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3380 MISC_REGISTERS_GPIO_OUTPUT_LOW, 3344 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3381 gpio_port); 3345 gpio_port);
3382 DP(NETIF_MSG_LINK, "reset external PHY\n"); 3346 DP(NETIF_MSG_LINK, "reset external PHY\n");
3383} 3347}
3384 3348
@@ -3409,9 +3373,8 @@ static u8 bnx2x_update_link_down(struct link_params *params,
3409 3373
3410 /* reset BigMac */ 3374 /* reset BigMac */
3411 bnx2x_bmac_rx_disable(bp, params->port); 3375 bnx2x_bmac_rx_disable(bp, params->port);
3412 REG_WR(bp, GRCBASE_MISC + 3376 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3413 MISC_REGISTERS_RESET_REG_2_CLEAR, 3377 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3414 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3415 return 0; 3378 return 0;
3416} 3379}
3417 3380
@@ -3501,12 +3464,11 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3501 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 3464 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3502 3465
3503 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 3466 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3504 port*0x18) > 0); 3467 port*0x18) > 0);
3505 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 3468 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3506 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 3469 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3507 is_mi_int, 3470 is_mi_int,
3508 REG_RD(bp, 3471 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3509 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3510 3472
3511 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 3473 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3512 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 3474 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
@@ -3658,8 +3620,8 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3658 ext_phy_line_speed); 3620 ext_phy_line_speed);
3659 vars->phy_link_up = 0; 3621 vars->phy_link_up = 0;
3660 } else if (prev_line_speed != vars->line_speed) { 3622 } else if (prev_line_speed != vars->line_speed) {
3661 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE 3623 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3662 + params->port*4, 0); 3624 0);
3663 msleep(1); 3625 msleep(1);
3664 } 3626 }
3665 } 3627 }
@@ -3724,10 +3686,10 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3724void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 3686void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3725{ 3687{
3726 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 3688 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3727 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 3689 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3728 msleep(1); 3690 msleep(1);
3729 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 3691 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3730 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 3692 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3731} 3693}
3732 3694
3733static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 3695static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
@@ -3747,9 +3709,9 @@ static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3747 u16 fw_ver1, fw_ver2; 3709 u16 fw_ver1, fw_ver2;
3748 3710
3749 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 3711 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3750 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 3712 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3751 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 3713 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3752 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 3714 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3753 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 3715 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3754 phy->ver_addr); 3716 phy->ver_addr);
3755} 3717}
@@ -3770,7 +3732,7 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
3770 if ((vars->ieee_fc & 3732 if ((vars->ieee_fc &
3771 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3733 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3772 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3734 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3773 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3735 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3774 } 3736 }
3775 if ((vars->ieee_fc & 3737 if ((vars->ieee_fc &
3776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3738 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
@@ -3801,11 +3763,11 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3801 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3763 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3802 ret = 1; 3764 ret = 1;
3803 bnx2x_cl45_read(bp, phy, 3765 bnx2x_cl45_read(bp, phy,
3804 MDIO_AN_DEVAD, 3766 MDIO_AN_DEVAD,
3805 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3767 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3806 bnx2x_cl45_read(bp, phy, 3768 bnx2x_cl45_read(bp, phy,
3807 MDIO_AN_DEVAD, 3769 MDIO_AN_DEVAD,
3808 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3770 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3809 pause_result = (ld_pause & 3771 pause_result = (ld_pause &
3810 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3772 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3811 pause_result |= (lp_pause & 3773 pause_result |= (lp_pause &
@@ -3881,31 +3843,31 @@ static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3881 /* Boot port from external ROM */ 3843 /* Boot port from external ROM */
3882 /* EDC grst */ 3844 /* EDC grst */
3883 bnx2x_cl45_write(bp, phy, 3845 bnx2x_cl45_write(bp, phy,
3884 MDIO_PMA_DEVAD, 3846 MDIO_PMA_DEVAD,
3885 MDIO_PMA_REG_GEN_CTRL, 3847 MDIO_PMA_REG_GEN_CTRL,
3886 0x0001); 3848 0x0001);
3887 3849
3888 /* ucode reboot and rst */ 3850 /* ucode reboot and rst */
3889 bnx2x_cl45_write(bp, phy, 3851 bnx2x_cl45_write(bp, phy,
3890 MDIO_PMA_DEVAD, 3852 MDIO_PMA_DEVAD,
3891 MDIO_PMA_REG_GEN_CTRL, 3853 MDIO_PMA_REG_GEN_CTRL,
3892 0x008c); 3854 0x008c);
3893 3855
3894 bnx2x_cl45_write(bp, phy, 3856 bnx2x_cl45_write(bp, phy,
3895 MDIO_PMA_DEVAD, 3857 MDIO_PMA_DEVAD,
3896 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 3858 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3897 3859
3898 /* Reset internal microprocessor */ 3860 /* Reset internal microprocessor */
3899 bnx2x_cl45_write(bp, phy, 3861 bnx2x_cl45_write(bp, phy,
3900 MDIO_PMA_DEVAD, 3862 MDIO_PMA_DEVAD,
3901 MDIO_PMA_REG_GEN_CTRL, 3863 MDIO_PMA_REG_GEN_CTRL,
3902 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 3864 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3903 3865
3904 /* Release srst bit */ 3866 /* Release srst bit */
3905 bnx2x_cl45_write(bp, phy, 3867 bnx2x_cl45_write(bp, phy,
3906 MDIO_PMA_DEVAD, 3868 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_GEN_CTRL, 3869 MDIO_PMA_REG_GEN_CTRL,
3908 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 3870 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3909 3871
3910 /* Delay 100ms per the PHY specifications */ 3872 /* Delay 100ms per the PHY specifications */
3911 msleep(100); 3873 msleep(100);
@@ -3936,8 +3898,8 @@ static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3936 3898
3937 /* Clear ser_boot_ctl bit */ 3899 /* Clear ser_boot_ctl bit */
3938 bnx2x_cl45_write(bp, phy, 3900 bnx2x_cl45_write(bp, phy,
3939 MDIO_PMA_DEVAD, 3901 MDIO_PMA_DEVAD,
3940 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 3902 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3941 bnx2x_save_bcm_spirom_ver(bp, phy, port); 3903 bnx2x_save_bcm_spirom_ver(bp, phy, port);
3942 3904
3943 DP(NETIF_MSG_LINK, 3905 DP(NETIF_MSG_LINK,
@@ -3958,8 +3920,8 @@ static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3958 3920
3959 /* Read 8073 HW revision*/ 3921 /* Read 8073 HW revision*/
3960 bnx2x_cl45_read(bp, phy, 3922 bnx2x_cl45_read(bp, phy,
3961 MDIO_PMA_DEVAD, 3923 MDIO_PMA_DEVAD,
3962 MDIO_PMA_REG_8073_CHIP_REV, &val); 3924 MDIO_PMA_REG_8073_CHIP_REV, &val);
3963 3925
3964 if (val != 1) { 3926 if (val != 1) {
3965 /* No need to workaround in 8073 A1 */ 3927 /* No need to workaround in 8073 A1 */
@@ -3967,8 +3929,8 @@ static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3967 } 3929 }
3968 3930
3969 bnx2x_cl45_read(bp, phy, 3931 bnx2x_cl45_read(bp, phy,
3970 MDIO_PMA_DEVAD, 3932 MDIO_PMA_DEVAD,
3971 MDIO_PMA_REG_ROM_VER2, &val); 3933 MDIO_PMA_REG_ROM_VER2, &val);
3972 3934
3973 /* SNR should be applied only for version 0x102 */ 3935 /* SNR should be applied only for version 0x102 */
3974 if (val != 0x102) 3936 if (val != 0x102)
@@ -3982,8 +3944,8 @@ static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3982 u16 val, cnt, cnt1 ; 3944 u16 val, cnt, cnt1 ;
3983 3945
3984 bnx2x_cl45_read(bp, phy, 3946 bnx2x_cl45_read(bp, phy,
3985 MDIO_PMA_DEVAD, 3947 MDIO_PMA_DEVAD,
3986 MDIO_PMA_REG_8073_CHIP_REV, &val); 3948 MDIO_PMA_REG_8073_CHIP_REV, &val);
3987 3949
3988 if (val > 0) { 3950 if (val > 0) {
3989 /* No need to workaround in 8073 A1 */ 3951 /* No need to workaround in 8073 A1 */
@@ -3996,9 +3958,9 @@ static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3996 3958
3997 for (cnt = 0; cnt < 1000; cnt++) { 3959 for (cnt = 0; cnt < 1000; cnt++) {
3998 bnx2x_cl45_read(bp, phy, 3960 bnx2x_cl45_read(bp, phy,
3999 MDIO_PMA_DEVAD, 3961 MDIO_PMA_DEVAD,
4000 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 3962 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4001 &val); 3963 &val);
4002 /* If bit [14] = 0 or bit [13] = 0, continue on with 3964 /* If bit [14] = 0 or bit [13] = 0, continue on with
4003 system initialization (XAUI work-around not required, 3965 system initialization (XAUI work-around not required,
4004 as these bits indicate 2.5G or 1G link up). */ 3966 as these bits indicate 2.5G or 1G link up). */
@@ -4093,10 +4055,10 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4093 gpio_port = params->port; 4055 gpio_port = params->port;
4094 /* Restore normal power mode*/ 4056 /* Restore normal power mode*/
4095 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4057 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4096 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 4058 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4097 4059
4098 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 4060 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4099 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 4061 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4100 4062
4101 /* enable LASI */ 4063 /* enable LASI */
4102 bnx2x_cl45_write(bp, phy, 4064 bnx2x_cl45_write(bp, phy,
@@ -4381,8 +4343,8 @@ static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4381 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 4343 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4382 gpio_port); 4344 gpio_port);
4383 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4345 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4384 MISC_REGISTERS_GPIO_OUTPUT_LOW, 4346 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4385 gpio_port); 4347 gpio_port);
4386} 4348}
4387 4349
4388/******************************************************************/ 4350/******************************************************************/
@@ -4396,7 +4358,7 @@ static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4396 DP(NETIF_MSG_LINK, "init 8705\n"); 4358 DP(NETIF_MSG_LINK, "init 8705\n");
4397 /* Restore normal power mode*/ 4359 /* Restore normal power mode*/
4398 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4360 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4399 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 4361 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4400 /* HW reset */ 4362 /* HW reset */
4401 bnx2x_ext_phy_hw_reset(bp, params->port); 4363 bnx2x_ext_phy_hw_reset(bp, params->port);
4402 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 4364 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -4479,7 +4441,7 @@ static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
4479 4441
4480static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 4442static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4481 struct link_params *params, 4443 struct link_params *params,
4482 u16 addr, u8 byte_cnt, u8 *o_buf) 4444 u16 addr, u8 byte_cnt, u8 *o_buf)
4483{ 4445{
4484 struct bnx2x *bp = params->bp; 4446 struct bnx2x *bp = params->bp;
4485 u16 val = 0; 4447 u16 val = 0;
@@ -4492,23 +4454,23 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4492 /* Set the read command byte count */ 4454 /* Set the read command byte count */
4493 bnx2x_cl45_write(bp, phy, 4455 bnx2x_cl45_write(bp, phy,
4494 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 4456 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4495 (byte_cnt | 0xa000)); 4457 (byte_cnt | 0xa000));
4496 4458
4497 /* Set the read command address */ 4459 /* Set the read command address */
4498 bnx2x_cl45_write(bp, phy, 4460 bnx2x_cl45_write(bp, phy,
4499 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 4461 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4500 addr); 4462 addr);
4501 4463
4502 /* Activate read command */ 4464 /* Activate read command */
4503 bnx2x_cl45_write(bp, phy, 4465 bnx2x_cl45_write(bp, phy,
4504 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 4466 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4505 0x2c0f); 4467 0x2c0f);
4506 4468
4507 /* Wait up to 500us for command complete status */ 4469 /* Wait up to 500us for command complete status */
4508 for (i = 0; i < 100; i++) { 4470 for (i = 0; i < 100; i++) {
4509 bnx2x_cl45_read(bp, phy, 4471 bnx2x_cl45_read(bp, phy,
4510 MDIO_PMA_DEVAD, 4472 MDIO_PMA_DEVAD,
4511 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 4473 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4512 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 4474 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4513 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 4475 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4514 break; 4476 break;
@@ -4526,15 +4488,15 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4526 /* Read the buffer */ 4488 /* Read the buffer */
4527 for (i = 0; i < byte_cnt; i++) { 4489 for (i = 0; i < byte_cnt; i++) {
4528 bnx2x_cl45_read(bp, phy, 4490 bnx2x_cl45_read(bp, phy,
4529 MDIO_PMA_DEVAD, 4491 MDIO_PMA_DEVAD,
4530 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 4492 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4531 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 4493 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4532 } 4494 }
4533 4495
4534 for (i = 0; i < 100; i++) { 4496 for (i = 0; i < 100; i++) {
4535 bnx2x_cl45_read(bp, phy, 4497 bnx2x_cl45_read(bp, phy,
4536 MDIO_PMA_DEVAD, 4498 MDIO_PMA_DEVAD,
4537 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 4499 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4538 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 4500 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4539 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 4501 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4540 return 0; 4502 return 0;
@@ -4545,7 +4507,7 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4545 4507
4546static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 4508static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4547 struct link_params *params, 4509 struct link_params *params,
4548 u16 addr, u8 byte_cnt, u8 *o_buf) 4510 u16 addr, u8 byte_cnt, u8 *o_buf)
4549{ 4511{
4550 struct bnx2x *bp = params->bp; 4512 struct bnx2x *bp = params->bp;
4551 u16 val, i; 4513 u16 val, i;
@@ -4558,32 +4520,32 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4558 4520
4559 /* Need to read from 1.8000 to clear it */ 4521 /* Need to read from 1.8000 to clear it */
4560 bnx2x_cl45_read(bp, phy, 4522 bnx2x_cl45_read(bp, phy,
4561 MDIO_PMA_DEVAD, 4523 MDIO_PMA_DEVAD,
4562 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 4524 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4563 &val); 4525 &val);
4564 4526
4565 /* Set the read command byte count */ 4527 /* Set the read command byte count */
4566 bnx2x_cl45_write(bp, phy, 4528 bnx2x_cl45_write(bp, phy,
4567 MDIO_PMA_DEVAD, 4529 MDIO_PMA_DEVAD,
4568 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 4530 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4569 ((byte_cnt < 2) ? 2 : byte_cnt)); 4531 ((byte_cnt < 2) ? 2 : byte_cnt));
4570 4532
4571 /* Set the read command address */ 4533 /* Set the read command address */
4572 bnx2x_cl45_write(bp, phy, 4534 bnx2x_cl45_write(bp, phy,
4573 MDIO_PMA_DEVAD, 4535 MDIO_PMA_DEVAD,
4574 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 4536 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4575 addr); 4537 addr);
4576 /* Set the destination address */ 4538 /* Set the destination address */
4577 bnx2x_cl45_write(bp, phy, 4539 bnx2x_cl45_write(bp, phy,
4578 MDIO_PMA_DEVAD, 4540 MDIO_PMA_DEVAD,
4579 0x8004, 4541 0x8004,
4580 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 4542 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4581 4543
4582 /* Activate read command */ 4544 /* Activate read command */
4583 bnx2x_cl45_write(bp, phy, 4545 bnx2x_cl45_write(bp, phy,
4584 MDIO_PMA_DEVAD, 4546 MDIO_PMA_DEVAD,
4585 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 4547 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4586 0x8002); 4548 0x8002);
4587 /* Wait appropriate time for two-wire command to finish before 4549 /* Wait appropriate time for two-wire command to finish before
4588 polling the status register */ 4550 polling the status register */
4589 msleep(1); 4551 msleep(1);
@@ -4591,8 +4553,8 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4591 /* Wait up to 500us for command complete status */ 4553 /* Wait up to 500us for command complete status */
4592 for (i = 0; i < 100; i++) { 4554 for (i = 0; i < 100; i++) {
4593 bnx2x_cl45_read(bp, phy, 4555 bnx2x_cl45_read(bp, phy,
4594 MDIO_PMA_DEVAD, 4556 MDIO_PMA_DEVAD,
4595 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 4557 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4596 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 4558 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4597 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 4559 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4598 break; 4560 break;
@@ -4610,15 +4572,15 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4610 /* Read the buffer */ 4572 /* Read the buffer */
4611 for (i = 0; i < byte_cnt; i++) { 4573 for (i = 0; i < byte_cnt; i++) {
4612 bnx2x_cl45_read(bp, phy, 4574 bnx2x_cl45_read(bp, phy,
4613 MDIO_PMA_DEVAD, 4575 MDIO_PMA_DEVAD,
4614 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 4576 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4615 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 4577 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4616 } 4578 }
4617 4579
4618 for (i = 0; i < 100; i++) { 4580 for (i = 0; i < 100; i++) {
4619 bnx2x_cl45_read(bp, phy, 4581 bnx2x_cl45_read(bp, phy,
4620 MDIO_PMA_DEVAD, 4582 MDIO_PMA_DEVAD,
4621 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 4583 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4622 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 4584 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4623 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 4585 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4624 return 0; 4586 return 0;
@@ -4628,22 +4590,22 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4628 return -EINVAL; 4590 return -EINVAL;
4629} 4591}
4630 4592
4631static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 4593u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4632 struct link_params *params, u16 addr, 4594 struct link_params *params, u16 addr,
4633 u8 byte_cnt, u8 *o_buf) 4595 u8 byte_cnt, u8 *o_buf)
4634{ 4596{
4635 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) 4597 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4636 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, 4598 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4637 byte_cnt, o_buf); 4599 byte_cnt, o_buf);
4638 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) 4600 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4639 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, 4601 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4640 byte_cnt, o_buf); 4602 byte_cnt, o_buf);
4641 return -EINVAL; 4603 return -EINVAL;
4642} 4604}
4643 4605
4644static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy, 4606static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4645 struct link_params *params, 4607 struct link_params *params,
4646 u16 *edc_mode) 4608 u16 *edc_mode)
4647{ 4609{
4648 struct bnx2x *bp = params->bp; 4610 struct bnx2x *bp = params->bp;
4649 u8 val, check_limiting_mode = 0; 4611 u8 val, check_limiting_mode = 0;
@@ -4774,17 +4736,17 @@ static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4774 /* format the warning message */ 4736 /* format the warning message */
4775 if (bnx2x_read_sfp_module_eeprom(phy, 4737 if (bnx2x_read_sfp_module_eeprom(phy,
4776 params, 4738 params,
4777 SFP_EEPROM_VENDOR_NAME_ADDR, 4739 SFP_EEPROM_VENDOR_NAME_ADDR,
4778 SFP_EEPROM_VENDOR_NAME_SIZE, 4740 SFP_EEPROM_VENDOR_NAME_SIZE,
4779 (u8 *)vendor_name)) 4741 (u8 *)vendor_name))
4780 vendor_name[0] = '\0'; 4742 vendor_name[0] = '\0';
4781 else 4743 else
4782 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 4744 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4783 if (bnx2x_read_sfp_module_eeprom(phy, 4745 if (bnx2x_read_sfp_module_eeprom(phy,
4784 params, 4746 params,
4785 SFP_EEPROM_PART_NO_ADDR, 4747 SFP_EEPROM_PART_NO_ADDR,
4786 SFP_EEPROM_PART_NO_SIZE, 4748 SFP_EEPROM_PART_NO_SIZE,
4787 (u8 *)vendor_pn)) 4749 (u8 *)vendor_pn))
4788 vendor_pn[0] = '\0'; 4750 vendor_pn[0] = '\0';
4789 else 4751 else
4790 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 4752 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
@@ -4861,15 +4823,14 @@ static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4861 u16 cur_limiting_mode; 4823 u16 cur_limiting_mode;
4862 4824
4863 bnx2x_cl45_read(bp, phy, 4825 bnx2x_cl45_read(bp, phy,
4864 MDIO_PMA_DEVAD, 4826 MDIO_PMA_DEVAD,
4865 MDIO_PMA_REG_ROM_VER2, 4827 MDIO_PMA_REG_ROM_VER2,
4866 &cur_limiting_mode); 4828 &cur_limiting_mode);
4867 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 4829 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4868 cur_limiting_mode); 4830 cur_limiting_mode);
4869 4831
4870 if (edc_mode == EDC_MODE_LIMITING) { 4832 if (edc_mode == EDC_MODE_LIMITING) {
4871 DP(NETIF_MSG_LINK, 4833 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
4872 "Setting LIMITING MODE\n");
4873 bnx2x_cl45_write(bp, phy, 4834 bnx2x_cl45_write(bp, phy,
4874 MDIO_PMA_DEVAD, 4835 MDIO_PMA_DEVAD,
4875 MDIO_PMA_REG_ROM_VER2, 4836 MDIO_PMA_REG_ROM_VER2,
@@ -4885,55 +4846,55 @@ static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4885 return 0; 4846 return 0;
4886 4847
4887 bnx2x_cl45_write(bp, phy, 4848 bnx2x_cl45_write(bp, phy,
4888 MDIO_PMA_DEVAD, 4849 MDIO_PMA_DEVAD,
4889 MDIO_PMA_REG_LRM_MODE, 4850 MDIO_PMA_REG_LRM_MODE,
4890 0); 4851 0);
4891 bnx2x_cl45_write(bp, phy, 4852 bnx2x_cl45_write(bp, phy,
4892 MDIO_PMA_DEVAD, 4853 MDIO_PMA_DEVAD,
4893 MDIO_PMA_REG_ROM_VER2, 4854 MDIO_PMA_REG_ROM_VER2,
4894 0x128); 4855 0x128);
4895 bnx2x_cl45_write(bp, phy, 4856 bnx2x_cl45_write(bp, phy,
4896 MDIO_PMA_DEVAD, 4857 MDIO_PMA_DEVAD,
4897 MDIO_PMA_REG_MISC_CTRL0, 4858 MDIO_PMA_REG_MISC_CTRL0,
4898 0x4008); 4859 0x4008);
4899 bnx2x_cl45_write(bp, phy, 4860 bnx2x_cl45_write(bp, phy,
4900 MDIO_PMA_DEVAD, 4861 MDIO_PMA_DEVAD,
4901 MDIO_PMA_REG_LRM_MODE, 4862 MDIO_PMA_REG_LRM_MODE,
4902 0xaaaa); 4863 0xaaaa);
4903 } 4864 }
4904 return 0; 4865 return 0;
4905} 4866}
4906 4867
4907static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 4868static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4908 struct bnx2x_phy *phy, 4869 struct bnx2x_phy *phy,
4909 u16 edc_mode) 4870 u16 edc_mode)
4910{ 4871{
4911 u16 phy_identifier; 4872 u16 phy_identifier;
4912 u16 rom_ver2_val; 4873 u16 rom_ver2_val;
4913 bnx2x_cl45_read(bp, phy, 4874 bnx2x_cl45_read(bp, phy,
4914 MDIO_PMA_DEVAD, 4875 MDIO_PMA_DEVAD,
4915 MDIO_PMA_REG_PHY_IDENTIFIER, 4876 MDIO_PMA_REG_PHY_IDENTIFIER,
4916 &phy_identifier); 4877 &phy_identifier);
4917 4878
4918 bnx2x_cl45_write(bp, phy, 4879 bnx2x_cl45_write(bp, phy,
4919 MDIO_PMA_DEVAD, 4880 MDIO_PMA_DEVAD,
4920 MDIO_PMA_REG_PHY_IDENTIFIER, 4881 MDIO_PMA_REG_PHY_IDENTIFIER,
4921 (phy_identifier & ~(1<<9))); 4882 (phy_identifier & ~(1<<9)));
4922 4883
4923 bnx2x_cl45_read(bp, phy, 4884 bnx2x_cl45_read(bp, phy,
4924 MDIO_PMA_DEVAD, 4885 MDIO_PMA_DEVAD,
4925 MDIO_PMA_REG_ROM_VER2, 4886 MDIO_PMA_REG_ROM_VER2,
4926 &rom_ver2_val); 4887 &rom_ver2_val);
4927 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 4888 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4928 bnx2x_cl45_write(bp, phy, 4889 bnx2x_cl45_write(bp, phy,
4929 MDIO_PMA_DEVAD, 4890 MDIO_PMA_DEVAD,
4930 MDIO_PMA_REG_ROM_VER2, 4891 MDIO_PMA_REG_ROM_VER2,
4931 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 4892 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4932 4893
4933 bnx2x_cl45_write(bp, phy, 4894 bnx2x_cl45_write(bp, phy,
4934 MDIO_PMA_DEVAD, 4895 MDIO_PMA_DEVAD,
4935 MDIO_PMA_REG_PHY_IDENTIFIER, 4896 MDIO_PMA_REG_PHY_IDENTIFIER,
4936 (phy_identifier | (1<<9))); 4897 (phy_identifier | (1<<9)));
4937 4898
4938 return 0; 4899 return 0;
4939} 4900}
@@ -4976,8 +4937,7 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
4976 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 4937 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
4977 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 4938 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4978 return -EINVAL; 4939 return -EINVAL;
4979 } else if (bnx2x_verify_sfp_module(phy, params) != 4940 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
4980 0) {
4981 /* check SFP+ module compatibility */ 4941 /* check SFP+ module compatibility */
4982 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 4942 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4983 rc = -EINVAL; 4943 rc = -EINVAL;
@@ -5053,9 +5013,9 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
5053 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 5013 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5054 } else { 5014 } else {
5055 u32 val = REG_RD(bp, params->shmem_base + 5015 u32 val = REG_RD(bp, params->shmem_base +
5056 offsetof(struct shmem_region, dev_info. 5016 offsetof(struct shmem_region, dev_info.
5057 port_feature_config[params->port]. 5017 port_feature_config[params->port].
5058 config)); 5018 config));
5059 5019
5060 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, 5020 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5061 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 5021 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
@@ -5126,7 +5086,7 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5126 u16 cnt, val; 5086 u16 cnt, val;
5127 struct bnx2x *bp = params->bp; 5087 struct bnx2x *bp = params->bp;
5128 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 5088 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5129 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 5089 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5130 /* HW reset */ 5090 /* HW reset */
5131 bnx2x_ext_phy_hw_reset(bp, params->port); 5091 bnx2x_ext_phy_hw_reset(bp, params->port);
5132 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 5092 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
@@ -5231,26 +5191,26 @@ static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5231 5191
5232 /* Set soft reset */ 5192 /* Set soft reset */
5233 bnx2x_cl45_write(bp, phy, 5193 bnx2x_cl45_write(bp, phy,
5234 MDIO_PMA_DEVAD, 5194 MDIO_PMA_DEVAD,
5235 MDIO_PMA_REG_GEN_CTRL, 5195 MDIO_PMA_REG_GEN_CTRL,
5236 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 5196 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5237 5197
5238 bnx2x_cl45_write(bp, phy, 5198 bnx2x_cl45_write(bp, phy,
5239 MDIO_PMA_DEVAD, 5199 MDIO_PMA_DEVAD,
5240 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 5200 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5241 5201
5242 bnx2x_cl45_write(bp, phy, 5202 bnx2x_cl45_write(bp, phy,
5243 MDIO_PMA_DEVAD, 5203 MDIO_PMA_DEVAD,
5244 MDIO_PMA_REG_GEN_CTRL, 5204 MDIO_PMA_REG_GEN_CTRL,
5245 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 5205 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5246 5206
5247 /* wait for 150ms for microcode load */ 5207 /* wait for 150ms for microcode load */
5248 msleep(150); 5208 msleep(150);
5249 5209
5250 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 5210 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5251 bnx2x_cl45_write(bp, phy, 5211 bnx2x_cl45_write(bp, phy,
5252 MDIO_PMA_DEVAD, 5212 MDIO_PMA_DEVAD,
5253 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 5213 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5254 5214
5255 msleep(200); 5215 msleep(200);
5256 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 5216 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
@@ -5367,7 +5327,7 @@ static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5367 5327
5368 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 5328 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5369 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 5329 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5370 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port); 5330 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5371 5331
5372 /* The GPIO should be swapped if the swap register is set and active */ 5332 /* The GPIO should be swapped if the swap register is set and active */
5373 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 5333 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
@@ -5467,7 +5427,7 @@ static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5467 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 5427 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5468 port = (swap_val && swap_override) ^ 1; 5428 port = (swap_val && swap_override) ^ 1;
5469 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 5429 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5470 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 5430 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5471} 5431}
5472 5432
5473static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy, 5433static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
@@ -5620,8 +5580,8 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5620 port_feature_config[params->port]. 5580 port_feature_config[params->port].
5621 config)); 5581 config));
5622 bnx2x_cl45_read(bp, phy, 5582 bnx2x_cl45_read(bp, phy,
5623 MDIO_PMA_DEVAD, 5583 MDIO_PMA_DEVAD,
5624 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 5584 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5625 if (mod_abs & (1<<8)) { 5585 if (mod_abs & (1<<8)) {
5626 5586
5627 /* Module is absent */ 5587 /* Module is absent */
@@ -5638,14 +5598,14 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5638 if (!(phy->flags & FLAGS_NOC)) 5598 if (!(phy->flags & FLAGS_NOC))
5639 mod_abs &= ~(1<<9); 5599 mod_abs &= ~(1<<9);
5640 bnx2x_cl45_write(bp, phy, 5600 bnx2x_cl45_write(bp, phy,
5641 MDIO_PMA_DEVAD, 5601 MDIO_PMA_DEVAD,
5642 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 5602 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5643 5603
5644 /* Clear RX alarm since it stays up as long as 5604 /* Clear RX alarm since it stays up as long as
5645 the mod_abs wasn't changed */ 5605 the mod_abs wasn't changed */
5646 bnx2x_cl45_read(bp, phy, 5606 bnx2x_cl45_read(bp, phy,
5647 MDIO_PMA_DEVAD, 5607 MDIO_PMA_DEVAD,
5648 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 5608 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5649 5609
5650 } else { 5610 } else {
5651 /* Module is present */ 5611 /* Module is present */
@@ -6086,7 +6046,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6086 struct bnx2x *bp = params->bp; 6046 struct bnx2x *bp = params->bp;
6087 /* Restore normal power mode*/ 6047 /* Restore normal power mode*/
6088 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6048 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6089 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 6049 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6090 6050
6091 /* HW reset */ 6051 /* HW reset */
6092 bnx2x_ext_phy_hw_reset(bp, params->port); 6052 bnx2x_ext_phy_hw_reset(bp, params->port);
@@ -6176,8 +6136,8 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6176} 6136}
6177 6137
6178static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 6138static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6179 struct link_params *params, 6139 struct link_params *params,
6180 struct link_vars *vars) 6140 struct link_vars *vars)
6181{ 6141{
6182 struct bnx2x *bp = params->bp; 6142 struct bnx2x *bp = params->bp;
6183 u16 val, val1, val2; 6143 u16 val, val1, val2;
@@ -6273,9 +6233,9 @@ static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6273 struct link_params *params) 6233 struct link_params *params)
6274{ 6234{
6275 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 6235 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6276 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 6236 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6277 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 6237 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6278 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 6238 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6279} 6239}
6280 6240
6281static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 6241static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
@@ -6297,8 +6257,8 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6297 else 6257 else
6298 port = params->port; 6258 port = params->port;
6299 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 6259 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6300 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6260 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6301 port); 6261 port);
6302} 6262}
6303 6263
6304static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 6264static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
@@ -6353,24 +6313,24 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6353 6313
6354 /* Set LED masks */ 6314 /* Set LED masks */
6355 bnx2x_cl45_write(bp, phy, 6315 bnx2x_cl45_write(bp, phy,
6356 MDIO_PMA_DEVAD, 6316 MDIO_PMA_DEVAD,
6357 MDIO_PMA_REG_8481_LED1_MASK, 6317 MDIO_PMA_REG_8481_LED1_MASK,
6358 0x0); 6318 0x0);
6359 6319
6360 bnx2x_cl45_write(bp, phy, 6320 bnx2x_cl45_write(bp, phy,
6361 MDIO_PMA_DEVAD, 6321 MDIO_PMA_DEVAD,
6362 MDIO_PMA_REG_8481_LED2_MASK, 6322 MDIO_PMA_REG_8481_LED2_MASK,
6363 0x0); 6323 0x0);
6364 6324
6365 bnx2x_cl45_write(bp, phy, 6325 bnx2x_cl45_write(bp, phy,
6366 MDIO_PMA_DEVAD, 6326 MDIO_PMA_DEVAD,
6367 MDIO_PMA_REG_8481_LED3_MASK, 6327 MDIO_PMA_REG_8481_LED3_MASK,
6368 0x0); 6328 0x0);
6369 6329
6370 bnx2x_cl45_write(bp, phy, 6330 bnx2x_cl45_write(bp, phy,
6371 MDIO_PMA_DEVAD, 6331 MDIO_PMA_DEVAD,
6372 MDIO_PMA_REG_8481_LED5_MASK, 6332 MDIO_PMA_REG_8481_LED5_MASK,
6373 0x20); 6333 0x20);
6374 6334
6375 } else { 6335 } else {
6376 bnx2x_cl45_write(bp, phy, 6336 bnx2x_cl45_write(bp, phy,
@@ -6394,35 +6354,35 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6394 val |= 0x2492; 6354 val |= 0x2492;
6395 6355
6396 bnx2x_cl45_write(bp, phy, 6356 bnx2x_cl45_write(bp, phy,
6397 MDIO_PMA_DEVAD, 6357 MDIO_PMA_DEVAD,
6398 MDIO_PMA_REG_8481_LINK_SIGNAL, 6358 MDIO_PMA_REG_8481_LINK_SIGNAL,
6399 val); 6359 val);
6400 6360
6401 /* Set LED masks */ 6361 /* Set LED masks */
6402 bnx2x_cl45_write(bp, phy, 6362 bnx2x_cl45_write(bp, phy,
6403 MDIO_PMA_DEVAD, 6363 MDIO_PMA_DEVAD,
6404 MDIO_PMA_REG_8481_LED1_MASK, 6364 MDIO_PMA_REG_8481_LED1_MASK,
6405 0x0); 6365 0x0);
6406 6366
6407 bnx2x_cl45_write(bp, phy, 6367 bnx2x_cl45_write(bp, phy,
6408 MDIO_PMA_DEVAD, 6368 MDIO_PMA_DEVAD,
6409 MDIO_PMA_REG_8481_LED2_MASK, 6369 MDIO_PMA_REG_8481_LED2_MASK,
6410 0x20); 6370 0x20);
6411 6371
6412 bnx2x_cl45_write(bp, phy, 6372 bnx2x_cl45_write(bp, phy,
6413 MDIO_PMA_DEVAD, 6373 MDIO_PMA_DEVAD,
6414 MDIO_PMA_REG_8481_LED3_MASK, 6374 MDIO_PMA_REG_8481_LED3_MASK,
6415 0x20); 6375 0x20);
6416 6376
6417 bnx2x_cl45_write(bp, phy, 6377 bnx2x_cl45_write(bp, phy,
6418 MDIO_PMA_DEVAD, 6378 MDIO_PMA_DEVAD,
6419 MDIO_PMA_REG_8481_LED5_MASK, 6379 MDIO_PMA_REG_8481_LED5_MASK,
6420 0x0); 6380 0x0);
6421 } else { 6381 } else {
6422 bnx2x_cl45_write(bp, phy, 6382 bnx2x_cl45_write(bp, phy,
6423 MDIO_PMA_DEVAD, 6383 MDIO_PMA_DEVAD,
6424 MDIO_PMA_REG_8481_LED1_MASK, 6384 MDIO_PMA_REG_8481_LED1_MASK,
6425 0x20); 6385 0x20);
6426 } 6386 }
6427 break; 6387 break;
6428 6388
@@ -6440,8 +6400,8 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6440 &val); 6400 &val);
6441 6401
6442 if (!((val & 6402 if (!((val &
6443 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 6403 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6444 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){ 6404 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
6445 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n"); 6405 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
6446 bnx2x_cl45_write(bp, phy, 6406 bnx2x_cl45_write(bp, phy,
6447 MDIO_PMA_DEVAD, 6407 MDIO_PMA_DEVAD,
@@ -6451,24 +6411,24 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6451 6411
6452 /* Set LED masks */ 6412 /* Set LED masks */
6453 bnx2x_cl45_write(bp, phy, 6413 bnx2x_cl45_write(bp, phy,
6454 MDIO_PMA_DEVAD, 6414 MDIO_PMA_DEVAD,
6455 MDIO_PMA_REG_8481_LED1_MASK, 6415 MDIO_PMA_REG_8481_LED1_MASK,
6456 0x10); 6416 0x10);
6457 6417
6458 bnx2x_cl45_write(bp, phy, 6418 bnx2x_cl45_write(bp, phy,
6459 MDIO_PMA_DEVAD, 6419 MDIO_PMA_DEVAD,
6460 MDIO_PMA_REG_8481_LED2_MASK, 6420 MDIO_PMA_REG_8481_LED2_MASK,
6461 0x80); 6421 0x80);
6462 6422
6463 bnx2x_cl45_write(bp, phy, 6423 bnx2x_cl45_write(bp, phy,
6464 MDIO_PMA_DEVAD, 6424 MDIO_PMA_DEVAD,
6465 MDIO_PMA_REG_8481_LED3_MASK, 6425 MDIO_PMA_REG_8481_LED3_MASK,
6466 0x98); 6426 0x98);
6467 6427
6468 bnx2x_cl45_write(bp, phy, 6428 bnx2x_cl45_write(bp, phy,
6469 MDIO_PMA_DEVAD, 6429 MDIO_PMA_DEVAD,
6470 MDIO_PMA_REG_8481_LED5_MASK, 6430 MDIO_PMA_REG_8481_LED5_MASK,
6471 0x40); 6431 0x40);
6472 6432
6473 } else { 6433 } else {
6474 bnx2x_cl45_write(bp, phy, 6434 bnx2x_cl45_write(bp, phy,
@@ -6513,7 +6473,7 @@ static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6513 6473
6514 /* Restore normal power mode*/ 6474 /* Restore normal power mode*/
6515 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6475 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6516 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 6476 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6517 /* HW reset */ 6477 /* HW reset */
6518 bnx2x_ext_phy_hw_reset(bp, params->port); 6478 bnx2x_ext_phy_hw_reset(bp, params->port);
6519 bnx2x_wait_reset_complete(bp, phy); 6479 bnx2x_wait_reset_complete(bp, phy);
@@ -6599,20 +6559,20 @@ void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6599 u16 val, cnt; 6559 u16 val, cnt;
6600 6560
6601 bnx2x_cl45_read(bp, phy, 6561 bnx2x_cl45_read(bp, phy,
6602 MDIO_PMA_DEVAD, 6562 MDIO_PMA_DEVAD,
6603 MDIO_PMA_REG_7101_RESET, &val); 6563 MDIO_PMA_REG_7101_RESET, &val);
6604 6564
6605 for (cnt = 0; cnt < 10; cnt++) { 6565 for (cnt = 0; cnt < 10; cnt++) {
6606 msleep(50); 6566 msleep(50);
6607 /* Writes a self-clearing reset */ 6567 /* Writes a self-clearing reset */
6608 bnx2x_cl45_write(bp, phy, 6568 bnx2x_cl45_write(bp, phy,
6609 MDIO_PMA_DEVAD, 6569 MDIO_PMA_DEVAD,
6610 MDIO_PMA_REG_7101_RESET, 6570 MDIO_PMA_REG_7101_RESET,
6611 (val | (1<<15))); 6571 (val | (1<<15)));
6612 /* Wait for clear */ 6572 /* Wait for clear */
6613 bnx2x_cl45_read(bp, phy, 6573 bnx2x_cl45_read(bp, phy,
6614 MDIO_PMA_DEVAD, 6574 MDIO_PMA_DEVAD,
6615 MDIO_PMA_REG_7101_RESET, &val); 6575 MDIO_PMA_REG_7101_RESET, &val);
6616 6576
6617 if ((val & (1<<15)) == 0) 6577 if ((val & (1<<15)) == 0)
6618 break; 6578 break;
@@ -6623,10 +6583,10 @@ static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6623 struct link_params *params) { 6583 struct link_params *params) {
6624 /* Low power mode is controlled by GPIO 2 */ 6584 /* Low power mode is controlled by GPIO 2 */
6625 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 6585 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6626 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 6586 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6627 /* The PHY reset is controlled by GPIO 1 */ 6587 /* The PHY reset is controlled by GPIO 1 */
6628 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 6588 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6629 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 6589 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6630} 6590}
6631 6591
6632static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 6592static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
@@ -6668,9 +6628,9 @@ static struct bnx2x_phy phy_null = {
6668 .supported = 0, 6628 .supported = 0,
6669 .media_type = ETH_PHY_NOT_PRESENT, 6629 .media_type = ETH_PHY_NOT_PRESENT,
6670 .ver_addr = 0, 6630 .ver_addr = 0,
6671 .req_flow_ctrl = 0, 6631 .req_flow_ctrl = 0,
6672 .req_line_speed = 0, 6632 .req_line_speed = 0,
6673 .speed_cap_mask = 0, 6633 .speed_cap_mask = 0,
6674 .req_duplex = 0, 6634 .req_duplex = 0,
6675 .rsrv = 0, 6635 .rsrv = 0,
6676 .config_init = (config_init_t)NULL, 6636 .config_init = (config_init_t)NULL,
@@ -6705,8 +6665,8 @@ static struct bnx2x_phy phy_serdes = {
6705 .media_type = ETH_PHY_UNSPECIFIED, 6665 .media_type = ETH_PHY_UNSPECIFIED,
6706 .ver_addr = 0, 6666 .ver_addr = 0,
6707 .req_flow_ctrl = 0, 6667 .req_flow_ctrl = 0,
6708 .req_line_speed = 0, 6668 .req_line_speed = 0,
6709 .speed_cap_mask = 0, 6669 .speed_cap_mask = 0,
6710 .req_duplex = 0, 6670 .req_duplex = 0,
6711 .rsrv = 0, 6671 .rsrv = 0,
6712 .config_init = (config_init_t)bnx2x_init_serdes, 6672 .config_init = (config_init_t)bnx2x_init_serdes,
@@ -6742,8 +6702,8 @@ static struct bnx2x_phy phy_xgxs = {
6742 .media_type = ETH_PHY_UNSPECIFIED, 6702 .media_type = ETH_PHY_UNSPECIFIED,
6743 .ver_addr = 0, 6703 .ver_addr = 0,
6744 .req_flow_ctrl = 0, 6704 .req_flow_ctrl = 0,
6745 .req_line_speed = 0, 6705 .req_line_speed = 0,
6746 .speed_cap_mask = 0, 6706 .speed_cap_mask = 0,
6747 .req_duplex = 0, 6707 .req_duplex = 0,
6748 .rsrv = 0, 6708 .rsrv = 0,
6749 .config_init = (config_init_t)bnx2x_init_xgxs, 6709 .config_init = (config_init_t)bnx2x_init_xgxs,
@@ -6773,8 +6733,8 @@ static struct bnx2x_phy phy_7101 = {
6773 .media_type = ETH_PHY_BASE_T, 6733 .media_type = ETH_PHY_BASE_T,
6774 .ver_addr = 0, 6734 .ver_addr = 0,
6775 .req_flow_ctrl = 0, 6735 .req_flow_ctrl = 0,
6776 .req_line_speed = 0, 6736 .req_line_speed = 0,
6777 .speed_cap_mask = 0, 6737 .speed_cap_mask = 0,
6778 .req_duplex = 0, 6738 .req_duplex = 0,
6779 .rsrv = 0, 6739 .rsrv = 0,
6780 .config_init = (config_init_t)bnx2x_7101_config_init, 6740 .config_init = (config_init_t)bnx2x_7101_config_init,
@@ -6804,9 +6764,9 @@ static struct bnx2x_phy phy_8073 = {
6804 SUPPORTED_Asym_Pause), 6764 SUPPORTED_Asym_Pause),
6805 .media_type = ETH_PHY_UNSPECIFIED, 6765 .media_type = ETH_PHY_UNSPECIFIED,
6806 .ver_addr = 0, 6766 .ver_addr = 0,
6807 .req_flow_ctrl = 0, 6767 .req_flow_ctrl = 0,
6808 .req_line_speed = 0, 6768 .req_line_speed = 0,
6809 .speed_cap_mask = 0, 6769 .speed_cap_mask = 0,
6810 .req_duplex = 0, 6770 .req_duplex = 0,
6811 .rsrv = 0, 6771 .rsrv = 0,
6812 .config_init = (config_init_t)bnx2x_8073_config_init, 6772 .config_init = (config_init_t)bnx2x_8073_config_init,
@@ -7036,19 +6996,19 @@ static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7036 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 6996 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7037 rx = REG_RD(bp, shmem_base + 6997 rx = REG_RD(bp, shmem_base +
7038 offsetof(struct shmem_region, 6998 offsetof(struct shmem_region,
7039 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 6999 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7040 7000
7041 tx = REG_RD(bp, shmem_base + 7001 tx = REG_RD(bp, shmem_base +
7042 offsetof(struct shmem_region, 7002 offsetof(struct shmem_region,
7043 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 7003 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7044 } else { 7004 } else {
7045 rx = REG_RD(bp, shmem_base + 7005 rx = REG_RD(bp, shmem_base +
7046 offsetof(struct shmem_region, 7006 offsetof(struct shmem_region,
7047 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 7007 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7048 7008
7049 tx = REG_RD(bp, shmem_base + 7009 tx = REG_RD(bp, shmem_base +
7050 offsetof(struct shmem_region, 7010 offsetof(struct shmem_region,
7051 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 7011 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7052 } 7012 }
7053 7013
7054 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 7014 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
@@ -7193,10 +7153,10 @@ static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7193 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 7153 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7194 port_mb[port].ext_phy_fw_version); 7154 port_mb[port].ext_phy_fw_version);
7195 7155
7196 /* Check specific mdc mdio settings */ 7156 /* Check specific mdc mdio settings */
7197 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 7157 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7198 mdc_mdio_access = config2 & 7158 mdc_mdio_access = config2 &
7199 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 7159 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7200 } else { 7160 } else {
7201 u32 size = REG_RD(bp, shmem2_base); 7161 u32 size = REG_RD(bp, shmem2_base);
7202 7162
@@ -7250,18 +7210,20 @@ static void bnx2x_phy_def_cfg(struct link_params *params,
7250 /* Populate the default phy configuration for MF mode */ 7210 /* Populate the default phy configuration for MF mode */
7251 if (phy_index == EXT_PHY2) { 7211 if (phy_index == EXT_PHY2) {
7252 link_config = REG_RD(bp, params->shmem_base + 7212 link_config = REG_RD(bp, params->shmem_base +
7253 offsetof(struct shmem_region, dev_info. 7213 offsetof(struct shmem_region, dev_info.
7254 port_feature_config[params->port].link_config2)); 7214 port_feature_config[params->port].link_config2));
7255 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 7215 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7256 offsetof(struct shmem_region, dev_info. 7216 offsetof(struct shmem_region,
7217 dev_info.
7257 port_hw_config[params->port].speed_capability_mask2)); 7218 port_hw_config[params->port].speed_capability_mask2));
7258 } else { 7219 } else {
7259 link_config = REG_RD(bp, params->shmem_base + 7220 link_config = REG_RD(bp, params->shmem_base +
7260 offsetof(struct shmem_region, dev_info. 7221 offsetof(struct shmem_region, dev_info.
7261 port_feature_config[params->port].link_config)); 7222 port_feature_config[params->port].link_config));
7262 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 7223 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7263 offsetof(struct shmem_region, dev_info. 7224 offsetof(struct shmem_region,
7264 port_hw_config[params->port].speed_capability_mask)); 7225 dev_info.
7226 port_hw_config[params->port].speed_capability_mask));
7265 } 7227 }
7266 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask" 7228 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7267 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask); 7229 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
@@ -7408,7 +7370,7 @@ static void set_phy_vars(struct link_params *params)
7408 else if (phy_index == EXT_PHY2) 7370 else if (phy_index == EXT_PHY2)
7409 actual_phy_idx = EXT_PHY1; 7371 actual_phy_idx = EXT_PHY1;
7410 } 7372 }
7411 params->phy[actual_phy_idx].req_flow_ctrl = 7373 params->phy[actual_phy_idx].req_flow_ctrl =
7412 params->req_flow_ctrl[link_cfg_idx]; 7374 params->req_flow_ctrl[link_cfg_idx];
7413 7375
7414 params->phy[actual_phy_idx].req_line_speed = 7376 params->phy[actual_phy_idx].req_line_speed =
@@ -7527,8 +7489,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7527 /* set bmac loopback */ 7489 /* set bmac loopback */
7528 bnx2x_bmac_enable(params, vars, 1); 7490 bnx2x_bmac_enable(params, vars, 1);
7529 7491
7530 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 7492 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7531 params->port*4, 0);
7532 7493
7533 } else if (params->loopback_mode == LOOPBACK_EMAC) { 7494 } else if (params->loopback_mode == LOOPBACK_EMAC) {
7534 7495
@@ -7544,8 +7505,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7544 /* set bmac loopback */ 7505 /* set bmac loopback */
7545 bnx2x_emac_enable(params, vars, 1); 7506 bnx2x_emac_enable(params, vars, 1);
7546 bnx2x_emac_program(params, vars); 7507 bnx2x_emac_program(params, vars);
7547 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 7508 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7548 params->port*4, 0);
7549 7509
7550 } else if ((params->loopback_mode == LOOPBACK_XGXS) || 7510 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7551 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 7511 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
@@ -7568,8 +7528,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7568 bnx2x_emac_program(params, vars); 7528 bnx2x_emac_program(params, vars);
7569 bnx2x_emac_enable(params, vars, 0); 7529 bnx2x_emac_enable(params, vars, 0);
7570 } else 7530 } else
7571 bnx2x_bmac_enable(params, vars, 0); 7531 bnx2x_bmac_enable(params, vars, 0);
7572
7573 if (params->loopback_mode == LOOPBACK_XGXS) { 7532 if (params->loopback_mode == LOOPBACK_XGXS) {
7574 /* set 10G XGXS loopback */ 7533 /* set 10G XGXS loopback */
7575 params->phy[INT_PHY].config_loopback( 7534 params->phy[INT_PHY].config_loopback(
@@ -7587,9 +7546,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7587 params); 7546 params);
7588 } 7547 }
7589 } 7548 }
7590 7549 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7591 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7592 params->port*4, 0);
7593 7550
7594 bnx2x_set_led(params, vars, 7551 bnx2x_set_led(params, vars,
7595 LED_MODE_OPER, vars->line_speed); 7552 LED_MODE_OPER, vars->line_speed);
@@ -7608,7 +7565,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7608 return 0; 7565 return 0;
7609} 7566}
7610u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 7567u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7611 u8 reset_ext_phy) 7568 u8 reset_ext_phy)
7612{ 7569{
7613 struct bnx2x *bp = params->bp; 7570 struct bnx2x *bp = params->bp;
7614 u8 phy_index, port = params->port, clear_latch_ind = 0; 7571 u8 phy_index, port = params->port, clear_latch_ind = 0;
@@ -7617,10 +7574,10 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7617 vars->link_status = 0; 7574 vars->link_status = 0;
7618 bnx2x_update_mng(params, vars->link_status); 7575 bnx2x_update_mng(params, vars->link_status);
7619 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 7576 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7620 (NIG_MASK_XGXS0_LINK_STATUS | 7577 (NIG_MASK_XGXS0_LINK_STATUS |
7621 NIG_MASK_XGXS0_LINK10G | 7578 NIG_MASK_XGXS0_LINK10G |
7622 NIG_MASK_SERDES0_LINK_STATUS | 7579 NIG_MASK_SERDES0_LINK_STATUS |
7623 NIG_MASK_MI_INT)); 7580 NIG_MASK_MI_INT));
7624 7581
7625 /* activate nig drain */ 7582 /* activate nig drain */
7626 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 7583 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
@@ -7719,21 +7676,22 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7719 /* disable attentions */ 7676 /* disable attentions */
7720 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 7677 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7721 port_of_path*4, 7678 port_of_path*4,
7722 (NIG_MASK_XGXS0_LINK_STATUS | 7679 (NIG_MASK_XGXS0_LINK_STATUS |
7723 NIG_MASK_XGXS0_LINK10G | 7680 NIG_MASK_XGXS0_LINK10G |
7724 NIG_MASK_SERDES0_LINK_STATUS | 7681 NIG_MASK_SERDES0_LINK_STATUS |
7725 NIG_MASK_MI_INT)); 7682 NIG_MASK_MI_INT));
7726 7683
7727 /* Need to take the phy out of low power mode in order 7684 /* Need to take the phy out of low power mode in order
7728 to write to access its registers */ 7685 to write to access its registers */
7729 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7686 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7730 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7687 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7688 port);
7731 7689
7732 /* Reset the phy */ 7690 /* Reset the phy */
7733 bnx2x_cl45_write(bp, &phy[port], 7691 bnx2x_cl45_write(bp, &phy[port],
7734 MDIO_PMA_DEVAD, 7692 MDIO_PMA_DEVAD,
7735 MDIO_PMA_REG_CTRL, 7693 MDIO_PMA_REG_CTRL,
7736 1<<15); 7694 1<<15);
7737 } 7695 }
7738 7696
7739 /* Add delay of 150ms after reset */ 7697 /* Add delay of 150ms after reset */
@@ -7762,14 +7720,14 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7762 7720
7763 /* Only set bit 10 = 1 (Tx power down) */ 7721 /* Only set bit 10 = 1 (Tx power down) */
7764 bnx2x_cl45_read(bp, phy_blk[port], 7722 bnx2x_cl45_read(bp, phy_blk[port],
7765 MDIO_PMA_DEVAD, 7723 MDIO_PMA_DEVAD,
7766 MDIO_PMA_REG_TX_POWER_DOWN, &val); 7724 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7767 7725
7768 /* Phase1 of TX_POWER_DOWN reset */ 7726 /* Phase1 of TX_POWER_DOWN reset */
7769 bnx2x_cl45_write(bp, phy_blk[port], 7727 bnx2x_cl45_write(bp, phy_blk[port],
7770 MDIO_PMA_DEVAD, 7728 MDIO_PMA_DEVAD,
7771 MDIO_PMA_REG_TX_POWER_DOWN, 7729 MDIO_PMA_REG_TX_POWER_DOWN,
7772 (val | 1<<10)); 7730 (val | 1<<10));
7773 } 7731 }
7774 7732
7775 /* Toggle Transmitter: Power down and then up with 600ms 7733 /* Toggle Transmitter: Power down and then up with 600ms
@@ -7781,25 +7739,25 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7781 /* Phase2 of POWER_DOWN_RESET */ 7739 /* Phase2 of POWER_DOWN_RESET */
7782 /* Release bit 10 (Release Tx power down) */ 7740 /* Release bit 10 (Release Tx power down) */
7783 bnx2x_cl45_read(bp, phy_blk[port], 7741 bnx2x_cl45_read(bp, phy_blk[port],
7784 MDIO_PMA_DEVAD, 7742 MDIO_PMA_DEVAD,
7785 MDIO_PMA_REG_TX_POWER_DOWN, &val); 7743 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7786 7744
7787 bnx2x_cl45_write(bp, phy_blk[port], 7745 bnx2x_cl45_write(bp, phy_blk[port],
7788 MDIO_PMA_DEVAD, 7746 MDIO_PMA_DEVAD,
7789 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 7747 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7790 msleep(15); 7748 msleep(15);
7791 7749
7792 /* Read modify write the SPI-ROM version select register */ 7750 /* Read modify write the SPI-ROM version select register */
7793 bnx2x_cl45_read(bp, phy_blk[port], 7751 bnx2x_cl45_read(bp, phy_blk[port],
7794 MDIO_PMA_DEVAD, 7752 MDIO_PMA_DEVAD,
7795 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 7753 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
7796 bnx2x_cl45_write(bp, phy_blk[port], 7754 bnx2x_cl45_write(bp, phy_blk[port],
7797 MDIO_PMA_DEVAD, 7755 MDIO_PMA_DEVAD,
7798 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 7756 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7799 7757
7800 /* set GPIO2 back to LOW */ 7758 /* set GPIO2 back to LOW */
7801 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7759 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7802 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7760 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7803 } 7761 }
7804 return 0; 7762 return 0;
7805} 7763}
@@ -7846,8 +7804,8 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7846 7804
7847 /* Set fault module detected LED on */ 7805 /* Set fault module detected LED on */
7848 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 7806 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7849 MISC_REGISTERS_GPIO_HIGH, 7807 MISC_REGISTERS_GPIO_HIGH,
7850 port); 7808 port);
7851 } 7809 }
7852 7810
7853 return 0; 7811 return 0;
@@ -7862,8 +7820,8 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7862 struct bnx2x_phy phy[PORT_MAX]; 7820 struct bnx2x_phy phy[PORT_MAX];
7863 struct bnx2x_phy *phy_blk[PORT_MAX]; 7821 struct bnx2x_phy *phy_blk[PORT_MAX];
7864 s8 port_of_path; 7822 s8 port_of_path;
7865 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7823 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7866 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7824 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7867 7825
7868 port = 1; 7826 port = 1;
7869 7827
@@ -7907,9 +7865,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7907 7865
7908 /* Reset the phy */ 7866 /* Reset the phy */
7909 bnx2x_cl45_write(bp, &phy[port], 7867 bnx2x_cl45_write(bp, &phy[port],
7910 MDIO_PMA_DEVAD, 7868 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
7911 MDIO_PMA_REG_CTRL,
7912 1<<15);
7913 } 7869 }
7914 7870
7915 /* Add delay of 150ms after reset */ 7871 /* Add delay of 150ms after reset */
@@ -7923,7 +7879,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7923 } 7879 }
7924 /* PART2 - Download firmware to both phys */ 7880 /* PART2 - Download firmware to both phys */
7925 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 7881 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7926 if (CHIP_IS_E2(bp)) 7882 if (CHIP_IS_E2(bp))
7927 port_of_path = 0; 7883 port_of_path = 0;
7928 else 7884 else
7929 port_of_path = port; 7885 port_of_path = port;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 14:44:17 -0500