diff options
author | Dmitry Kravkov <dmitry@broadcom.com> | 2010-10-05 23:23:26 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-10-06 17:10:35 -0400 |
commit | 523224a3b3cd407ce4e6731a087194e13a90db18 (patch) | |
tree | bb0fda289682e4259c401b8a5763ba4cc4d41659 /drivers/net/bnx2x/bnx2x_fw_defs.h | |
parent | 0c5b77152e736d23a23eb2546eab323e27a37f52 (diff) |
bnx2x, cnic, bnx2i: use new FW/HSI
This is the new FW HSI blob and the relevant definitions without logic changes.
It also included code adaptation for new HSI. New features are not enabled.
New FW/HSI includes:
- Support for 57712 HW
- Future support for VF (not used)
- Improvements in FW interrupts scheme
- FW FCoE hooks (stubs for future usage)
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_fw_defs.h')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_fw_defs.h | 819 |
1 files changed, 378 insertions, 441 deletions
diff --git a/drivers/net/bnx2x/bnx2x_fw_defs.h b/drivers/net/bnx2x/bnx2x_fw_defs.h index 08d71bf438d6..f4e5b1ce8149 100644 --- a/drivers/net/bnx2x/bnx2x_fw_defs.h +++ b/drivers/net/bnx2x/bnx2x_fw_defs.h | |||
@@ -7,369 +7,272 @@ | |||
7 | * the Free Software Foundation. | 7 | * the Free Software Foundation. |
8 | */ | 8 | */ |
9 | 9 | ||
10 | 10 | #ifndef BNX2X_FW_DEFS_H | |
11 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET \ | 11 | #define BNX2X_FW_DEFS_H |
12 | (IS_E1H_OFFSET ? 0x7000 : 0x1000) | 12 | |
13 | #define CSTORM_ASSERT_LIST_OFFSET(idx) \ | 13 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[142].base) |
14 | (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | 14 | #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ |
15 | #define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \ | 15 | (IRO[141].base + ((assertListEntry) * IRO[141].m1)) |
16 | (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \ | 16 | #define CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ |
17 | ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \ | 17 | (IRO[144].base + ((pfId) * IRO[144].m1)) |
18 | 0x40) + (index * 0x4))) | 18 | #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ |
19 | #define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \ | 19 | (IRO[149].base + (((pfId)>>1) * IRO[149].m1) + (((pfId)&1) * \ |
20 | (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \ | 20 | IRO[149].m2)) |
21 | ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \ | 21 | #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ |
22 | 0x80) + (index * 0x4))) | 22 | (IRO[150].base + (((pfId)>>1) * IRO[150].m1) + (((pfId)&1) * \ |
23 | #define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \ | 23 | IRO[150].m2)) |
24 | (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \ | 24 | #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ |
25 | ((function&1) * 0x100)) : (0x3540 + (function * 0x40))) | 25 | (IRO[156].base + ((funcId) * IRO[156].m1)) |
26 | #define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \ | 26 | #define CSTORM_FUNC_EN_OFFSET(funcId) \ |
27 | (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \ | 27 | (IRO[146].base + ((funcId) * IRO[146].m1)) |
28 | ((function&1) * 0x200)) : (0x35c0 + (function * 0x80))) | 28 | #define CSTORM_FUNCTION_MODE_OFFSET (IRO[153].base) |
29 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \ | 29 | #define CSTORM_IGU_MODE_OFFSET (IRO[154].base) |
30 | (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \ | 30 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ |
31 | ((function&1) * 0x100)) : (0x3548 + (function * 0x40))) | 31 | (IRO[311].base + ((pfId) * IRO[311].m1)) |
32 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \ | 32 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ |
33 | (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \ | 33 | (IRO[312].base + ((pfId) * IRO[312].m1)) |
34 | ((function&1) * 0x200)) : (0x35c8 + (function * 0x80))) | 34 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ |
35 | #define CSTORM_FUNCTION_MODE_OFFSET \ | 35 | (IRO[304].base + ((pfId) * IRO[304].m1) + ((iscsiEqId) * \ |
36 | (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) | 36 | IRO[304].m2)) |
37 | #define CSTORM_HC_BTR_C_OFFSET(port) \ | 37 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ |
38 | (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0))) | 38 | (IRO[306].base + ((pfId) * IRO[306].m1) + ((iscsiEqId) * \ |
39 | #define CSTORM_HC_BTR_U_OFFSET(port) \ | 39 | IRO[306].m2)) |
40 | (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0))) | 40 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ |
41 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \ | 41 | (IRO[305].base + ((pfId) * IRO[305].m1) + ((iscsiEqId) * \ |
42 | (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \ | 42 | IRO[305].m2)) |
43 | (function * 0x8))) | 43 | #define \ |
44 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ | 44 | CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ |
45 | (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \ | 45 | (IRO[307].base + ((pfId) * IRO[307].m1) + ((iscsiEqId) * \ |
46 | (function * 0x8))) | 46 | IRO[307].m2)) |
47 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \ | 47 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ |
48 | (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 48 | (IRO[303].base + ((pfId) * IRO[303].m1) + ((iscsiEqId) * \ |
49 | (0x2410 + (function * 0xc0) + (eqIdx * 0x18))) | 49 | IRO[303].m2)) |
50 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \ | 50 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ |
51 | (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 51 | (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * \ |
52 | (0x2414 + (function * 0xc0) + (eqIdx * 0x18))) | 52 | IRO[309].m2)) |
53 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \ | 53 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ |
54 | (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \ | 54 | (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * \ |
55 | (0x241c + (function * 0xc0) + (eqIdx * 0x18))) | 55 | IRO[308].m2)) |
56 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \ | 56 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ |
57 | (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 57 | (IRO[310].base + ((pfId) * IRO[310].m1)) |
58 | (0x2427 + (function * 0xc0) + (eqIdx * 0x18))) | 58 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
59 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \ | 59 | (IRO[302].base + ((pfId) * IRO[302].m1)) |
60 | (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 60 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
61 | (0x2412 + (function * 0xc0) + (eqIdx * 0x18))) | 61 | (IRO[301].base + ((pfId) * IRO[301].m1)) |
62 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \ | 62 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
63 | (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 63 | (IRO[300].base + ((pfId) * IRO[300].m1)) |
64 | (0x2426 + (function * 0xc0) + (eqIdx * 0x18))) | 64 | #define CSTORM_PATH_ID_OFFSET (IRO[159].base) |
65 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \ | 65 | #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ |
66 | (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \ | 66 | (IRO[137].base + ((pfId) * IRO[137].m1)) |
67 | (0x2424 + (function * 0xc0) + (eqIdx * 0x18))) | 67 | #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ |
68 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ | 68 | (IRO[136].base + ((pfId) * IRO[136].m1)) |
69 | (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \ | 69 | #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[136].size) |
70 | (function * 0x8))) | 70 | #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ |
71 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | 71 | (IRO[138].base + ((pfId) * IRO[138].m1)) |
72 | (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \ | 72 | #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[138].size) |
73 | (function * 0x8))) | 73 | #define CSTORM_STATS_FLAGS_OFFSET(pfId) \ |
74 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | 74 | (IRO[143].base + ((pfId) * IRO[143].m1)) |
75 | (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \ | 75 | #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ |
76 | (function * 0x8))) | 76 | (IRO[129].base + ((sbId) * IRO[129].m1)) |
77 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | 77 | #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ |
78 | (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \ | 78 | (IRO[128].base + ((sbId) * IRO[128].m1)) |
79 | (function * 0x8))) | 79 | #define CSTORM_STATUS_BLOCK_SIZE (IRO[128].size) |
80 | #define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \ | 80 | #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ |
81 | (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \ | 81 | (IRO[132].base + ((sbId) * IRO[132].m1)) |
82 | (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \ | 82 | #define CSTORM_SYNC_BLOCK_SIZE (IRO[132].size) |
83 | (index * 0x4))) | 83 | #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \ |
84 | #define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \ | 84 | (IRO[151].base + ((vfId) * IRO[151].m1)) |
85 | (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \ | 85 | #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \ |
86 | (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \ | 86 | (IRO[152].base + ((vfId) * IRO[152].m1)) |
87 | (index * 0x4))) | 87 | #define CSTORM_VF_TO_PF_OFFSET(funcId) \ |
88 | #define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \ | 88 | (IRO[147].base + ((funcId) * IRO[147].m1)) |
89 | (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \ | 89 | #define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[199].base) |
90 | (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \ | 90 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ |
91 | (index * 0x4))) | 91 | (IRO[198].base + ((pfId) * IRO[198].m1)) |
92 | #define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \ | 92 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[99].base) |
93 | (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \ | 93 | #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ |
94 | (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \ | 94 | (IRO[98].base + ((assertListEntry) * IRO[98].m1)) |
95 | (index * 0x4))) | 95 | #define TSTORM_CLIENT_CONFIG_OFFSET(portId, clientId) \ |
96 | #define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \ | 96 | (IRO[197].base + ((portId) * IRO[197].m1) + ((clientId) * \ |
97 | (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \ | 97 | IRO[197].m2)) |
98 | (0x3040 + (port * 0x280) + (cpu_id * 0x28))) | 98 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[104].base) |
99 | #define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \ | ||
100 | (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \ | ||
101 | (0x4000 + (port * 0x800) + (cpu_id * 0x80))) | ||
102 | #define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \ | ||
103 | (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \ | ||
104 | (0x3048 + (port * 0x280) + (cpu_id * 0x28))) | ||
105 | #define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \ | ||
106 | (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \ | ||
107 | (0x4008 + (port * 0x800) + (cpu_id * 0x80))) | ||
108 | #define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10 | ||
109 | #define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60 | ||
110 | #define CSTORM_STATS_FLAGS_OFFSET(function) \ | ||
111 | (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ | ||
112 | (function * 0x8))) | ||
113 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ | ||
114 | (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff) | ||
115 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ | ||
116 | (IS_E1H_OFFSET ? 0xa000 : 0x1000) | ||
117 | #define TSTORM_ASSERT_LIST_OFFSET(idx) \ | ||
118 | (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | ||
119 | #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ | ||
120 | (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \ | ||
121 | : (0x9c0 + (port * 0x120) + (client_id * 0x10))) | ||
122 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ | ||
123 | (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff) | ||
124 | #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \ | 99 | #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \ |
125 | (IS_E1H_OFFSET ? 0x1eda : 0xffffffff) | 100 | (IRO[105].base) |
126 | #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ | 101 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ |
127 | (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ | 102 | (IRO[96].base + ((pfId) * IRO[96].m1)) |
128 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | 103 | #define TSTORM_FUNC_EN_OFFSET(funcId) \ |
129 | 0x28) + (index * 0x4))) | 104 | (IRO[101].base + ((funcId) * IRO[101].m1)) |
130 | #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ | 105 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ |
131 | (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \ | 106 | (IRO[195].base + ((pfId) * IRO[195].m1)) |
132 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | 107 | #define TSTORM_FUNCTION_MODE_OFFSET (IRO[103].base) |
133 | #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ | 108 | #define TSTORM_INDIRECTION_TABLE_OFFSET(pfId) \ |
134 | (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ | 109 | (IRO[91].base + ((pfId) * IRO[91].m1)) |
135 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | 110 | #define TSTORM_INDIRECTION_TABLE_SIZE (IRO[91].size) |
136 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | 111 | #define \ |
137 | (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \ | 112 | TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfId, iscsiConBufPblEntry) \ |
138 | (function * 0x8))) | 113 | (IRO[260].base + ((pfId) * IRO[260].m1) + ((iscsiConBufPblEntry) \ |
139 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ | 114 | * IRO[260].m2)) |
140 | (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \ | 115 | #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ |
141 | (function * 0x40))) | 116 | (IRO[264].base + ((pfId) * IRO[264].m1)) |
142 | #define TSTORM_FUNCTION_MODE_OFFSET \ | 117 | #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \ |
143 | (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff) | 118 | (IRO[265].base + ((pfId) * IRO[265].m1)) |
144 | #define TSTORM_HC_BTR_OFFSET(port) \ | 119 | #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \ |
145 | (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) | 120 | (IRO[266].base + ((pfId) * IRO[266].m1)) |
146 | #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ | 121 | #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \ |
147 | (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ | 122 | (IRO[267].base + ((pfId) * IRO[267].m1)) |
148 | (function * 0x80))) | 123 | #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
149 | #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 | 124 | (IRO[263].base + ((pfId) * IRO[263].m1)) |
150 | #define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \ | 125 | #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
151 | (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \ | 126 | (IRO[262].base + ((pfId) * IRO[262].m1)) |
152 | : (0x4c30 + (function * 0x40) + (pblEntry * 0x8))) | 127 | #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
153 | #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ | 128 | (IRO[261].base + ((pfId) * IRO[261].m1)) |
154 | (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \ | 129 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ |
155 | (function * 0x8))) | 130 | (IRO[259].base + ((pfId) * IRO[259].m1)) |
156 | #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | 131 | #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ |
157 | (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \ | 132 | (IRO[269].base + ((pfId) * IRO[269].m1)) |
158 | (function * 0x8))) | 133 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ |
159 | #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | 134 | (IRO[256].base + ((pfId) * IRO[256].m1)) |
160 | (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \ | 135 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ |
161 | (function * 0x8))) | 136 | (IRO[257].base + ((pfId) * IRO[257].m1)) |
162 | #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | 137 | #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ |
163 | (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \ | 138 | (IRO[258].base + ((pfId) * IRO[258].m1)) |
164 | (function * 0x8))) | 139 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ |
165 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \ | 140 | (IRO[196].base + ((pfId) * IRO[196].m1)) |
166 | (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \ | 141 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(portId, tStatCntId) \ |
167 | (function * 0x8))) | 142 | (IRO[100].base + ((portId) * IRO[100].m1) + ((tStatCntId) * \ |
168 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ | 143 | IRO[100].m2)) |
169 | (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \ | 144 | #define TSTORM_STATS_FLAGS_OFFSET(pfId) \ |
170 | (function * 0x8))) | 145 | (IRO[95].base + ((pfId) * IRO[95].m1)) |
171 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \ | 146 | #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ |
172 | (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \ | 147 | (IRO[211].base + ((pfId) * IRO[211].m1)) |
173 | (function * 0x8))) | 148 | #define TSTORM_VF_TO_PF_OFFSET(funcId) \ |
174 | #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \ | 149 | (IRO[102].base + ((funcId) * IRO[102].m1)) |
175 | (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \ | 150 | #define USTORM_AGG_DATA_OFFSET (IRO[201].base) |
176 | (function * 0x8))) | 151 | #define USTORM_AGG_DATA_SIZE (IRO[201].size) |
177 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ | 152 | #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[170].base) |
178 | (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \ | 153 | #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ |
179 | (function * 0x40))) | 154 | (IRO[169].base + ((assertListEntry) * IRO[169].m1)) |
180 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | 155 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ |
181 | (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \ | 156 | (IRO[178].base + ((portId) * IRO[178].m1)) |
182 | 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40))) | 157 | #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ |
183 | #define TSTORM_STATS_FLAGS_OFFSET(function) \ | 158 | (IRO[172].base + ((pfId) * IRO[172].m1)) |
184 | (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \ | 159 | #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ |
185 | (function * 0x8))) | 160 | (IRO[313].base + ((pfId) * IRO[313].m1)) |
186 | #define TSTORM_TCP_MAX_CWND_OFFSET(function) \ | 161 | #define USTORM_FUNC_EN_OFFSET(funcId) \ |
187 | (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \ | 162 | (IRO[174].base + ((funcId) * IRO[174].m1)) |
188 | (function * 0x8))) | 163 | #define USTORM_FUNCTION_MODE_OFFSET (IRO[177].base) |
189 | #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000) | 164 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ |
190 | #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000) | 165 | (IRO[277].base + ((pfId) * IRO[277].m1)) |
191 | #define USTORM_ASSERT_LIST_INDEX_OFFSET \ | 166 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ |
192 | (IS_E1H_OFFSET ? 0x8000 : 0x1000) | 167 | (IRO[278].base + ((pfId) * IRO[278].m1)) |
193 | #define USTORM_ASSERT_LIST_OFFSET(idx) \ | 168 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ |
194 | (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | 169 | (IRO[282].base + ((pfId) * IRO[282].m1)) |
195 | #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ | 170 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ |
196 | (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \ | 171 | (IRO[279].base + ((pfId) * IRO[279].m1)) |
197 | (0x4010 + (port * 0x360) + (clientId * 0x30))) | 172 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
198 | #define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \ | 173 | (IRO[275].base + ((pfId) * IRO[275].m1)) |
199 | (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \ | 174 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
200 | (0x4028 + (port * 0x360) + (clientId * 0x30))) | 175 | (IRO[274].base + ((pfId) * IRO[274].m1)) |
201 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \ | 176 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
202 | (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff) | 177 | (IRO[273].base + ((pfId) * IRO[273].m1)) |
203 | #define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ | 178 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ |
204 | (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \ | 179 | (IRO[276].base + ((pfId) * IRO[276].m1)) |
205 | 0xffffffff) | 180 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ |
206 | #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | 181 | (IRO[280].base + ((pfId) * IRO[280].m1)) |
207 | (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \ | 182 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ |
208 | (function * 0x8))) | 183 | (IRO[281].base + ((pfId) * IRO[281].m1)) |
209 | #define USTORM_FUNCTION_MODE_OFFSET \ | 184 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ |
210 | (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) | 185 | (IRO[176].base + ((pfId) * IRO[176].m1)) |
211 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \ | 186 | #define USTORM_PER_COUNTER_ID_STATS_OFFSET(portId, uStatCntId) \ |
212 | (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \ | 187 | (IRO[173].base + ((portId) * IRO[173].m1) + ((uStatCntId) * \ |
213 | (function * 0x8))) | 188 | IRO[173].m2)) |
214 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \ | 189 | #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ |
215 | (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \ | 190 | (IRO[204].base + ((portId) * IRO[204].m1) + ((clientId) * \ |
216 | (function * 0x8))) | 191 | IRO[204].m2)) |
217 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \ | 192 | #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ |
218 | (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \ | 193 | (IRO[205].base + ((qzoneId) * IRO[205].m1)) |
219 | (function * 0x8))) | 194 | #define USTORM_STATS_FLAGS_OFFSET(pfId) \ |
220 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \ | 195 | (IRO[171].base + ((pfId) * IRO[171].m1)) |
221 | (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \ | 196 | #define USTORM_TPA_BTR_OFFSET (IRO[202].base) |
222 | (function * 0x8))) | 197 | #define USTORM_TPA_BTR_SIZE (IRO[202].size) |
223 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | 198 | #define USTORM_VF_TO_PF_OFFSET(funcId) \ |
224 | (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \ | 199 | (IRO[175].base + ((funcId) * IRO[175].m1)) |
225 | (function * 0x8))) | 200 | #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[59].base) |
226 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | 201 | #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[58].base) |
227 | (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \ | 202 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[54].base) |
228 | (function * 0x8))) | 203 | #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ |
229 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | 204 | (IRO[53].base + ((assertListEntry) * IRO[53].m1)) |
230 | (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \ | 205 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ |
231 | (function * 0x8))) | 206 | (IRO[47].base + ((portId) * IRO[47].m1)) |
232 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ | 207 | #define XSTORM_E1HOV_OFFSET(pfId) \ |
233 | (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \ | 208 | (IRO[55].base + ((pfId) * IRO[55].m1)) |
234 | (function * 0x8))) | 209 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(pfId) \ |
235 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \ | 210 | (IRO[45].base + ((pfId) * IRO[45].m1)) |
236 | (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \ | 211 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ |
237 | (function * 0x8))) | 212 | (IRO[49].base + ((pfId) * IRO[49].m1)) |
238 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \ | 213 | #define XSTORM_FUNC_EN_OFFSET(funcId) \ |
239 | (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \ | 214 | (IRO[51].base + ((funcId) * IRO[51].m1)) |
240 | (function * 0x8))) | 215 | #define XSTORM_FUNCTION_MODE_OFFSET (IRO[56].base) |
241 | #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ | 216 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ |
242 | (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \ | 217 | (IRO[290].base + ((pfId) * IRO[290].m1)) |
243 | (0x4018 + (port * 0x360) + (clientId * 0x30))) | 218 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ |
244 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ | 219 | (IRO[293].base + ((pfId) * IRO[293].m1)) |
245 | (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \ | 220 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ |
246 | (function * 0x8))) | 221 | (IRO[294].base + ((pfId) * IRO[294].m1)) |
247 | #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | 222 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ |
248 | (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ | 223 | (IRO[295].base + ((pfId) * IRO[295].m1)) |
249 | 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28))) | 224 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ |
250 | #define USTORM_RX_PRODS_OFFSET(port, client_id) \ | 225 | (IRO[296].base + ((pfId) * IRO[296].m1)) |
251 | (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \ | 226 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ |
252 | : (0x4000 + (port * 0x360) + (client_id * 0x30))) | 227 | (IRO[297].base + ((pfId) * IRO[297].m1)) |
253 | #define USTORM_STATS_FLAGS_OFFSET(function) \ | 228 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ |
254 | (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \ | 229 | (IRO[298].base + ((pfId) * IRO[298].m1)) |
255 | (function * 0x8))) | 230 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ |
256 | #define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095) | 231 | (IRO[299].base + ((pfId) * IRO[299].m1)) |
257 | #define USTORM_TPA_BTR_SIZE 0x1 | 232 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
258 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ | 233 | (IRO[289].base + ((pfId) * IRO[289].m1)) |
259 | (IS_E1H_OFFSET ? 0x9000 : 0x1000) | 234 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
260 | #define XSTORM_ASSERT_LIST_OFFSET(idx) \ | 235 | (IRO[288].base + ((pfId) * IRO[288].m1)) |
261 | (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) | 236 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
262 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ | 237 | (IRO[287].base + ((pfId) * IRO[287].m1)) |
263 | (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50))) | 238 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ |
264 | #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ | 239 | (IRO[292].base + ((pfId) * IRO[292].m1)) |
265 | (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ | 240 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ |
266 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | 241 | (IRO[291].base + ((pfId) * IRO[291].m1)) |
267 | 0x28) + (index * 0x4))) | 242 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ |
268 | #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ | 243 | (IRO[286].base + ((pfId) * IRO[286].m1)) |
269 | (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \ | 244 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ |
270 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | 245 | (IRO[285].base + ((pfId) * IRO[285].m1)) |
271 | #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ | 246 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ |
272 | (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ | 247 | (IRO[284].base + ((pfId) * IRO[284].m1)) |
273 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | 248 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ |
274 | #define XSTORM_E1HOV_OFFSET(function) \ | 249 | (IRO[283].base + ((pfId) * IRO[283].m1)) |
275 | (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff) | 250 | #define XSTORM_PATH_ID_OFFSET (IRO[65].base) |
276 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ | 251 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(portId, xStatCntId) \ |
277 | (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \ | 252 | (IRO[50].base + ((portId) * IRO[50].m1) + ((xStatCntId) * \ |
278 | (function * 0x8))) | 253 | IRO[50].m2)) |
279 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ | 254 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ |
280 | (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \ | 255 | (IRO[48].base + ((pfId) * IRO[48].m1)) |
281 | (function * 0x90))) | 256 | #define XSTORM_SPQ_DATA_OFFSET(funcId) \ |
282 | #define XSTORM_FUNCTION_MODE_OFFSET \ | 257 | (IRO[32].base + ((funcId) * IRO[32].m1)) |
283 | (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff) | 258 | #define XSTORM_SPQ_DATA_SIZE (IRO[32].size) |
284 | #define XSTORM_HC_BTR_OFFSET(port) \ | 259 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ |
285 | (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) | 260 | (IRO[30].base + ((funcId) * IRO[30].m1)) |
286 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \ | 261 | #define XSTORM_SPQ_PROD_OFFSET(funcId) \ |
287 | (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \ | 262 | (IRO[31].base + ((funcId) * IRO[31].m1)) |
288 | (function * 0x8))) | 263 | #define XSTORM_STATS_FLAGS_OFFSET(pfId) \ |
289 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \ | 264 | (IRO[43].base + ((pfId) * IRO[43].m1)) |
290 | (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \ | 265 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ |
291 | (function * 0x8))) | 266 | (IRO[206].base + ((portId) * IRO[206].m1)) |
292 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \ | 267 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ |
293 | (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \ | 268 | (IRO[207].base + ((portId) * IRO[207].m1)) |
294 | (function * 0x8))) | 269 | #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ |
295 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \ | 270 | (IRO[209].base + (((pfId)>>1) * IRO[209].m1) + (((pfId)&1) * \ |
296 | (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \ | 271 | IRO[209].m2)) |
297 | (function * 0x8))) | 272 | #define XSTORM_VF_TO_PF_OFFSET(funcId) \ |
298 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \ | 273 | (IRO[52].base + ((funcId) * IRO[52].m1)) |
299 | (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \ | ||
300 | (function * 0x8))) | ||
301 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \ | ||
302 | (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \ | ||
303 | (function * 0x8))) | ||
304 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \ | ||
305 | (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \ | ||
306 | (function * 0x8))) | ||
307 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \ | ||
308 | (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \ | ||
309 | (function * 0x8))) | ||
310 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \ | ||
311 | (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \ | ||
312 | (function * 0x8))) | ||
313 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \ | ||
314 | (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \ | ||
315 | (function * 0x8))) | ||
316 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \ | ||
317 | (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \ | ||
318 | (function * 0x8))) | ||
319 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \ | ||
320 | (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \ | ||
321 | (function * 0x8))) | ||
322 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \ | ||
323 | (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \ | ||
324 | (function * 0x8))) | ||
325 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \ | ||
326 | (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \ | ||
327 | (function * 0x8))) | ||
328 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \ | ||
329 | (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \ | ||
330 | (function * 0x8))) | ||
331 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \ | ||
332 | (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \ | ||
333 | (function * 0x8))) | ||
334 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \ | ||
335 | (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \ | ||
336 | (function * 0x8))) | ||
337 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ | ||
338 | (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \ | ||
339 | 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30))) | ||
340 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ | ||
341 | (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \ | ||
342 | (function * 0x90))) | ||
343 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ | ||
344 | (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ | ||
345 | (function * 0x10))) | ||
346 | #define XSTORM_SPQ_PROD_OFFSET(function) \ | ||
347 | (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ | ||
348 | (function * 0x10))) | ||
349 | #define XSTORM_STATS_FLAGS_OFFSET(function) \ | ||
350 | (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \ | ||
351 | (function * 0x8))) | ||
352 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \ | ||
353 | (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8))) | ||
354 | #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \ | ||
355 | (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8))) | ||
356 | #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \ | ||
357 | (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \ | ||
358 | * 0x4)) : (0x1978 + (function * 0x4))) | ||
359 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 | 274 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 |
360 | 275 | ||
361 | /** | ||
362 | * This file defines HSI constants for the ETH flow | ||
363 | */ | ||
364 | #ifdef _EVEREST_MICROCODE | ||
365 | #include "microcode_constants.h" | ||
366 | #include "eth_rx_bd.h" | ||
367 | #include "eth_tx_bd.h" | ||
368 | #include "eth_rx_cqe.h" | ||
369 | #include "eth_rx_sge.h" | ||
370 | #include "eth_rx_cqe_next_page.h" | ||
371 | #endif | ||
372 | |||
373 | /* RSS hash types */ | 276 | /* RSS hash types */ |
374 | #define DEFAULT_HASH_TYPE 0 | 277 | #define DEFAULT_HASH_TYPE 0 |
375 | #define IPV4_HASH_TYPE 1 | 278 | #define IPV4_HASH_TYPE 1 |
@@ -389,11 +292,17 @@ | |||
389 | #define U_ETH_NUM_OF_SGES_TO_FETCH 8 | 292 | #define U_ETH_NUM_OF_SGES_TO_FETCH 8 |
390 | #define U_ETH_MAX_SGES_FOR_PACKET 3 | 293 | #define U_ETH_MAX_SGES_FOR_PACKET 3 |
391 | 294 | ||
295 | /*Tx params*/ | ||
296 | #define X_ETH_NO_VLAN 0 | ||
297 | #define X_ETH_OUTBAND_VLAN 1 | ||
298 | #define X_ETH_INBAND_VLAN 2 | ||
392 | /* Rx ring params */ | 299 | /* Rx ring params */ |
393 | #define U_ETH_LOCAL_BD_RING_SIZE 8 | 300 | #define U_ETH_LOCAL_BD_RING_SIZE 8 |
394 | #define U_ETH_LOCAL_SGE_RING_SIZE 10 | 301 | #define U_ETH_LOCAL_SGE_RING_SIZE 10 |
395 | #define U_ETH_SGL_SIZE 8 | 302 | #define U_ETH_SGL_SIZE 8 |
396 | 303 | /* The fw will padd the buffer with this value, so the IP header \ | |
304 | will be align to 4 Byte */ | ||
305 | #define IP_HEADER_ALIGNMENT_PADDING 2 | ||
397 | 306 | ||
398 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ | 307 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ |
399 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) | 308 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) |
@@ -409,16 +318,15 @@ | |||
409 | #define U_ETH_UNDEFINED_Q 0xFF | 318 | #define U_ETH_UNDEFINED_Q 0xFF |
410 | 319 | ||
411 | /* values of command IDs in the ramrod message */ | 320 | /* values of command IDs in the ramrod message */ |
412 | #define RAMROD_CMD_ID_ETH_PORT_SETUP 80 | 321 | #define RAMROD_CMD_ID_ETH_UNUSED 0 |
413 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85 | 322 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 1 |
414 | #define RAMROD_CMD_ID_ETH_STAT_QUERY 90 | 323 | #define RAMROD_CMD_ID_ETH_UPDATE 2 |
415 | #define RAMROD_CMD_ID_ETH_UPDATE 100 | 324 | #define RAMROD_CMD_ID_ETH_HALT 3 |
416 | #define RAMROD_CMD_ID_ETH_HALT 105 | 325 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 4 |
417 | #define RAMROD_CMD_ID_ETH_SET_MAC 110 | 326 | #define RAMROD_CMD_ID_ETH_ACTIVATE 5 |
418 | #define RAMROD_CMD_ID_ETH_CFC_DEL 115 | 327 | #define RAMROD_CMD_ID_ETH_DEACTIVATE 6 |
419 | #define RAMROD_CMD_ID_ETH_PORT_DEL 120 | 328 | #define RAMROD_CMD_ID_ETH_EMPTY 7 |
420 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125 | 329 | #define RAMROD_CMD_ID_ETH_TERMINATE 8 |
421 | |||
422 | 330 | ||
423 | /* command values for set mac command */ | 331 | /* command values for set mac command */ |
424 | #define T_ETH_MAC_COMMAND_SET 0 | 332 | #define T_ETH_MAC_COMMAND_SET 0 |
@@ -431,7 +339,9 @@ | |||
431 | 339 | ||
432 | /* Maximal L2 clients supported */ | 340 | /* Maximal L2 clients supported */ |
433 | #define ETH_MAX_RX_CLIENTS_E1 18 | 341 | #define ETH_MAX_RX_CLIENTS_E1 18 |
434 | #define ETH_MAX_RX_CLIENTS_E1H 26 | 342 | #define ETH_MAX_RX_CLIENTS_E1H 28 |
343 | |||
344 | #define MAX_STAT_COUNTER_ID ETH_MAX_RX_CLIENTS_E1H | ||
435 | 345 | ||
436 | /* Maximal aggregation queues supported */ | 346 | /* Maximal aggregation queues supported */ |
437 | #define ETH_MAX_AGGREGATION_QUEUES_E1 32 | 347 | #define ETH_MAX_AGGREGATION_QUEUES_E1 32 |
@@ -443,6 +353,20 @@ | |||
443 | #define ETH_RSS_MODE_VLAN_PRI 2 | 353 | #define ETH_RSS_MODE_VLAN_PRI 2 |
444 | #define ETH_RSS_MODE_E1HOV_PRI 3 | 354 | #define ETH_RSS_MODE_E1HOV_PRI 3 |
445 | #define ETH_RSS_MODE_IP_DSCP 4 | 355 | #define ETH_RSS_MODE_IP_DSCP 4 |
356 | #define ETH_RSS_MODE_E2_INTEG 5 | ||
357 | |||
358 | |||
359 | /* ETH vlan filtering modes */ | ||
360 | #define ETH_VLAN_FILTER_ANY_VLAN 0 /* Don't filter by vlan */ | ||
361 | #define ETH_VLAN_FILTER_SPECIFIC_VLAN \ | ||
362 | 1 /* Only the vlan_id is allowed */ | ||
363 | #define ETH_VLAN_FILTER_CLASSIFY \ | ||
364 | 2 /* vlan will be added to CAM for classification */ | ||
365 | |||
366 | /* Fast path CQE selection */ | ||
367 | #define ETH_FP_CQE_REGULAR 0 | ||
368 | #define ETH_FP_CQE_SGL 1 | ||
369 | #define ETH_FP_CQE_RAW 2 | ||
446 | 370 | ||
447 | 371 | ||
448 | /** | 372 | /** |
@@ -458,6 +382,7 @@ | |||
458 | #define RESERVED_CONNECTION_TYPE_0 5 | 382 | #define RESERVED_CONNECTION_TYPE_0 5 |
459 | #define RESERVED_CONNECTION_TYPE_1 6 | 383 | #define RESERVED_CONNECTION_TYPE_1 6 |
460 | #define RESERVED_CONNECTION_TYPE_2 7 | 384 | #define RESERVED_CONNECTION_TYPE_2 7 |
385 | #define NONE_CONNECTION_TYPE 8 | ||
461 | 386 | ||
462 | 387 | ||
463 | #define PROTOCOL_STATE_BIT_OFFSET 6 | 388 | #define PROTOCOL_STATE_BIT_OFFSET 6 |
@@ -466,6 +391,16 @@ | |||
466 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | 391 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) |
467 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | 392 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) |
468 | 393 | ||
394 | /* values of command IDs in the ramrod message */ | ||
395 | #define RAMROD_CMD_ID_COMMON_FUNCTION_START 1 | ||
396 | #define RAMROD_CMD_ID_COMMON_FUNCTION_STOP 2 | ||
397 | #define RAMROD_CMD_ID_COMMON_CFC_DEL 3 | ||
398 | #define RAMROD_CMD_ID_COMMON_CFC_DEL_WB 4 | ||
399 | #define RAMROD_CMD_ID_COMMON_SET_MAC 5 | ||
400 | #define RAMROD_CMD_ID_COMMON_STAT_QUERY 6 | ||
401 | #define RAMROD_CMD_ID_COMMON_STOP_TRAFFIC 7 | ||
402 | #define RAMROD_CMD_ID_COMMON_START_TRAFFIC 8 | ||
403 | |||
469 | /* microcode fixed page page size 4K (chains and ring segments) */ | 404 | /* microcode fixed page page size 4K (chains and ring segments) */ |
470 | #define MC_PAGE_SIZE 4096 | 405 | #define MC_PAGE_SIZE 4096 |
471 | 406 | ||
@@ -473,46 +408,26 @@ | |||
473 | /* Host coalescing constants */ | 408 | /* Host coalescing constants */ |
474 | #define HC_IGU_BC_MODE 0 | 409 | #define HC_IGU_BC_MODE 0 |
475 | #define HC_IGU_NBC_MODE 1 | 410 | #define HC_IGU_NBC_MODE 1 |
411 | /* Host coalescing constants. E1 includes E1H as well */ | ||
412 | |||
413 | /* Number of indices per slow-path SB */ | ||
414 | #define HC_SP_SB_MAX_INDICES 16 | ||
415 | |||
416 | /* Number of indices per SB */ | ||
417 | #define HC_SB_MAX_INDICES_E1X 8 | ||
418 | #define HC_SB_MAX_INDICES_E2 8 | ||
419 | |||
420 | #define HC_SB_MAX_SB_E1X 32 | ||
421 | #define HC_SB_MAX_SB_E2 136 | ||
422 | |||
423 | #define HC_SP_SB_ID 0xde | ||
476 | 424 | ||
477 | #define HC_REGULAR_SEGMENT 0 | 425 | #define HC_REGULAR_SEGMENT 0 |
478 | #define HC_DEFAULT_SEGMENT 1 | 426 | #define HC_DEFAULT_SEGMENT 1 |
427 | #define HC_SB_MAX_SM 2 | ||
479 | 428 | ||
480 | /* index numbers */ | 429 | #define HC_SB_MAX_DYNAMIC_INDICES 4 |
481 | #define HC_USTORM_DEF_SB_NUM_INDICES 8 | 430 | #define HC_FUNCTION_DISABLED 0xff |
482 | #define HC_CSTORM_DEF_SB_NUM_INDICES 8 | ||
483 | #define HC_XSTORM_DEF_SB_NUM_INDICES 4 | ||
484 | #define HC_TSTORM_DEF_SB_NUM_INDICES 4 | ||
485 | #define HC_USTORM_SB_NUM_INDICES 4 | ||
486 | #define HC_CSTORM_SB_NUM_INDICES 4 | ||
487 | |||
488 | /* index values - which counter to update */ | ||
489 | |||
490 | #define HC_INDEX_U_TOE_RX_CQ_CONS 0 | ||
491 | #define HC_INDEX_U_ETH_RX_CQ_CONS 1 | ||
492 | #define HC_INDEX_U_ETH_RX_BD_CONS 2 | ||
493 | #define HC_INDEX_U_FCOE_EQ_CONS 3 | ||
494 | |||
495 | #define HC_INDEX_C_TOE_TX_CQ_CONS 0 | ||
496 | #define HC_INDEX_C_ETH_TX_CQ_CONS 1 | ||
497 | #define HC_INDEX_C_ISCSI_EQ_CONS 2 | ||
498 | |||
499 | #define HC_INDEX_DEF_X_SPQ_CONS 0 | ||
500 | |||
501 | #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0 | ||
502 | #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1 | ||
503 | #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2 | ||
504 | #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 | ||
505 | #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 | ||
506 | #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 | ||
507 | #define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6 | ||
508 | |||
509 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 | ||
510 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 | ||
511 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 | ||
512 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 | ||
513 | #define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4 | ||
514 | #define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5 | ||
515 | |||
516 | /* used by the driver to get the SB offset */ | 431 | /* used by the driver to get the SB offset */ |
517 | #define USTORM_ID 0 | 432 | #define USTORM_ID 0 |
518 | #define CSTORM_ID 1 | 433 | #define CSTORM_ID 1 |
@@ -529,45 +444,17 @@ | |||
529 | 444 | ||
530 | 445 | ||
531 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | 446 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ |
532 | #define EMULATION_FREQUENCY_FACTOR 1600 | ||
533 | #define FPGA_FREQUENCY_FACTOR 100 | ||
534 | 447 | ||
535 | #define TIMERS_TICK_SIZE_CHIP (1e-3) | 448 | #define TIMERS_TICK_SIZE_CHIP (1e-3) |
536 | #define TIMERS_TICK_SIZE_EMUL \ | ||
537 | ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR))) | ||
538 | #define TIMERS_TICK_SIZE_FPGA \ | ||
539 | ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR))) | ||
540 | 449 | ||
541 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) | 450 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) |
542 | #define TSEMI_CLK1_RESUL_EMUL \ | ||
543 | ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
544 | #define TSEMI_CLK1_RESUL_FPGA \ | ||
545 | ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
546 | |||
547 | #define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP) | ||
548 | #define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL) | ||
549 | #define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA) | ||
550 | 451 | ||
551 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) | 452 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) |
552 | #define XSEMI_CLK1_RESUL_EMUL \ | ||
553 | ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
554 | #define XSEMI_CLK1_RESUL_FPGA \ | ||
555 | ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
556 | |||
557 | #define XSEMI_CLK2_RESUL_CHIP (1e-6) | ||
558 | #define XSEMI_CLK2_RESUL_EMUL \ | ||
559 | ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
560 | #define XSEMI_CLK2_RESUL_FPGA \ | ||
561 | ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
562 | 453 | ||
563 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) | 454 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) |
564 | #define SDM_TIMER_TICK_RESUL_EMUL \ | ||
565 | ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | ||
566 | #define SDM_TIMER_TICK_RESUL_FPGA \ | ||
567 | ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | ||
568 | |||
569 | 455 | ||
570 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | 456 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ |
457 | |||
571 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 | 458 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 |
572 | #define XSTORM_IP_ID_ROLL_ALL 0 | 459 | #define XSTORM_IP_ID_ROLL_ALL 0 |
573 | 460 | ||
@@ -576,10 +463,36 @@ | |||
576 | #define NUM_OF_PROTOCOLS 4 | 463 | #define NUM_OF_PROTOCOLS 4 |
577 | #define NUM_OF_SAFC_BITS 16 | 464 | #define NUM_OF_SAFC_BITS 16 |
578 | #define MAX_COS_NUMBER 4 | 465 | #define MAX_COS_NUMBER 4 |
579 | #define MAX_T_STAT_COUNTER_ID 18 | ||
580 | #define MAX_X_STAT_COUNTER_ID 18 | ||
581 | #define MAX_U_STAT_COUNTER_ID 18 | ||
582 | 466 | ||
467 | #define FAIRNESS_COS_WRR_MODE 0 | ||
468 | #define FAIRNESS_COS_ETS_MODE 1 | ||
469 | |||
470 | |||
471 | /* Priority Flow Control (PFC) */ | ||
472 | #define MAX_PFC_PRIORITIES 8 | ||
473 | #define MAX_PFC_TRAFFIC_TYPES 8 | ||
474 | |||
475 | /* Available Traffic Types for Link Layer Flow Control */ | ||
476 | #define LLFC_TRAFFIC_TYPE_NW 0 | ||
477 | #define LLFC_TRAFFIC_TYPE_FCOE 1 | ||
478 | #define LLFC_TRAFFIC_TYPE_ISCSI 2 | ||
479 | /***************** START OF E2 INTEGRATION \ | ||
480 | CODE***************************************/ | ||
481 | #define LLFC_TRAFFIC_TYPE_NW_COS1_E2INTEG 3 | ||
482 | /***************** END OF E2 INTEGRATION \ | ||
483 | CODE***************************************/ | ||
484 | #define LLFC_TRAFFIC_TYPE_MAX 4 | ||
485 | |||
486 | /* used by array traffic_type_to_priority[] to mark traffic type \ | ||
487 | that is not mapped to priority*/ | ||
488 | #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF | ||
489 | |||
490 | #define LLFC_MODE_NONE 0 | ||
491 | #define LLFC_MODE_PFC 1 | ||
492 | #define LLFC_MODE_SAFC 2 | ||
493 | |||
494 | #define DCB_DISABLED 0 | ||
495 | #define DCB_ENABLED 1 | ||
583 | 496 | ||
584 | #define UNKNOWN_ADDRESS 0 | 497 | #define UNKNOWN_ADDRESS 0 |
585 | #define UNICAST_ADDRESS 1 | 498 | #define UNICAST_ADDRESS 1 |
@@ -587,8 +500,32 @@ | |||
587 | #define BROADCAST_ADDRESS 3 | 500 | #define BROADCAST_ADDRESS 3 |
588 | 501 | ||
589 | #define SINGLE_FUNCTION 0 | 502 | #define SINGLE_FUNCTION 0 |
590 | #define MULTI_FUNCTION 1 | 503 | #define MULTI_FUNCTION_SD 1 |
504 | #define MULTI_FUNCTION_SI 2 | ||
591 | 505 | ||
592 | #define IP_V4 0 | 506 | #define IP_V4 0 |
593 | #define IP_V6 1 | 507 | #define IP_V6 1 |
594 | 508 | ||
509 | |||
510 | #define C_ERES_PER_PAGE \ | ||
511 | (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) | ||
512 | #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) | ||
513 | |||
514 | #define EVENT_RING_OPCODE_VF_PF_CHANNEL 0 | ||
515 | #define EVENT_RING_OPCODE_FUNCTION_START 1 | ||
516 | #define EVENT_RING_OPCODE_FUNCTION_STOP 2 | ||
517 | #define EVENT_RING_OPCODE_CFC_DEL 3 | ||
518 | #define EVENT_RING_OPCODE_CFC_DEL_WB 4 | ||
519 | #define EVENT_RING_OPCODE_SET_MAC 5 | ||
520 | #define EVENT_RING_OPCODE_STAT_QUERY 6 | ||
521 | #define EVENT_RING_OPCODE_STOP_TRAFFIC 7 | ||
522 | #define EVENT_RING_OPCODE_START_TRAFFIC 8 | ||
523 | #define EVENT_RING_OPCODE_FORWARD_SETUP 9 | ||
524 | |||
525 | #define VF_PF_CHANNEL_STATE_READY 0 | ||
526 | #define VF_PF_CHANNEL_STATE_WAITING_FOR_ACK 1 | ||
527 | |||
528 | #define VF_PF_CHANNEL_STATE_MAX_NUMBER 2 | ||
529 | |||
530 | |||
531 | #endif /* BNX2X_FW_DEFS_H */ | ||