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authorDmitry Kravkov <dmitry@broadcom.com>2011-06-13 21:34:02 -0400
committerDavid S. Miller <davem@conan.davemloft.net>2011-06-15 10:56:56 -0400
commit754a2f5220ac7d597454df3104cfce9c83d68df0 (patch)
treed00abd015be81f74128fa1f96a3de29e6332b7db /drivers/net/bnx2x/bnx2x_ethtool.c
parentef01854e24035a0b17ebeb98b05cfee2c8b36e02 (diff)
bnx2x: Cosmetic changes.
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_ethtool.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_ethtool.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c
index 965fb071fbe4..1a3ed418946d 100644
--- a/drivers/net/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/bnx2x/bnx2x_ethtool.c
@@ -762,7 +762,7 @@ static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
762 u32 val = 0; 762 u32 val = 0;
763 763
764 /* adjust timeout for emulation/FPGA */ 764 /* adjust timeout for emulation/FPGA */
765 count = NVRAM_TIMEOUT_COUNT; 765 count = BNX2X_NVRAM_TIMEOUT_COUNT;
766 if (CHIP_REV_IS_SLOW(bp)) 766 if (CHIP_REV_IS_SLOW(bp))
767 count *= 100; 767 count *= 100;
768 768
@@ -793,7 +793,7 @@ static int bnx2x_release_nvram_lock(struct bnx2x *bp)
793 u32 val = 0; 793 u32 val = 0;
794 794
795 /* adjust timeout for emulation/FPGA */ 795 /* adjust timeout for emulation/FPGA */
796 count = NVRAM_TIMEOUT_COUNT; 796 count = BNX2X_NVRAM_TIMEOUT_COUNT;
797 if (CHIP_REV_IS_SLOW(bp)) 797 if (CHIP_REV_IS_SLOW(bp))
798 count *= 100; 798 count *= 100;
799 799
@@ -861,7 +861,7 @@ static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
861 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 861 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
862 862
863 /* adjust timeout for emulation/FPGA */ 863 /* adjust timeout for emulation/FPGA */
864 count = NVRAM_TIMEOUT_COUNT; 864 count = BNX2X_NVRAM_TIMEOUT_COUNT;
865 if (CHIP_REV_IS_SLOW(bp)) 865 if (CHIP_REV_IS_SLOW(bp))
866 count *= 100; 866 count *= 100;
867 867
@@ -984,7 +984,7 @@ static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
984 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 984 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
985 985
986 /* adjust timeout for emulation/FPGA */ 986 /* adjust timeout for emulation/FPGA */
987 count = NVRAM_TIMEOUT_COUNT; 987 count = BNX2X_NVRAM_TIMEOUT_COUNT;
988 if (CHIP_REV_IS_SLOW(bp)) 988 if (CHIP_REV_IS_SLOW(bp))
989 count *= 100; 989 count *= 100;
990 990
@@ -1088,9 +1088,9 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1088 while ((written_so_far < buf_size) && (rc == 0)) { 1088 while ((written_so_far < buf_size) && (rc == 0)) {
1089 if (written_so_far == (buf_size - sizeof(u32))) 1089 if (written_so_far == (buf_size - sizeof(u32)))
1090 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1090 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1091 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) 1091 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1092 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1092 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1093 else if ((offset % NVRAM_PAGE_SIZE) == 0) 1093 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1094 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1094 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1095 1095
1096 memcpy(&val, data_buf, 4); 1096 memcpy(&val, data_buf, 4);