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authorEilon Greenstein <eilong@broadcom.com>2009-08-12 04:24:29 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-13 02:03:01 -0400
commitab6ad5a4875e99dffe957a411fe890402a91f67f (patch)
tree26bb0b2a38808f099c0719d5e54ceb3ccc835fa9 /drivers/net/bnx2x.h
parent9c63de6293775b537614550fd61075a33ada9469 (diff)
bnx2x: Whitespaces and comments
Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h38
1 files changed, 20 insertions, 18 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 97bc5e046f47..bbf842284ebb 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -314,9 +314,11 @@ struct bnx2x_fastpath {
314 __le16 *rx_cons_sb; 314 __le16 *rx_cons_sb;
315 __le16 *rx_bd_cons_sb; 315 __le16 *rx_bd_cons_sb;
316 316
317
317 unsigned long tx_pkt, 318 unsigned long tx_pkt,
318 rx_pkt, 319 rx_pkt,
319 rx_calls; 320 rx_calls;
321
320 /* TPA related */ 322 /* TPA related */
321 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; 323 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
322 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; 324 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -998,20 +1000,20 @@ struct bnx2x {
998#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1000#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
999#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1001#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1000 1002
1001 struct raw_op *init_ops; 1003 struct raw_op *init_ops;
1002 /* Init blocks offsets inside init_ops */ 1004 /* Init blocks offsets inside init_ops */
1003 u16 *init_ops_offsets; 1005 u16 *init_ops_offsets;
1004 /* Data blob - has 32 bit granularity */ 1006 /* Data blob - has 32 bit granularity */
1005 u32 *init_data; 1007 u32 *init_data;
1006 /* Zipped PRAM blobs - raw data */ 1008 /* Zipped PRAM blobs - raw data */
1007 const u8 *tsem_int_table_data; 1009 const u8 *tsem_int_table_data;
1008 const u8 *tsem_pram_data; 1010 const u8 *tsem_pram_data;
1009 const u8 *usem_int_table_data; 1011 const u8 *usem_int_table_data;
1010 const u8 *usem_pram_data; 1012 const u8 *usem_pram_data;
1011 const u8 *xsem_int_table_data; 1013 const u8 *xsem_int_table_data;
1012 const u8 *xsem_pram_data; 1014 const u8 *xsem_pram_data;
1013 const u8 *csem_int_table_data; 1015 const u8 *csem_int_table_data;
1014 const u8 *csem_pram_data; 1016 const u8 *csem_pram_data;
1015#define INIT_OPS(bp) (bp->init_ops) 1017#define INIT_OPS(bp) (bp->init_ops)
1016#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1018#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1017#define INIT_DATA(bp) (bp->init_data) 1019#define INIT_DATA(bp) (bp->init_data)
@@ -1024,7 +1026,7 @@ struct bnx2x {
1024#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1026#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1025#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1027#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1026 1028
1027 const struct firmware *firmware; 1029 const struct firmware *firmware;
1028}; 1030};
1029 1031
1030 1032
@@ -1111,9 +1113,9 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1111#define DMAE_COMP_VAL 0xe0d0d0ae 1113#define DMAE_COMP_VAL 0xe0d0d0ae
1112 1114
1113#define MAX_DMAE_C_PER_PORT 8 1115#define MAX_DMAE_C_PER_PORT 8
1114#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ 1116#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1115 BP_E1HVN(bp)) 1117 BP_E1HVN(bp))
1116#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ 1118#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1117 E1HVN_MAX) 1119 E1HVN_MAX)
1118 1120
1119 1121
@@ -1138,7 +1140,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1138 1140
1139 1141
1140/* must be used on a CID before placing it on a HW ring */ 1142/* must be used on a CID before placing it on a HW ring */
1141#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) 1143#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1144 (BP_E1HVN(bp) << 17) | (x))
1142 1145
1143#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1146#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1144#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1147#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
@@ -1226,8 +1229,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1226 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1229 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1227 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1230 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1228 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1231 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1229 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1232 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1230 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1233 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1231 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 1234 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1232 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 1235 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1233 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 1236 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
@@ -1255,7 +1258,6 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1255 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ 1258 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1256 (bp->multi_mode << \ 1259 (bp->multi_mode << \
1257 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) 1260 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1258
1259#define MULTI_MASK 0x7f 1261#define MULTI_MASK 0x7f
1260 1262
1261 1263