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authorYaniv Rosner <yanivr@broadcom.com>2008-06-23 23:27:52 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-23 23:27:52 -0400
commitc18487ee24381b40df3b8b4f54dd13ee9367a1ce (patch)
tree0c52df7c30f0789fd7509426c38b2d1551c444b9 /drivers/net/bnx2x.h
parentea4e040abc72f2dbbfdd8d04e271a18593ba72c7 (diff)
bnx2x: New link code
New Link code: Moving all the link related code (including the calculations, the initialization of the MAC and PHY and the external PHY's code) into a separated file. The changes from the code that used to be part of bnx2x.c (now called bnx2x_main.c) are: - Using separate structures for link inputs and link outputs to clearly identify what was configured and what is the outcome - Adding code to read external PHY FW version and print it as part of ethtool -i - Adding code to upgrade external PHY FW from ethtool -E with special magic number - Changing the link down indication to ERR level - Adding a lock on all PHY access to prevent an interrupt and setting changes to overlap - Adding support for emulation and FPGA (small chunk of code that really helps in the lab) - Adding support for 1G on BCM8706 PHY - Adding clear debug print incase of fan failure (the PHY type is now "failure") Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h180
1 files changed, 25 insertions, 155 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 8e68d06510a6..2a13defda8ab 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -90,6 +90,12 @@
90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
92 92
93#define REG_RD_DMAE(bp, offset, valp, len32) \
94 do { \
95 bnx2x_read_dmae(bp, offset, len32);\
96 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
97 } while (0)
98
93#define REG_WR_DMAE(bp, offset, val, len32) \ 99#define REG_WR_DMAE(bp, offset, val, len32) \
94 do { \ 100 do { \
95 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ 101 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
@@ -542,11 +548,8 @@ struct bnx2x {
542 int pm_cap; 548 int pm_cap;
543 int pcie_cap; 549 int pcie_cap;
544 550
545 /* Used to synchronize phy accesses */ 551 struct work_struct sp_task;
546 spinlock_t phy_lock; 552 struct work_struct reset_task;
547
548 struct work_struct reset_task;
549 struct work_struct sp_task;
550 553
551 struct timer_list timer; 554 struct timer_list timer;
552 int timer_interval; 555 int timer_interval;
@@ -568,6 +571,8 @@ struct bnx2x {
568#define CHIP_REV_FPGA 0x0000f000 571#define CHIP_REV_FPGA 0x0000f000
569#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ 572#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
570 (CHIP_REV(bp) == CHIP_REV_FPGA)) 573 (CHIP_REV(bp) == CHIP_REV_FPGA))
574#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL)
575#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA)
571 576
572#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 577#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
573#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) 578#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
@@ -578,84 +583,29 @@ struct bnx2x {
578 583
579 u32 hw_config; 584 u32 hw_config;
580 u32 board; 585 u32 board;
581 u32 serdes_config; 586
582 u32 lane_config; 587 struct link_params link_params;
583 u32 ext_phy_config; 588
584#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ 589 struct link_vars link_vars;
585 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 590
586#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ 591 u32 link_config;
587 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
588
589 u32 speed_cap_mask;
590 u32 link_config;
591#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
592#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
593#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
594#define SWITCH_CFG_ONE_TIME_DETECT \
595 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
596
597 u8 ser_lane;
598 u8 rx_lane_swap;
599 u8 tx_lane_swap;
600
601 u8 link_up;
602 u8 phy_link_up;
603 592
604 u32 supported; 593 u32 supported;
605/* link settings - missing defines */ 594/* link settings - missing defines */
606#define SUPPORTED_2500baseT_Full (1 << 15) 595#define SUPPORTED_2500baseT_Full (1 << 15)
607 596
608 u32 phy_flags;
609/*#define PHY_SERDES_FLAG 0x1*/
610#define PHY_BMAC_FLAG 0x2
611#define PHY_EMAC_FLAG 0x4
612#define PHY_XGXS_FLAG 0x8
613#define PHY_SGMII_FLAG 0x10
614#define PHY_INT_MODE_MASK_FLAG 0x300
615#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
616#define PHY_INT_MODE_LINK_READY_FLAG 0x200
617
618 u32 phy_addr; 597 u32 phy_addr;
598
599 /* used to synchronize phy accesses */
600 struct mutex phy_mutex;
601
619 u32 phy_id; 602 u32 phy_id;
620 603
621 u32 autoneg;
622#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
623#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
624#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
625#define AUTONEG_PARALLEL \
626 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
627#define AUTONEG_SGMII_FIBER_AUTODET \
628 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
629#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
630
631 u32 req_autoneg;
632#define AUTONEG_SPEED 0x1
633#define AUTONEG_FLOW_CTRL 0x2
634
635 u32 req_line_speed;
636/* link settings - missing defines */
637#define SPEED_12000 12000
638#define SPEED_12500 12500
639#define SPEED_13000 13000
640#define SPEED_15000 15000
641#define SPEED_16000 16000
642
643 u32 req_duplex;
644 u32 req_flow_ctrl;
645#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
646#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
647#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
648#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
649#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
650 604
651 u32 advertising; 605 u32 advertising;
652/* link settings - missing defines */ 606/* link settings - missing defines */
653#define ADVERTISED_2500baseT_Full (1 << 15) 607#define ADVERTISED_2500baseT_Full (1 << 15)
654 608
655 u32 link_status;
656 u32 line_speed;
657 u32 duplex;
658 u32 flow_ctrl;
659 609
660 u32 bc_ver; 610 u32 bc_ver;
661 611
@@ -765,6 +715,11 @@ struct bnx2x {
765 715
766#define DMAE_LEN32_MAX 0x400 716#define DMAE_LEN32_MAX 0x400
767 717
718void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
719void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
720 u32 len32);
721int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
722
768 723
769/* MC hsi */ 724/* MC hsi */
770#define RX_COPY_THRESH 92 725#define RX_COPY_THRESH 92
@@ -890,91 +845,6 @@ struct bnx2x {
890 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) 845 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
891 846
892 847
893#define MDIO_AN_CL73_OR_37_COMPLETE \
894 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
895 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
896
897#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
898 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
899#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
900 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
901#define GP_STATUS_SPEED_MASK \
902 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
903#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
904#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
905#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
906#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
907#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
908#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
909#define GP_STATUS_10G_HIG \
910 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
911#define GP_STATUS_10G_CX4 \
912 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
913#define GP_STATUS_12G_HIG \
914 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
915#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
916#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
917#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
918#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
919#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
920#define GP_STATUS_10G_KX4 \
921 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
922
923#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
924#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
925#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
926#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
927#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
928#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
929#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
930#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
931#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
932#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
933#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
934#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
935#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
936#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
937#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
938#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
939#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
940#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
941#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
942#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
943#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
944#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
945#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
946
947#define NIG_STATUS_XGXS0_LINK10G \
948 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
949#define NIG_STATUS_XGXS0_LINK_STATUS \
950 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
951#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
952 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
953#define NIG_STATUS_SERDES0_LINK_STATUS \
954 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
955#define NIG_MASK_MI_INT \
956 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
957#define NIG_MASK_XGXS0_LINK10G \
958 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
959#define NIG_MASK_XGXS0_LINK_STATUS \
960 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
961#define NIG_MASK_SERDES0_LINK_STATUS \
962 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
963
964#define XGXS_RESET_BITS \
965 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
966 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
967 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
970
971#define SERDES_RESET_BITS \
972 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
973 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
974 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
975 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
976
977
978#define BNX2X_MC_ASSERT_BITS \ 848#define BNX2X_MC_ASSERT_BITS \
979 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 849 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
980 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 850 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
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