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authorEilon Greenstein <eilong@broadcom.com>2008-08-13 18:58:49 -0400
committerDavid S. Miller <davem@davemloft.net>2008-08-13 19:05:36 -0400
commit3196a88a8593748bad24824ef5eb8e5aa99698c9 (patch)
tree2ed8c1557ec13fca018db1858b98ddd45697c7a6 /drivers/net/bnx2x.h
parentf0e53a847a4435f3226f5e385503f792f5f99ce2 (diff)
bnx2x: Minor code improvements
Minor code improvements Small changes to make the code a little bit more efficient and mostly more readable: - Using unified macros for EMAC_RD/WR which looks like normal REG_RD/WR - Removing the NIG_WR since it did nothing and was only confusing - On bnx2x_panic_dump, print only the used parts of the rings - define parameters only on the branch they are needed and not at the beginning of the function - using NETIF_MSG_INTR and not private BNX2X_MSG_SP for debug prints Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h23
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 98d6f85fdeb5..80f5179d636c 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -121,16 +121,7 @@
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122 122
123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124#define NIG_WR(reg, val) REG_WR(bp, reg, val) 124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
126#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
127
128
129#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
130
131#define for_each_nondefault_queue(bp, var) \
132 for (var = 1; var < bp->num_queues; var++)
133#define is_multi(bp) (bp->num_queues > 1)
134 125
135 126
136/* fast path */ 127/* fast path */
@@ -815,9 +806,6 @@ struct bnx2x {
815#define BP_FUNC(bp) (bp->func) 806#define BP_FUNC(bp) (bp->func)
816#define BP_E1HVN(bp) (bp->func >> 1) 807#define BP_E1HVN(bp) (bp->func >> 1)
817#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 808#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
818/* assorted E1HVN */
819#define IS_E1HMF(bp) (bp->e1hmf != 0)
820#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
821 809
822 int pm_cap; 810 int pm_cap;
823 int pcie_cap; 811 int pcie_cap;
@@ -842,6 +830,7 @@ struct bnx2x {
842 u32 mf_config; 830 u32 mf_config;
843 u16 e1hov; 831 u16 e1hov;
844 u8 e1hmf; 832 u8 e1hmf;
833#define IS_E1HMF(bp) (bp->e1hmf != 0)
845 834
846 u8 wol; 835 u8 wol;
847 836
@@ -872,6 +861,7 @@ struct bnx2x {
872#define BNX2X_STATE_ERROR 0xf000 861#define BNX2X_STATE_ERROR 0xf000
873 862
874 int num_queues; 863 int num_queues;
864#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
875 865
876 u32 rx_mode; 866 u32 rx_mode;
877#define BNX2X_RX_MODE_NONE 0 867#define BNX2X_RX_MODE_NONE 0
@@ -922,6 +912,13 @@ struct bnx2x {
922}; 912};
923 913
924 914
915#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
916
917#define for_each_nondefault_queue(bp, var) \
918 for (var = 1; var < bp->num_queues; var++)
919#define is_multi(bp) (bp->num_queues > 1)
920
921
925void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 922void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
926void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 923void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
927 u32 len32); 924 u32 len32);