[BNX2X]: Correct Link management

Properly protect PHY access between two devices on the same board with
a HW lock.

Use GPIO to clear all previous configurations before changing link
parameters.

Shut down the external PHY in case of fan failure.

Reducing the MDC/MDIO clock to 2.5MHz due to problems with some
devices.

Resolve the flow control response according to autoneg with external
PHY.

Unmasking all PHY interrupts in single write to prevent a race in the
interrupts order.

LASI indication fixes to work with peculiarities of PHYs.

Disable MAC RX to avoid a HW bug when closing the MAC under traffic.

Disable parallel detection on HiGig due to HW limitation.

Updating the shared memory structure to work with the current
bootcode.

Signed-off-by: Eliezer Tamir <eliezert@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 18 insertions, 16 deletions

diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index ea9100855c5c..dc423e58dad8 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -24,6 +24,8 @@
 #define BNX2X_MSG_STATS                 0x20000 /* was: NETIF_MSG_TIMER */
 #define NETIF_MSG_NVM                   0x40000 /* was: NETIF_MSG_HW */
 #define NETIF_MSG_DMAE                  0x80000 /* was: NETIF_MSG_HW */
+#define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
+#define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
 
 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
 
@@ -40,6 +42,12 @@
                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
         } while (0)
 
+/* for logging (never masked) */
+#define BNX2X_LOG(__fmt, __args...) do { \
+        printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+                __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
+        } while (0)
+
 /* before we have a dev->name use dev_info() */
 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
         if (bp->msglevel & NETIF_MSG_PROBE) \
@@ -574,7 +582,8 @@ struct bnx2x {
         u32                     fw_mb;
 
         u32                     hw_config;
-        u32                     serdes_config;
+        u32                     board;
+        u32                     serdes_config;
         u32                     lane_config;
         u32                     ext_phy_config;
 #define XGXS_EXT_PHY_TYPE(bp)           (bp->ext_phy_config & \
@@ -595,11 +604,11 @@ struct bnx2x {
         u8                      tx_lane_swap;
 
         u8                      link_up;
+        u8                      phy_link_up;
 
         u32                     supported;
 /* link settings - missing defines */
 #define SUPPORTED_2500baseT_Full        (1 << 15)
-#define SUPPORTED_CX4                   (1 << 16)
 
         u32                     phy_flags;
 /*#define PHY_SERDES_FLAG                       0x1*/
@@ -644,16 +653,9 @@ struct bnx2x {
 #define FLOW_CTRL_BOTH                  PORT_FEATURE_FLOW_CONTROL_BOTH
 #define FLOW_CTRL_NONE                  PORT_FEATURE_FLOW_CONTROL_NONE
 
-        u32                     pause_mode;
-#define PAUSE_NONE                      0
-#define PAUSE_SYMMETRIC                 1
-#define PAUSE_ASYMMETRIC                2
-#define PAUSE_BOTH                      3
-
         u32                     advertising;
 /* link settings - missing defines */
 #define ADVERTISED_2500baseT_Full       (1 << 15)
-#define ADVERTISED_CX4                  (1 << 16)
 
         u32                     link_status;
         u32                     line_speed;
@@ -667,6 +669,8 @@ struct bnx2x {
 #define NVRAM_TIMEOUT_COUNT             30000
 #define NVRAM_PAGE_SIZE                 256
 
+        u8                      wol;
+
         int                     rx_ring_size;
 
         u16                     tx_quick_cons_trip_int;
@@ -718,9 +722,6 @@ struct bnx2x {
 #endif
 
         char                    *name;
-        u16                     bus_speed_mhz;
-        u8                      wol;
-        u8                      pad;
 
         /* used to synchronize stats collecting */
         int                     stats_state;
@@ -873,6 +874,7 @@ struct bnx2x {
 #define PCICFG_LINK_SPEED               0xf0000
 #define PCICFG_LINK_SPEED_SHIFT         16
 
+#define BMAC_CONTROL_RX_ENABLE          2
 /* stuff added to make the code fit 80Col */
 
 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
@@ -944,13 +946,13 @@ struct bnx2x {
 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 
-#define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \
+#define NIG_STATUS_XGXS0_LINK10G \
                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
-#define NIG_XGXS0_LINK_STATUS \
+#define NIG_STATUS_XGXS0_LINK_STATUS \
                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
-#define NIG_XGXS0_LINK_STATUS_SIZE \
+#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
-#define NIG_SERDES0_LINK_STATUS \
+#define NIG_STATUS_SERDES0_LINK_STATUS \
                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
 #define NIG_MASK_MI_INT \
                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT