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authorVladislav Zolotarov <vladz@broadcom.com>2010-04-18 21:13:12 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-19 16:17:05 -0400
commit72fd0718332e6514fb9db325e89ffc694bb31f6e (patch)
tree944305857677a520b4ac33732feb139b52c8af29 /drivers/net/bnx2x.h
parentfc6055a5ba31e2c14e36e8939f9bf2b6d586a7f5 (diff)
bnx2x: Parity errors handling for 57710 and 57711
This patch introduces the parity errors handling code for 57710 and 57711 chips. HW is configured to stop all DMA transactions to the host and sending packets to the network once parity error is detected, which is meant to prevent silent data corruption. At the same time HW generates the attention interrupt to every function of the device where parity has been detected so that driver can start the recovery flow. The recovery is actually resetting the chip and restarting the driver on all active functions of the chip where the parity error has been reported. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x.h')
-rw-r--r--drivers/net/bnx2x.h23
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index ae9c89ebcc8b..ccef13b41dfa 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -155,9 +155,15 @@ do { \
155#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 155#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
156#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 156#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
157 157
158#define MF_CFG_RD(bp, field) SHMEM_RD(bp, mf_cfg.field)
159#define MF_CFG_WR(bp, field, val) SHMEM_WR(bp, mf_cfg.field, val)
160
158#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 161#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
159#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 162#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
160 163
164#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
165 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
166
161 167
162/* fast path */ 168/* fast path */
163 169
@@ -818,6 +824,12 @@ struct attn_route {
818 u32 sig[4]; 824 u32 sig[4];
819}; 825};
820 826
827typedef enum {
828 BNX2X_RECOVERY_DONE,
829 BNX2X_RECOVERY_INIT,
830 BNX2X_RECOVERY_WAIT,
831} bnx2x_recovery_state_t;
832
821struct bnx2x { 833struct bnx2x {
822 /* Fields used in the tx and intr/napi performance paths 834 /* Fields used in the tx and intr/napi performance paths
823 * are grouped together in the beginning of the structure 835 * are grouped together in the beginning of the structure
@@ -835,6 +847,9 @@ struct bnx2x {
835 struct pci_dev *pdev; 847 struct pci_dev *pdev;
836 848
837 atomic_t intr_sem; 849 atomic_t intr_sem;
850
851 bnx2x_recovery_state_t recovery_state;
852 int is_leader;
838#ifdef BCM_CNIC 853#ifdef BCM_CNIC
839 struct msix_entry msix_table[MAX_CONTEXT+2]; 854 struct msix_entry msix_table[MAX_CONTEXT+2];
840#else 855#else
@@ -924,8 +939,7 @@ struct bnx2x {
924 int mrrs; 939 int mrrs;
925 940
926 struct delayed_work sp_task; 941 struct delayed_work sp_task;
927 struct work_struct reset_task; 942 struct delayed_work reset_task;
928
929 struct timer_list timer; 943 struct timer_list timer;
930 int current_interval; 944 int current_interval;
931 945
@@ -1125,6 +1139,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1125#define LOAD_DIAG 2 1139#define LOAD_DIAG 2
1126#define UNLOAD_NORMAL 0 1140#define UNLOAD_NORMAL 0
1127#define UNLOAD_CLOSE 1 1141#define UNLOAD_CLOSE 1
1142#define UNLOAD_RECOVERY 2
1128 1143
1129 1144
1130/* DMAE command defines */ 1145/* DMAE command defines */
@@ -1294,6 +1309,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1294 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 1309 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1295 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1310 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1296 1311
1312#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1313 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1314 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1315 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1297 1316
1298#define MULTI_FLAGS(bp) \ 1317#define MULTI_FLAGS(bp) \
1299 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ 1318 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \