diff options
author | Michael Chan <mchan@broadcom.com> | 2008-01-21 20:07:06 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-28 18:10:15 -0500 |
commit | b2fadeae1334008c1bb4d87bc507141cb7aaf0e8 (patch) | |
tree | 26fbaeefce8860a40e54852783280446c4c95847 /drivers/net/bnx2.h | |
parent | 1097f5e92107ca3950fabf5e1d724faa80c91e7f (diff) |
[BNX2]: Add link-down workaround on 5706 serdes.
In some blade systems using the 5706 serdes, the hardware sometimes
does not properly generate link down interrupts. We add a workaround
in the driver's timer to force a link-down when some PHY registers
report loss of SYNC.
The parallel detect logic is cleaned up slightly to better integrate
the workaround.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r-- | drivers/net/bnx2.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index c1ab30b0f87a..31a030a6e2a5 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h | |||
@@ -6344,6 +6344,15 @@ struct l2_fhdr { | |||
6344 | #define MII_BNX2_DSP_RW_PORT 0x15 | 6344 | #define MII_BNX2_DSP_RW_PORT 0x15 |
6345 | #define MII_BNX2_DSP_ADDRESS 0x17 | 6345 | #define MII_BNX2_DSP_ADDRESS 0x17 |
6346 | #define MII_BNX2_DSP_EXPAND_REG 0x0f00 | 6346 | #define MII_BNX2_DSP_EXPAND_REG 0x0f00 |
6347 | #define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1) | ||
6348 | #define MII_EXPAND_REG1_RUDI_C 0x20 | ||
6349 | #define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 2) | ||
6350 | |||
6351 | #define MII_BNX2_MISC_SHADOW 0x1c | ||
6352 | #define MISC_SHDW_AN_DBG 0x6800 | ||
6353 | #define MISC_SHDW_AN_DBG_NOSYNC 0x0002 | ||
6354 | #define MISC_SHDW_MODE_CTL 0x7c00 | ||
6355 | #define MISC_SHDW_MODE_CTL_SIG_DET 0x0010 | ||
6347 | 6356 | ||
6348 | #define MII_BNX2_BLK_ADDR 0x1f | 6357 | #define MII_BNX2_BLK_ADDR 0x1f |
6349 | #define MII_BNX2_BLK_ADDR_IEEE0 0x0000 | 6358 | #define MII_BNX2_BLK_ADDR_IEEE0 0x0000 |
@@ -6643,6 +6652,7 @@ struct bnx2 { | |||
6643 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 | 6652 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 |
6644 | #define PHY_DIS_EARLY_DAC_FLAG 0x400 | 6653 | #define PHY_DIS_EARLY_DAC_FLAG 0x400 |
6645 | #define REMOTE_PHY_CAP_FLAG 0x800 | 6654 | #define REMOTE_PHY_CAP_FLAG 0x800 |
6655 | #define PHY_FORCED_DOWN_FLAG 0x1000 | ||
6646 | 6656 | ||
6647 | u32 mii_bmcr; | 6657 | u32 mii_bmcr; |
6648 | u32 mii_bmsr; | 6658 | u32 mii_bmsr; |