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authorMichael Chan <mchan@broadcom.com>2006-03-20 20:49:20 -0500
committerDavid S. Miller <davem@davemloft.net>2006-03-20 20:49:20 -0500
commit13daffa2f2ba65674e7816a0e95e7b93246cb686 (patch)
tree3170a19dfba530398d4f12e54a21400254fa98b1 /drivers/net/bnx2.h
parent236b6394bb49ea58465c6f935a286d2342576f8d (diff)
[BNX2]: Support larger rx ring sizes (part 1)
Increase maximum receive ring size from 255 to 1020 by supporting up to 4 linked pages of receive descriptors. To accomodate the higher memory usage, each physical descriptor page is allocated separately and the software ring that keeps track of the SKBs and the DMA addresses is allocated using vmalloc. Some of the receive-related fields in the bp structure are re- organized a bit for better locality of reference. The max. was reduced to 1020 from 4080 after discussion with David Miller. This patch contains ring init code changes only. This next patch contains rx data path code changes. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r--drivers/net/bnx2.h36
1 files changed, 22 insertions, 14 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 9f691cbd666b..beb2e8bcc659 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -3792,8 +3792,10 @@ struct l2_fhdr {
3792#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 3792#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
3793#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) 3793#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
3794 3794
3795#define MAX_RX_RINGS 4
3795#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 3796#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
3796#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) 3797#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
3798#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
3797 3799
3798#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \ 3800#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
3799 (MAX_TX_DESC_CNT - 1)) ? \ 3801 (MAX_TX_DESC_CNT - 1)) ? \
@@ -3805,8 +3807,10 @@ struct l2_fhdr {
3805 (MAX_RX_DESC_CNT - 1)) ? \ 3807 (MAX_RX_DESC_CNT - 1)) ? \
3806 (x) + 2 : (x) + 1 3808 (x) + 2 : (x) + 1
3807 3809
3808#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT) 3810#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
3809 3811
3812#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
3813#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
3810 3814
3811/* Context size. */ 3815/* Context size. */
3812#define CTX_SHIFT 7 3816#define CTX_SHIFT 7
@@ -3903,6 +3907,15 @@ struct bnx2 {
3903 struct status_block *status_blk; 3907 struct status_block *status_blk;
3904 u32 last_status_idx; 3908 u32 last_status_idx;
3905 3909
3910 u32 flags;
3911#define PCIX_FLAG 1
3912#define PCI_32BIT_FLAG 2
3913#define ONE_TDMA_FLAG 4 /* no longer used */
3914#define NO_WOL_FLAG 8
3915#define USING_DAC_FLAG 0x10
3916#define USING_MSI_FLAG 0x20
3917#define ASF_ENABLE_FLAG 0x40
3918
3906 struct tx_bd *tx_desc_ring; 3919 struct tx_bd *tx_desc_ring;
3907 struct sw_bd *tx_buf_ring; 3920 struct sw_bd *tx_buf_ring;
3908 u32 tx_prod_bseq; 3921 u32 tx_prod_bseq;
@@ -3920,19 +3933,22 @@ struct bnx2 {
3920 u32 rx_offset; 3933 u32 rx_offset;
3921 u32 rx_buf_use_size; /* useable size */ 3934 u32 rx_buf_use_size; /* useable size */
3922 u32 rx_buf_size; /* with alignment */ 3935 u32 rx_buf_size; /* with alignment */
3923 struct rx_bd *rx_desc_ring; 3936 u32 rx_max_ring_idx;
3924 struct sw_bd *rx_buf_ring; 3937
3925 u32 rx_prod_bseq; 3938 u32 rx_prod_bseq;
3926 u16 rx_prod; 3939 u16 rx_prod;
3927 u16 rx_cons; 3940 u16 rx_cons;
3928 3941
3929 u32 rx_csum; 3942 u32 rx_csum;
3930 3943
3944 struct sw_bd *rx_buf_ring;
3945 struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
3946
3931 /* Only used to synchronize netif_stop_queue/wake_queue when tx */ 3947 /* Only used to synchronize netif_stop_queue/wake_queue when tx */
3932 /* ring is full */ 3948 /* ring is full */
3933 spinlock_t tx_lock; 3949 spinlock_t tx_lock;
3934 3950
3935 /* End of fileds used in the performance code paths. */ 3951 /* End of fields used in the performance code paths. */
3936 3952
3937 char *name; 3953 char *name;
3938 3954
@@ -3945,15 +3961,6 @@ struct bnx2 {
3945 /* Used to synchronize phy accesses. */ 3961 /* Used to synchronize phy accesses. */
3946 spinlock_t phy_lock; 3962 spinlock_t phy_lock;
3947 3963
3948 u32 flags;
3949#define PCIX_FLAG 1
3950#define PCI_32BIT_FLAG 2
3951#define ONE_TDMA_FLAG 4 /* no longer used */
3952#define NO_WOL_FLAG 8
3953#define USING_DAC_FLAG 0x10
3954#define USING_MSI_FLAG 0x20
3955#define ASF_ENABLE_FLAG 0x40
3956
3957 u32 phy_flags; 3964 u32 phy_flags;
3958#define PHY_SERDES_FLAG 1 3965#define PHY_SERDES_FLAG 1
3959#define PHY_CRC_FIX_FLAG 2 3966#define PHY_CRC_FIX_FLAG 2
@@ -4004,8 +4011,9 @@ struct bnx2 {
4004 dma_addr_t tx_desc_mapping; 4011 dma_addr_t tx_desc_mapping;
4005 4012
4006 4013
4014 int rx_max_ring;
4007 int rx_ring_size; 4015 int rx_ring_size;
4008 dma_addr_t rx_desc_mapping; 4016 dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
4009 4017
4010 u16 tx_quick_cons_trip; 4018 u16 tx_quick_cons_trip;
4011 u16 tx_quick_cons_trip_int; 4019 u16 tx_quick_cons_trip_int;