aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/bnx2.h
diff options
context:
space:
mode:
authorMichael Chan <mchan@broadcom.com>2008-01-30 00:37:17 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-31 22:27:16 -0500
commit83e3fc89bb2b7bb27b3a6da5a541c43ce7706f42 (patch)
tree1216f5b1f02e30362d5cd153d29ac4e1182b0f1f /drivers/net/bnx2.h
parent62a8313cddbea04f2a28d1d76acf317c2a56cfae (diff)
[BNX2]: Fine-tune flow control on 5709.
Make use of the programmable high/low water marks in 5709 for 802.3 flow control. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r--drivers/net/bnx2.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index c5fe34013548..3aa0364942e2 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -348,6 +348,12 @@ struct l2_fhdr {
348#define BNX2_L2CTX_BD_PRE_READ 0x00000000 348#define BNX2_L2CTX_BD_PRE_READ 0x00000000
349#define BNX2_L2CTX_CTX_SIZE 0x00000000 349#define BNX2_L2CTX_CTX_SIZE 0x00000000
350#define BNX2_L2CTX_CTX_TYPE 0x00000000 350#define BNX2_L2CTX_CTX_TYPE 0x00000000
351#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 32
352#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4
353#define BNX2_L2CTX_LO_WATER_MARK_DIS 0
354#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4
355#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16
356#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff
351#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 357#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
352#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 358#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
353#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 359#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
@@ -4494,6 +4500,9 @@ struct l2_fhdr {
4494#define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31) 4500#define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31)
4495#define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646 4501#define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646
4496 4502
4503#define BNX2_MQ_MAP_L2_5 0x00003d34
4504#define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26)
4505
4497/* 4506/*
4498 * tsch_reg definition 4507 * tsch_reg definition
4499 * offset: 0x4c00 4508 * offset: 0x4c00
@@ -6405,7 +6414,7 @@ struct l2_fhdr {
6405 6414
6406#define RX_COPY_THRESH 128 6415#define RX_COPY_THRESH 128
6407 6416
6408#define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff 6417#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff
6409 6418
6410#define DMA_READ_CHANS 5 6419#define DMA_READ_CHANS 5
6411#define DMA_WRITE_CHANS 3 6420#define DMA_WRITE_CHANS 3