Merge git://git.tuxdriver.com/git/netdev-jwl

1 files changed, 115 insertions, 4 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 62857b6a6ee4..76bb5f1a250b 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -1449,8 +1449,9 @@ struct l2_fhdr {
 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
-#define BNX2_EMAC_MODE_PORT_UNDEF                        (3L<<2)
+#define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
+#define BNX2_EMAC_MODE_25G                               (1L<<5)
 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
@@ -3714,6 +3715,15 @@ struct l2_fhdr {
 #define BNX2_MCP_ROM                                    0x00150000
 #define BNX2_MCP_SCRATCH                                0x00160000
 
+#define BNX2_SHM_HDR_SIGNATURE                          BNX2_MCP_SCRATCH
+#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                  0xffff0000
+#define BNX2_SHM_HDR_SIGNATURE_SIG                       0x53530000
+#define BNX2_SHM_HDR_SIGNATURE_VER_MASK                  0x000000ff
+#define BNX2_SHM_HDR_SIGNATURE_VER_ONE                   0x00000001
+
+#define BNX2_SHM_HDR_ADDR_0                             BNX2_MCP_SCRATCH + 4
+#define BNX2_SHM_HDR_ADDR_1                             BNX2_MCP_SCRATCH + 8
+
 
 #define NUM_MC_HASH_REGISTERS   8
 
@@ -3724,6 +3734,53 @@ struct l2_fhdr {
 #define PHY_ID(id)                                  ((id) & 0xfffffff0)
 #define PHY_REV_ID(id)                              ((id) & 0xf)
 
+/* 5708 Serdes PHY registers */
+
+#define BCM5708S_UP1                            0xb
+
+#define BCM5708S_UP1_2G5                        0x1
+
+#define BCM5708S_BLK_ADDR                       0x1f
+
+#define BCM5708S_BLK_ADDR_DIG                   0x0000
+#define BCM5708S_BLK_ADDR_DIG3                  0x0002
+#define BCM5708S_BLK_ADDR_TX_MISC               0x0005
+
+/* Digital Block */
+#define BCM5708S_1000X_CTL1                     0x10
+
+#define BCM5708S_1000X_CTL1_FIBER_MODE          0x0001
+#define BCM5708S_1000X_CTL1_AUTODET_EN          0x0010
+
+#define BCM5708S_1000X_CTL2                     0x11
+
+#define BCM5708S_1000X_CTL2_PLLEL_DET_EN        0x0001
+
+#define BCM5708S_1000X_STAT1                    0x14
+
+#define BCM5708S_1000X_STAT1_SGMII              0x0001
+#define BCM5708S_1000X_STAT1_LINK               0x0002
+#define BCM5708S_1000X_STAT1_FD                 0x0004
+#define BCM5708S_1000X_STAT1_SPEED_MASK         0x0018
+#define BCM5708S_1000X_STAT1_SPEED_10           0x0000
+#define BCM5708S_1000X_STAT1_SPEED_100          0x0008
+#define BCM5708S_1000X_STAT1_SPEED_1G           0x0010
+#define BCM5708S_1000X_STAT1_SPEED_2G5          0x0018
+#define BCM5708S_1000X_STAT1_TX_PAUSE           0x0020
+#define BCM5708S_1000X_STAT1_RX_PAUSE           0x0040
+
+/* Digital3 Block */
+#define BCM5708S_DIG_3_0                        0x10
+
+#define BCM5708S_DIG_3_0_USE_IEEE               0x0001
+
+/* Tx/Misc Block */
+#define BCM5708S_TX_ACTL1                       0x15
+
+#define BCM5708S_TX_ACTL1_DRIVER_VCM            0x30
+
+#define BCM5708S_TX_ACTL3                       0x17
+
 #define MIN_ETHERNET_PACKET_SIZE        60
 #define MAX_ETHERNET_PACKET_SIZE        1514
 #define MAX_ETHERNET_JUMBO_PACKET_SIZE  9014
@@ -3799,7 +3856,7 @@ struct sw_bd {
 #define BUFFERED_FLASH_PHY_PAGE_SIZE            (1 << BUFFERED_FLASH_PAGE_BITS)
 #define BUFFERED_FLASH_BYTE_ADDR_MASK           (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
 #define BUFFERED_FLASH_PAGE_SIZE                264
-#define BUFFERED_FLASH_TOTAL_SIZE               131072
+#define BUFFERED_FLASH_TOTAL_SIZE               0x21000
 
 #define SAIFUN_FLASH_PAGE_BITS                  8
 #define SAIFUN_FLASH_PHY_PAGE_SIZE              (1 << SAIFUN_FLASH_PAGE_BITS)
@@ -3807,6 +3864,12 @@ struct sw_bd {
 #define SAIFUN_FLASH_PAGE_SIZE                  256
 #define SAIFUN_FLASH_BASE_TOTAL_SIZE            65536
 
+#define ST_MICRO_FLASH_PAGE_BITS                8
+#define ST_MICRO_FLASH_PHY_PAGE_SIZE            (1 << ST_MICRO_FLASH_PAGE_BITS)
+#define ST_MICRO_FLASH_BYTE_ADDR_MASK           (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
+#define ST_MICRO_FLASH_PAGE_SIZE                256
+#define ST_MICRO_FLASH_BASE_TOTAL_SIZE          65536
+
 #define NVRAM_TIMEOUT_COUNT                     30000
 
 
@@ -3815,6 +3878,8 @@ struct sw_bd {
                                                  BNX2_NVM_CFG1_PROTECT_MODE | \
                                                  BNX2_NVM_CFG1_FLASH_SIZE)
 
+#define FLASH_BACKUP_STRAP_MASK                 (0xf << 26)
+
 struct flash_spec {
         u32 strapping;
         u32 config1;
@@ -3849,6 +3914,9 @@ struct bnx2 {
         u16                     tx_cons;
         int                     tx_ring_size;
 
+        u16                     hw_tx_cons;
+        u16                     hw_rx_cons;
+
 #ifdef BCM_VLAN 
         struct                  vlan_group *vlgrp;
 #endif
@@ -3893,6 +3961,7 @@ struct bnx2 {
 #define PHY_SERDES_FLAG                 1
 #define PHY_CRC_FIX_FLAG                2
 #define PHY_PARALLEL_DETECT_FLAG        4
+#define PHY_2_5G_CAPABLE_FLAG           8
 #define PHY_INT_MODE_MASK_FLAG          0x300
 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
@@ -3901,6 +3970,7 @@ struct bnx2 {
         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
 #define CHIP_NUM_5706                   0x57060000
+#define CHIP_NUM_5708                   0x57080000
 
 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
 #define CHIP_REV_Ax                     0x00000000
@@ -3913,6 +3983,9 @@ struct bnx2 {
 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
 #define CHIP_ID_5706_A0                 0x57060000
 #define CHIP_ID_5706_A1                 0x57060010
+#define CHIP_ID_5706_A2                 0x57060020
+#define CHIP_ID_5708_A0                 0x57080000
+#define CHIP_ID_5708_B0                 0x57081000
 
 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0xf)
 
@@ -3991,6 +4064,8 @@ struct bnx2 {
 
         u8                      mac_addr[8];
 
+        u32                     shmem_base;
+
         u32                     fw_ver;
 
         int                     pm_cap;
@@ -4130,14 +4205,46 @@ struct fw_info {
 #define BNX2_FW_MSG_STATUS_FAILURE               0x00ff0000
 
 #define BNX2_LINK_STATUS                        0x0000000c
+#define BNX2_LINK_STATUS_INIT_VALUE              0xffffffff 
+#define BNX2_LINK_STATUS_LINK_UP                 0x1 
+#define BNX2_LINK_STATUS_LINK_DOWN               0x0 
+#define BNX2_LINK_STATUS_SPEED_MASK              0x1e
+#define BNX2_LINK_STATUS_AN_INCOMPLETE           (0<<1) 
+#define BNX2_LINK_STATUS_10HALF                  (1<<1) 
+#define BNX2_LINK_STATUS_10FULL                  (2<<1) 
+#define BNX2_LINK_STATUS_100HALF                 (3<<1) 
+#define BNX2_LINK_STATUS_100BASE_T4              (4<<1) 
+#define BNX2_LINK_STATUS_100FULL                 (5<<1) 
+#define BNX2_LINK_STATUS_1000HALF                (6<<1) 
+#define BNX2_LINK_STATUS_1000FULL                (7<<1) 
+#define BNX2_LINK_STATUS_2500HALF                (8<<1) 
+#define BNX2_LINK_STATUS_2500FULL                (9<<1) 
+#define BNX2_LINK_STATUS_AN_ENABLED              (1<<5) 
+#define BNX2_LINK_STATUS_AN_COMPLETE             (1<<6) 
+#define BNX2_LINK_STATUS_PARALLEL_DET            (1<<7) 
+#define BNX2_LINK_STATUS_RESERVED                (1<<8) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL     (1<<9) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF     (1<<10) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100BT4       (1<<11) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100FULL      (1<<12) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100HALF      (1<<13) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10FULL       (1<<14) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10HALF       (1<<15) 
+#define BNX2_LINK_STATUS_TX_FC_ENABLED           (1<<16) 
+#define BNX2_LINK_STATUS_RX_FC_ENABLED           (1<<17) 
+#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP   (1<<18) 
+#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP  (1<<19) 
+#define BNX2_LINK_STATUS_SERDES_LINK             (1<<20) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL     (1<<21) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF     (1<<22) 
 
 #define BNX2_DRV_PULSE_MB                       0x00000010
-#define BNX2_DRV_PULSE_SEQ_MASK                  0x0000ffff
+#define BNX2_DRV_PULSE_SEQ_MASK                  0x00007fff
 
 /* Indicate to the firmware not to go into the
  * OS absent when it is not getting driver pulse.
  * This is used for debugging. */
-#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE        0x00010000
+#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE        0x00080000
 
 #define BNX2_DEV_INFO_SIGNATURE                 0x00000020
 #define BNX2_DEV_INFO_SIGNATURE_MAGIC            0x44564900
@@ -4160,6 +4267,8 @@ struct fw_info {
 #define BNX2_SHARED_HW_CFG_DESIGN_LOM            0x1
 #define BNX2_SHARED_HW_CFG_PHY_COPPER            0
 #define BNX2_SHARED_HW_CFG_PHY_FIBER             0x2
+#define BNX2_SHARED_HW_CFG_PHY_2_5G              0x20
+#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE         0x40
 #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS   8
 #define BNX2_SHARED_HW_CFG_LED_MODE_MASK         0x300
 #define BNX2_SHARED_HW_CFG_LED_MODE_MAC          0
@@ -4173,9 +4282,11 @@ struct fw_info {
 
 #define BNX2_PORT_HW_CFG_MAC_LOWER              0x00000054
 #define BNX2_PORT_HW_CFG_CONFIG                 0x00000058
+#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK         0x0000ffff
 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK      0x001f0000
 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN        0x00000000
 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G        0x00030000
+#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G      0x00040000
 
 #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER        0x00000068
 #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER        0x0000006c