bnx2: Turn on multi rx rings.

Enable multiple rx rings if MSI-X vectors are available.  We enable
up to 7 rx rings.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 25 insertions, 1 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 362bef6ff5ff..efa0ca9a8fd3 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -4158,6 +4158,23 @@ struct l2_fhdr {
 
 
 /*
+ *  rlup_reg definition
+ *  offset: 0x2000
+ */
+#define BNX2_RLUP_RSS_CONFIG                            0x0000201c
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI            (0x3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI        (0L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI        (1L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI    (2L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI        (3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI            (0x3L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI        (0L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI        (1L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI    (2L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI        (3L<<2)
+
+
+/*
  *  rbuf_reg definition
  *  offset: 0x200000
  */
@@ -5528,6 +5545,9 @@ struct l2_fhdr {
 #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF  (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
                                          BNX2_HC_SB_CONFIG_1)
 #define BNX2_HC_TX_TICKS_OFF    (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF  (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
+                                         BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_TICKS_OFF    (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
 
 
 /*
@@ -5856,6 +5876,9 @@ struct l2_fhdr {
 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
 
 #define BNX2_RXP_SCRATCH                                0x000e0000
+#define BNX2_RXP_SCRATCH_RSS_TBL_SZ                      0x000e0038
+#define BNX2_RXP_SCRATCH_RSS_TBL                         0x000e003c
+#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES             128
 
 
 /*
@@ -6480,6 +6503,7 @@ struct l2_fhdr {
 #define TX_TSS_CID      32
 #define RX_CID          0
 #define RX_RSS_CID      4
+#define RX_MAX_RSS_RINGS        7
 
 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
 #define MB_RX_CID_ADDR  MB_GET_CID_ADDR(RX_CID)
@@ -6558,7 +6582,7 @@ struct flash_spec {
 };
 
 #define BNX2_MAX_MSIX_HW_VEC    9
-#define BNX2_MAX_MSIX_VEC       2
+#define BNX2_MAX_MSIX_VEC       9
 #define BNX2_BASE_VEC           0
 #define BNX2_TX_VEC             1
 #define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)