[BNX2]: Add new 5709 registers (part 1).

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1311 insertions, 146 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 11e9c55d1dd0..73c785585fc3 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -56,6 +56,7 @@ struct rx_bd {
 
 };
 
+#define BNX2_RX_ALIGN                   16
 
 /*
  *  status_block definition
@@ -90,6 +91,7 @@ struct status_block {
                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
+                #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
 
         u32 status_attn_bits_ack;
@@ -117,7 +119,8 @@ struct status_block {
         u16 status_completion_producer_index;
         u16 status_cmd_consumer_index;
         u16 status_idx;
-        u16 status_unused;
+        u8 status_unused;
+        u8 status_blk_num;
 #elif defined(__LITTLE_ENDIAN)
         u16 status_tx_quick_consumer_index1;
         u16 status_tx_quick_consumer_index0;
@@ -141,7 +144,8 @@ struct status_block {
         u16 status_rx_quick_consumer_index14;
         u16 status_cmd_consumer_index;
         u16 status_completion_producer_index;
-        u16 status_unused;
+        u8 status_blk_num;
+        u8 status_unused;
         u16 status_idx;
 #endif
 };
@@ -301,6 +305,10 @@ struct l2_fhdr {
 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
 
+#define BNX2_L2CTX_TYPE_XI                              0x00000080
+#define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
+#define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
+#define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
 
 /*
  *  l2_bd_chain_context definition
@@ -328,11 +336,15 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
+#define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
+#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
@@ -347,6 +359,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
+#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
 
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
@@ -366,7 +379,7 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
@@ -374,18 +387,21 @@ struct l2_fhdr {
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
-#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
 
 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
+#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
+
 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
+#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
 
 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
@@ -398,9 +414,11 @@ struct l2_fhdr {
  *  offset: 0x400
  */
 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
-#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
+#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
+#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
 
 #define BNX2_PCI_CONFIG_1                               0x00000404
+#define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
@@ -419,6 +437,7 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
+#define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
 
 #define BNX2_PCI_CONFIG_2                               0x00000408
 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
@@ -468,9 +487,13 @@ struct l2_fhdr {
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
+#define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
+#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
+#define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
 
 #define BNX2_PCI_CONFIG_3                               0x0000040c
 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
+#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
@@ -501,8 +524,10 @@ struct l2_fhdr {
 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
 
 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
-#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
-#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
+#define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
+#define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
+#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
+#define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
 
 #define BNX2_PCI_VPD_DATA                               0x00000430
 #define BNX2_PCI_ID_VAL1                                0x00000434
@@ -535,19 +560,26 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
+#define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
+#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
-#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
+#define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
-#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
-#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
-#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
+#define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
+#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
+#define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
+#define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
 
 #define BNX2_PCI_ID_VAL5                                0x00000444
 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
@@ -556,6 +588,10 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
+#define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
+#define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
+#define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
+#define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
 
 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
@@ -567,12 +603,91 @@ struct l2_fhdr {
 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
+#define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
 
 #define BNX2_PCI_MSI_DATA                               0x00000450
-#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
+#define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
 
 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
+#define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
+
+#define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
+#define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
+#define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
+#define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
+
+#define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
+#define BNX2_PCI_MSI_MASK                               0x00000464
+#define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
+
+#define BNX2_PCI_MSI_PEND                               0x00000468
+#define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
+
+#define BNX2_PCI_PM_DATA_C                              0x0000046c
+#define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
+#define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
+
+#define BNX2_PCI_MSIX_CONTROL                           0x000004c0
+#define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
+#define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
+
+#define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
+#define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
+
+#define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
+#define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
+#define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
+
+#define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
+#define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
+#define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
+#define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
+#define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
+#define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
+
+#define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
+#define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
+#define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
+#define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
+#define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
+
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
+#define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
+
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
+#define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
+
+#define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
+#define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
+#define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
+
+#define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
+#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
 
 
 /*
@@ -582,13 +697,23 @@ struct l2_fhdr {
 #define BNX2_MISC_COMMAND                               0x00000800
 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
-#define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
-#define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
+#define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
+#define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
+#define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
+#define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
+#define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
+#define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
+#define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
+#define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
+#define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
+#define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
+#define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
+#define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
 
 #define BNX2_MISC_CFG                                   0x00000804
-#define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
+#define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
@@ -596,16 +721,45 @@ struct l2_fhdr {
 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
-#define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
-#define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
+#define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
+#define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
-#define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
+#define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
-#define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
+#define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
+#define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
+#define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
+#define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
+#define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
+#define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
+#define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
 
 #define BNX2_MISC_ID                                    0x00000808
 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
+#define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
+#define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
+#define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
@@ -639,6 +793,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -669,6 +825,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
@@ -699,6 +857,8 @@ struct l2_fhdr {
 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
+#define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
+#define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 
 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
@@ -718,30 +878,41 @@ struct l2_fhdr {
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
-#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
-
-#define BNX2_MISC_GPIO                                  0x0000081c
-#define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
-#define BNX2_MISC_GPIO_SET                               (0xffL<<8)
-#define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
-#define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
-
-#define BNX2_MISC_GPIO_INT                              0x00000820
-#define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
-#define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
-#define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
-#define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
+
+#define BNX2_MISC_SPIO                                  0x0000081c
+#define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
+#define BNX2_MISC_SPIO_SET                               (0xffL<<8)
+#define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
+#define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
+
+#define BNX2_MISC_SPIO_INT                              0x00000820
+#define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
+#define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
+#define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
+#define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
+#define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
 
 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
@@ -775,6 +946,8 @@ struct l2_fhdr {
 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
+#define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
+#define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
 
 #define BNX2_MISC_ARB_REQ0                              0x0000082c
 #define BNX2_MISC_ARB_REQ1                              0x00000830
@@ -831,22 +1004,12 @@ struct l2_fhdr {
 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
 
-#define BNX2_MISC_PRBS_CONTROL                          0x00000878
-#define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
-#define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
-#define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
-#define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
-#define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
-#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
-
-#define BNX2_MISC_PRBS_STATUS                           0x0000087c
-#define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
-#define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
-#define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
-#define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
+#define BNX2_MISC_RESERVED1                             0x00000878
+#define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
+
+#define BNX2_MISC_RESERVED2                             0x0000087c
+#define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
+#define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
 
 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
@@ -857,13 +1020,15 @@ struct l2_fhdr {
 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
-#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
+#define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
-#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
 
@@ -891,13 +1056,13 @@ struct l2_fhdr {
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
-#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
@@ -955,6 +1120,38 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
+#define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
+#define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
+#define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
+#define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
+#define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
+#define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
+#define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
+#define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
+#define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
+#define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
+#define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
+#define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
+#define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
+#define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
+#define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
+#define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
+#define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
+#define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
+#define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
+#define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
+#define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
+#define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
+#define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
+#define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
+#define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
+#define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
+#define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
+#define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
+#define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
 
 #define BNX2_MISC_PERR_ENA1                             0x000008a8
 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
@@ -989,6 +1186,35 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
+#define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
+#define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
+#define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
+#define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
+#define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
+#define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
+#define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
+#define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
+#define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
+#define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
+#define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
+#define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
+#define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
+#define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
+#define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
+#define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
+#define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
+#define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
+#define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
+#define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
+#define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
+#define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
+#define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
+#define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
+#define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
+#define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
+#define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
+#define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
+#define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
 
 #define BNX2_MISC_PERR_ENA2                             0x000008ac
 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
@@ -1000,19 +1226,498 @@ struct l2_fhdr {
 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
+#define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
+#define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
+#define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
+#define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
+#define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
+#define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
+#define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
 
 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
+#define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
 
 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
+#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
+#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
+#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
 
 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
 
-#define BNX2_MISC_UNUSED0                               0x000008bc
+#define BNX2_MISC_GP_HW_CTL0                            0x000008bc
+#define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
+#define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
+#define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
+#define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
+#define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
+#define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
+#define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
+#define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
+#define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
+#define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
+#define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
+#define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
+#define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
+#define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
+#define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
+#define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
+#define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
+#define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
+
+#define BNX2_MISC_GP_HW_CTL1                            0x000008c0
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
+#define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
+#define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
+#define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
+#define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
+
+#define BNX2_MISC_NEW_HW_CTL                            0x000008c4
+#define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
+#define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
+#define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
+
+#define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
+#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
+#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_HW_CTL                            0x000008cc
+#define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
+#define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
+
+#define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
+#define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
+
+#define BNX2_MISC_PPIO                                  0x000008d4
+#define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
+#define BNX2_MISC_PPIO_SET                               (0xfL<<8)
+#define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
+#define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
+
+#define BNX2_MISC_PPIO_INT                              0x000008d8
+#define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
+#define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
+#define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
+#define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
+
+#define BNX2_MISC_RESET_NUMS                            0x000008dc
+#define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
+#define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
+#define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
+#define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
+#define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
+
+#define BNX2_MISC_CS16_ERR                              0x000008e0
+#define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
+#define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
+#define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
+#define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
+#define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
+#define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
+#define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
+#define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
+#define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
+#define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
+#define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
+#define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
+#define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
+#define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
+#define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
+#define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
+#define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
+#define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
+
+#define BNX2_MISC_SPIO_EVENT                            0x000008e4
+#define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
+
+#define BNX2_MISC_PPIO_EVENT                            0x000008e8
+#define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
+
+#define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
+#define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
+
+#define BNX2_MISC_OTP_CMD1                              0x000008f0
+#define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
+#define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
+#define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
+#define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
+#define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
+#define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
+#define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
+#define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
+#define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
+#define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
+#define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
+
+#define BNX2_MISC_OTP_CMD2                              0x000008f4
+#define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
+#define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
+#define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
+
+#define BNX2_MISC_OTP_STATUS                            0x000008f8
+#define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
+#define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
+#define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
+#define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
+#define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
+
+#define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
+#define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
+#define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
+#define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
+#define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
+#define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
+
+#define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
+#define BNX2_MISC_BIST_CS0                              0x0000090c
+#define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
+#define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
+
+#define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
+#define BNX2_MISC_BIST_CS1                              0x00000914
+#define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
+#define BNX2_MISC_BIST_CS2                              0x0000091c
+#define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
+#define BNX2_MISC_BIST_CS3                              0x00000924
+#define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
+#define BNX2_MISC_BIST_CS4                              0x0000092c
+#define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
+#define BNX2_MISC_BIST_CS5                              0x00000934
+#define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
+#define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
+#define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
+#define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
+#define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
+
+#define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
+#define BNX2_MISC_MEM_TM0                               0x0000093c
+#define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
+#define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
+#define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
+#define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
+
+#define BNX2_MISC_USPLL_CTRL                            0x00000940
+#define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
+#define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
+#define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
+#define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
+#define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
+#define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
+#define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
+#define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
+#define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
+#define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
+#define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
+#define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
+#define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
+#define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
+#define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS0                          0x00000944
+#define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
+#define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
+#define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
+#define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
+#define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
+#define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
+#define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
+#define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
+#define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
+#define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
+#define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
+#define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
+#define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
+#define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
+#define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
+#define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
+#define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
+#define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
+#define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
+#define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
+#define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
+#define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
+#define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
+#define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
+#define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
+#define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
+#define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
+#define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
+
+#define BNX2_MISC_PERR_STATUS1                          0x00000948
+#define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
+#define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
+#define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
+#define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
+#define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
+#define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
+#define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
+#define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
+#define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
+#define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
+#define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
+#define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
+#define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
+#define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
+#define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
+#define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
+#define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
+#define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
+#define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
+#define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
+#define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
+#define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
+#define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
+#define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
+#define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
+#define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
+#define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
+#define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
+#define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
+
+#define BNX2_MISC_PERR_STATUS2                          0x0000094c
+#define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
+#define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
+#define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
+#define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
+#define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
+#define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
+#define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
+
+#define BNX2_MISC_LCPLL_CTRL0                           0x00000950
+#define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
+#define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
+#define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
+#define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
+#define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
+#define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
+#define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
+#define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
+#define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
+#define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
+
+#define BNX2_MISC_LCPLL_CTRL1                           0x00000954
+#define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
+#define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
+#define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
+
+#define BNX2_MISC_LCPLL_STATUS                          0x00000958
+#define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
+#define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
+#define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
+#define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
+#define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
+#define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
+#define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
+
+#define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
+#define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
 
 
 /*
@@ -1031,11 +1736,35 @@ struct l2_fhdr {
 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
+#define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
+#define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
+#define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
 
 #define BNX2_NVM_STATUS                                 0x00006404
 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
+#define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
 
 #define BNX2_NVM_WRITE                                  0x00006408
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
@@ -1046,6 +1775,10 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
 
 #define BNX2_NVM_ADDR                                   0x0000640c
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
@@ -1056,6 +1789,10 @@ struct l2_fhdr {
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_READ                                   0x00006410
 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
@@ -1066,6 +1803,10 @@ struct l2_fhdr {
 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
 
 #define BNX2_NVM_CFG1                                   0x00006414
 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
@@ -1077,14 +1818,21 @@ struct l2_fhdr {
 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
+#define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
+#define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
+#define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
+#define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
+#define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
+#define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
 
 #define BNX2_NVM_CFG2                                   0x00006418
 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
+#define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
 
 #define BNX2_NVM_CFG3                                   0x0000641c
 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
@@ -1119,6 +1867,35 @@ struct l2_fhdr {
 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
 
+#define BNX2_NVM_CFG4                                   0x0000642c
+#define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
+#define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
+#define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
+#define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
+#define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
+#define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
+#define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
+
+#define BNX2_NVM_RECONFIG                               0x00006430
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
+#define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
+#define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
+#define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
+#define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
+
 
 
 /*
@@ -1140,6 +1917,8 @@ struct l2_fhdr {
 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
+#define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
+#define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
 
 #define BNX2_DMA_CONFIG                                 0x00000c08
 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
@@ -1161,85 +1940,315 @@ struct l2_fhdr {
 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
+#define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
+#define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
+#define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
+#define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
+#define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
+#define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
+#define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
 
 #define BNX2_DMA_BLACKOUT                               0x00000c0c
 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
 
-#define BNX2_DMA_RCHAN_STAT                             0x00000c30
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_WCHAN_STAT                             0x00000c34
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
-#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
-#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
-
-#define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
-#define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
-#define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
-#define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
-
-#define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
-#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
-#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
-
-#define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
-#define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
-#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
-#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
-#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
-
-#define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
-#define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
-#define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
-#define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
-#define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
+#define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
+#define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
+#define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
+
+#define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
+#define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
+#define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
+
+#define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
+#define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
+
+#define BNX2_DMA_ARBITER                                0x00000c20
+#define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
+#define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
+#define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
+#define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
+#define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
+#define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
+#define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
+
+#define BNX2_DMA_ARB_TIMERS                             0x00000c24
+#define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
+#define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
+#define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
+
+#define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
+#define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
+#define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
+
+#define BNX2_DMA_TAG_RAM_00                             0x00000c30
+#define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_01                             0x00000c34
+#define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_02                             0x00000c38
+#define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_03                             0x00000c3c
+#define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_04                             0x00000c40
+#define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_05                             0x00000c44
+#define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_06                             0x00000c48
+#define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_07                             0x00000c4c
+#define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_08                             0x00000c50
+#define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_09                             0x00000c54
+#define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_10                             0x00000c58
+#define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
+
+#define BNX2_DMA_TAG_RAM_11                             0x00000c5c
+#define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
+#define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
+#define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
+#define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
+#define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
+#define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
+#define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
+
 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
@@ -1336,6 +2345,25 @@ struct l2_fhdr {
  */
 #define BNX2_CTX_COMMAND                                0x00001000
 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
+#define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
+#define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
+#define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
+#define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
+#define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
+#define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
+#define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
 
 #define BNX2_CTX_STATUS                                 0x00001004
 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
@@ -1343,6 +2371,13 @@ struct l2_fhdr {
 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
+#define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
+#define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
+#define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
+#define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
+#define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
+#define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
+#define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
 
 #define BNX2_CTX_VIRT_ADDR                              0x00001008
 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
@@ -1357,10 +2392,15 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK                                   0x00001018
 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
-#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
+#define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
+#define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
+#define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
+#define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
+#define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
@@ -1370,21 +2410,89 @@ struct l2_fhdr {
 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
 
+#define BNX2_CTX_CTX_CTRL                               0x0000101c
+#define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
+#define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
+#define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
+#define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
+#define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
+#define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
+
+#define BNX2_CTX_CTX_DATA                               0x00001020
 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
+#define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
+#define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
+#define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
 
 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
 
+#define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
+#define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
+#define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
+#define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
+#define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
+#define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
+
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
+#define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
+
+#define BNX2_CTX_CACHE_STATUS                           0x00001050
+#define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
+#define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
+
+#define BNX2_CTX_DMA_STATUS                             0x00001054
+#define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
+#define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
+
+#define BNX2_CTX_REP_STATUS                             0x00001058
+#define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
+#define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
+#define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
+
+#define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
+#define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
 
 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
@@ -1394,6 +2502,26 @@ struct l2_fhdr {
 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
+#define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
+
+#define BNX2_CTX_CACHE_DATA                             0x000010c4
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
+#define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
+#define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
+
+#define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
+#define BNX2_CTX_CAM_CTRL                               0x000010d4
+#define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
+#define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
+#define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
+#define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
+#define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
+#define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
 
 
 /*
@@ -1407,14 +2535,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
-#define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
+#define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
-#define BNX2_EMAC_MODE_25G                               (1L<<5)
+#define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
+#define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
+#define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
@@ -1422,6 +2552,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_STATUS                                0x00001404
 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
+#define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
+#define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
@@ -1429,6 +2564,9 @@ struct l2_fhdr {
 
 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
+#define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
+#define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
+#define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
@@ -1445,6 +2583,13 @@ struct l2_fhdr {
 #define BNX2_EMAC_LED_100MB                              (1L<<8)
 #define BNX2_EMAC_LED_10MB                               (1L<<9)
 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
+#define BNX2_EMAC_LED_2500MB                             (1L<<11)
+#define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
+#define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
+#define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
 
@@ -1515,9 +2660,15 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
@@ -1534,13 +2685,17 @@ struct l2_fhdr {
 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
+#define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
+#define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
 
 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
 
 #define BNX2_EMAC_TX_MODE                               0x000014bc
 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
+#define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
@@ -1553,6 +2708,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
+#define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
 
 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
@@ -1586,6 +2742,10 @@ struct l2_fhdr {
 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
+#define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
@@ -1608,7 +2768,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
-#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
@@ -1661,9 +2821,9 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
-#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
@@ -1701,7 +2861,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
-#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
+#define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
 
@@ -1733,6 +2893,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
 
+#define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
@@ -1757,6 +2918,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
+#define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
@@ -1777,7 +2939,7 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
-#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
@@ -1843,16 +3005,16 @@ struct l2_fhdr {
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
-#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
@@ -1887,8 +3049,11 @@ struct l2_fhdr {
 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
-#define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
+#define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
 
 
 /*