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authorJeff Garzik <jeff@garzik.org>2006-09-13 13:24:59 -0400
committerJeff Garzik <jeff@garzik.org>2006-09-13 13:24:59 -0400
commit6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch)
treedf0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/bnx2.h
parent7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff)
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r--drivers/net/bnx2.h82
1 files changed, 41 insertions, 41 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index fe804763c607..ca31904893ea 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -22,9 +22,9 @@
22 */ 22 */
23struct tx_bd { 23struct tx_bd {
24 u32 tx_bd_haddr_hi; 24 u32 tx_bd_haddr_hi;
25 u32 tx_bd_haddr_lo; 25 u32 tx_bd_haddr_lo;
26 u32 tx_bd_mss_nbytes; 26 u32 tx_bd_mss_nbytes;
27 u32 tx_bd_vlan_tag_flags; 27 u32 tx_bd_vlan_tag_flags;
28 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 28 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
29 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 29 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
30 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 30 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
@@ -3893,7 +3893,7 @@ struct bnx2 {
3893 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); 3893 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
3894 u16 hw_tx_cons; 3894 u16 hw_tx_cons;
3895 3895
3896#ifdef BCM_VLAN 3896#ifdef BCM_VLAN
3897 struct vlan_group *vlgrp; 3897 struct vlan_group *vlgrp;
3898#endif 3898#endif
3899 3899
@@ -3950,7 +3950,7 @@ struct bnx2 {
3950#define CHIP_REV_Ax 0x00000000 3950#define CHIP_REV_Ax 0x00000000
3951#define CHIP_REV_Bx 0x00001000 3951#define CHIP_REV_Bx 0x00001000
3952#define CHIP_REV_Cx 0x00002000 3952#define CHIP_REV_Cx 0x00002000
3953 3953
3954#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 3954#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
3955#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) 3955#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
3956 3956
@@ -3969,7 +3969,7 @@ struct bnx2 {
3969 3969
3970 u32 phy_addr; 3970 u32 phy_addr;
3971 u32 phy_id; 3971 u32 phy_id;
3972 3972
3973 u16 bus_speed_mhz; 3973 u16 bus_speed_mhz;
3974 u8 wol; 3974 u8 wol;
3975 3975
@@ -4025,7 +4025,7 @@ struct bnx2 {
4025 4025
4026 u32 advertising; 4026 u32 advertising;
4027 4027
4028 u8 req_flow_ctrl; /* flow ctrl advertisement */ 4028 u8 req_flow_ctrl; /* flow ctrl advertisement */
4029 /* settings or forced */ 4029 /* settings or forced */
4030 /* settings */ 4030 /* settings */
4031 u8 autoneg; 4031 u8 autoneg;
@@ -4179,7 +4179,7 @@ struct fw_info {
4179#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000 4179#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
4180#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000 4180#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
4181#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000 4181#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
4182 4182
4183#define BNX2_DRV_MSG_SEQ 0x0000ffff 4183#define BNX2_DRV_MSG_SEQ 0x0000ffff
4184 4184
4185#define BNX2_FW_MB 0x00000008 4185#define BNX2_FW_MB 0x00000008
@@ -4189,38 +4189,38 @@ struct fw_info {
4189#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 4189#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
4190 4190
4191#define BNX2_LINK_STATUS 0x0000000c 4191#define BNX2_LINK_STATUS 0x0000000c
4192#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff 4192#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
4193#define BNX2_LINK_STATUS_LINK_UP 0x1 4193#define BNX2_LINK_STATUS_LINK_UP 0x1
4194#define BNX2_LINK_STATUS_LINK_DOWN 0x0 4194#define BNX2_LINK_STATUS_LINK_DOWN 0x0
4195#define BNX2_LINK_STATUS_SPEED_MASK 0x1e 4195#define BNX2_LINK_STATUS_SPEED_MASK 0x1e
4196#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) 4196#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
4197#define BNX2_LINK_STATUS_10HALF (1<<1) 4197#define BNX2_LINK_STATUS_10HALF (1<<1)
4198#define BNX2_LINK_STATUS_10FULL (2<<1) 4198#define BNX2_LINK_STATUS_10FULL (2<<1)
4199#define BNX2_LINK_STATUS_100HALF (3<<1) 4199#define BNX2_LINK_STATUS_100HALF (3<<1)
4200#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) 4200#define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
4201#define BNX2_LINK_STATUS_100FULL (5<<1) 4201#define BNX2_LINK_STATUS_100FULL (5<<1)
4202#define BNX2_LINK_STATUS_1000HALF (6<<1) 4202#define BNX2_LINK_STATUS_1000HALF (6<<1)
4203#define BNX2_LINK_STATUS_1000FULL (7<<1) 4203#define BNX2_LINK_STATUS_1000FULL (7<<1)
4204#define BNX2_LINK_STATUS_2500HALF (8<<1) 4204#define BNX2_LINK_STATUS_2500HALF (8<<1)
4205#define BNX2_LINK_STATUS_2500FULL (9<<1) 4205#define BNX2_LINK_STATUS_2500FULL (9<<1)
4206#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) 4206#define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
4207#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) 4207#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
4208#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) 4208#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
4209#define BNX2_LINK_STATUS_RESERVED (1<<8) 4209#define BNX2_LINK_STATUS_RESERVED (1<<8)
4210#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 4210#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
4211#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 4211#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
4212#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 4212#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
4213#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 4213#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
4214#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 4214#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
4215#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 4215#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
4216#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 4216#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
4217#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) 4217#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
4218#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) 4218#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
4219#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 4219#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
4220#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 4220#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
4221#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) 4221#define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
4222#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 4222#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
4223#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 4223#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
4224 4224
4225#define BNX2_DRV_PULSE_MB 0x00000010 4225#define BNX2_DRV_PULSE_MB 0x00000010
4226#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff 4226#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
@@ -4400,7 +4400,7 @@ struct fw_info {
4400 0x00020000) 4400 0x00020000)
4401#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ 4401#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
4402 0x00030000) 4402 0x00030000)
4403#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 4403#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
4404#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \ 4404#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
4405 DRV_MSG_CODE_RESET) 4405 DRV_MSG_CODE_RESET)
4406#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \ 4406#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
@@ -4443,7 +4443,7 @@ struct fw_info {
4443#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) 4443#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
4444#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) 4444#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
4445#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) 4445#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
4446 4446
4447#define BNX2_BC_STATE_DEBUG_CMD 0x1dc 4447#define BNX2_BC_STATE_DEBUG_CMD 0x1dc
4448#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 4448#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
4449#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 4449#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000