diff options
author | Michael Chan <mchan@broadcom.com> | 2005-11-04 11:51:21 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2005-11-05 21:00:03 -0500 |
commit | e3648b3d8de3b37fae7acbb57db1e001a19cd3b7 (patch) | |
tree | 3de20299e878d60d7b5904f572f325f432e8891e /drivers/net/bnx2.h | |
parent | 371377091dff14090cbe995d0a9291364f8583cb (diff) |
[PATCH] bnx2: update firmware handshake for 5708
Dynamically determine the shared memory location where eeprom
parameters are stored instead of using a fixed location.
Add speed reporting to management firmware. This allows management
firmware to know the current speed without contending for MII
registers.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r-- | drivers/net/bnx2.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 4a2e6ba7cd70..012586e4ba0b 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h | |||
@@ -3715,6 +3715,15 @@ struct l2_fhdr { | |||
3715 | #define BNX2_MCP_ROM 0x00150000 | 3715 | #define BNX2_MCP_ROM 0x00150000 |
3716 | #define BNX2_MCP_SCRATCH 0x00160000 | 3716 | #define BNX2_MCP_SCRATCH 0x00160000 |
3717 | 3717 | ||
3718 | #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH | ||
3719 | #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 | ||
3720 | #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000 | ||
3721 | #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff | ||
3722 | #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 | ||
3723 | |||
3724 | #define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4 | ||
3725 | #define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8 | ||
3726 | |||
3718 | 3727 | ||
3719 | #define NUM_MC_HASH_REGISTERS 8 | 3728 | #define NUM_MC_HASH_REGISTERS 8 |
3720 | 3729 | ||
@@ -4052,6 +4061,8 @@ struct bnx2 { | |||
4052 | 4061 | ||
4053 | u8 mac_addr[8]; | 4062 | u8 mac_addr[8]; |
4054 | 4063 | ||
4064 | u32 shmem_base; | ||
4065 | |||
4055 | u32 fw_ver; | 4066 | u32 fw_ver; |
4056 | 4067 | ||
4057 | int pm_cap; | 4068 | int pm_cap; |
@@ -4191,6 +4202,38 @@ struct fw_info { | |||
4191 | #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 | 4202 | #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 |
4192 | 4203 | ||
4193 | #define BNX2_LINK_STATUS 0x0000000c | 4204 | #define BNX2_LINK_STATUS 0x0000000c |
4205 | #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff | ||
4206 | #define BNX2_LINK_STATUS_LINK_UP 0x1 | ||
4207 | #define BNX2_LINK_STATUS_LINK_DOWN 0x0 | ||
4208 | #define BNX2_LINK_STATUS_SPEED_MASK 0x1e | ||
4209 | #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) | ||
4210 | #define BNX2_LINK_STATUS_10HALF (1<<1) | ||
4211 | #define BNX2_LINK_STATUS_10FULL (2<<1) | ||
4212 | #define BNX2_LINK_STATUS_100HALF (3<<1) | ||
4213 | #define BNX2_LINK_STATUS_100BASE_T4 (4<<1) | ||
4214 | #define BNX2_LINK_STATUS_100FULL (5<<1) | ||
4215 | #define BNX2_LINK_STATUS_1000HALF (6<<1) | ||
4216 | #define BNX2_LINK_STATUS_1000FULL (7<<1) | ||
4217 | #define BNX2_LINK_STATUS_2500HALF (8<<1) | ||
4218 | #define BNX2_LINK_STATUS_2500FULL (9<<1) | ||
4219 | #define BNX2_LINK_STATUS_AN_ENABLED (1<<5) | ||
4220 | #define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) | ||
4221 | #define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) | ||
4222 | #define BNX2_LINK_STATUS_RESERVED (1<<8) | ||
4223 | #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) | ||
4224 | #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) | ||
4225 | #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) | ||
4226 | #define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) | ||
4227 | #define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) | ||
4228 | #define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) | ||
4229 | #define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) | ||
4230 | #define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) | ||
4231 | #define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) | ||
4232 | #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) | ||
4233 | #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) | ||
4234 | #define BNX2_LINK_STATUS_SERDES_LINK (1<<20) | ||
4235 | #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) | ||
4236 | #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) | ||
4194 | 4237 | ||
4195 | #define BNX2_DRV_PULSE_MB 0x00000010 | 4238 | #define BNX2_DRV_PULSE_MB 0x00000010 |
4196 | #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff | 4239 | #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff |