[BNX2]: Add new 5709 registers (part 2).

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1410 insertions, 22 deletions

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 73c785585fc3..13b6f9b11e01 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -3074,8 +3074,15 @@ struct l2_fhdr {
 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
+#define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
 
+#define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
+#define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
+
 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
 
@@ -3096,6 +3103,7 @@ struct l2_fhdr {
 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
+#define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
 
 #define BNX2_RPM_SORT_USER1                             0x00001824
@@ -3133,11 +3141,187 @@ struct l2_fhdr {
 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
+
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
+#define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
+
 #define BNX2_RPM_STAT_AC0                               0x00001880
 #define BNX2_RPM_STAT_AC1                               0x00001884
 #define BNX2_RPM_STAT_AC2                               0x00001888
 #define BNX2_RPM_STAT_AC3                               0x0000188c
 #define BNX2_RPM_STAT_AC4                               0x00001890
+#define BNX2_RPM_RC_CNTL_16                             0x000018e0
+#define BNX2_RPM_RC_CNTL_16_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_16_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_16_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_16_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_16_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_16_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_16_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_16_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_16_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_16_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_16_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_16_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_16_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_16_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_16_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_16                       0x000018e4
+#define BNX2_RPM_RC_VALUE_MASK_16_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_16_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_17                             0x000018e8
+#define BNX2_RPM_RC_CNTL_17_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_17_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_17_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_17_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_17_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_17_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_17_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_17_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_17_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_17_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_17_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_17_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_17_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_17_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_17_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_17                       0x000018ec
+#define BNX2_RPM_RC_VALUE_MASK_17_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_17_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_18                             0x000018f0
+#define BNX2_RPM_RC_CNTL_18_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_18_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_18_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_18_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_18_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_18_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_18_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_18_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_18_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_18_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_18_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_18_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_18_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_18_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_18_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_18                       0x000018f4
+#define BNX2_RPM_RC_VALUE_MASK_18_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_18_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_19                             0x000018f8
+#define BNX2_RPM_RC_CNTL_19_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_19_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_19_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_19_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP                 (2L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP                 (3L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP             (5L<<13)
+#define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6              (6L<<13)
+#define BNX2_RPM_RC_CNTL_19_COMP                         (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_GREATER                 (2L<<16)
+#define BNX2_RPM_RC_CNTL_19_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_19_MAP                          (1L<<18)
+#define BNX2_RPM_RC_CNTL_19_SBIT                         (1L<<19)
+#define BNX2_RPM_RC_CNTL_19_CMDSEL                       (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_19_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_19_MASK                         (1L<<26)
+#define BNX2_RPM_RC_CNTL_19_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_19_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_19_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_19_NBIT                         (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_19                       0x000018fc
+#define BNX2_RPM_RC_VALUE_MASK_19_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_19_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_0                              0x00001900
 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
@@ -3149,14 +3333,18 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP              (5L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6               (6L<<13)
 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
+#define BNX2_RPM_RC_CNTL_0_MAP_XI                        (1L<<18)
 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
+#define BNX2_RPM_RC_CNTL_0_CMDSEL_XI                     (0x1fL<<20)
 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
@@ -3171,81 +3359,518 @@ struct l2_fhdr {
 #define BNX2_RPM_RC_CNTL_1                              0x00001908
 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_1_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_1_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_1_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_1_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_1_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_1_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_1_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_1_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_1_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_1_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_1_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_1_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_1_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_1_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
+#define BNX2_RPM_RC_VALUE_MASK_1_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_1_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_2                              0x00001910
 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_2_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_2_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_2_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_2_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_2_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_2_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_2_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_2_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_2_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_2_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_2_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_2_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_2_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_2_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
+#define BNX2_RPM_RC_VALUE_MASK_2_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_2_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_3                              0x00001918
 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_3_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_3_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_3_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_3_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_3_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_3_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_3_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_3_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_3_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_3_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_3_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_3_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_3_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_3_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
+#define BNX2_RPM_RC_VALUE_MASK_3_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_3_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_4                              0x00001920
 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_4_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_4_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_4_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_4_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_4_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_4_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_4_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_4_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_4_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_4_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_4_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_4_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_4_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_4_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
+#define BNX2_RPM_RC_VALUE_MASK_4_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_4_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_5                              0x00001928
 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_5_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_5_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_5_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_5_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_5_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_5_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_5_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_5_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_5_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_5_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_5_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_5_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_5_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_5_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
+#define BNX2_RPM_RC_VALUE_MASK_5_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_5_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_6                              0x00001930
 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_6_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_6_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_6_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_6_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_6_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_6_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_6_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_6_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_6_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_6_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_6_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_6_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_6_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_6_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
+#define BNX2_RPM_RC_VALUE_MASK_6_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_6_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_7                              0x00001938
 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_7_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_7_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_7_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_7_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_7_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_7_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_7_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_7_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_7_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_7_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_7_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_7_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_7_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_7_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
+#define BNX2_RPM_RC_VALUE_MASK_7_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_7_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_8                              0x00001940
 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_8_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_8_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_8_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_8_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_8_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_8_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_8_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_8_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_8_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_8_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_8_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_8_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_8_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_8_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
+#define BNX2_RPM_RC_VALUE_MASK_8_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_8_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_9                              0x00001948
 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_9_OFFSET_XI                     (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_9_CLASS_XI                      (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_9_PRIORITY_XI                   (1L<<11)
+#define BNX2_RPM_RC_CNTL_9_P4_XI                         (1L<<12)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI                   (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI             (0L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI                (1L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI               (2L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI               (3L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI              (4L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI           (5L<<13)
+#define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI            (6L<<13)
+#define BNX2_RPM_RC_CNTL_9_COMP_XI                       (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI                 (0L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI                (1L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI               (2L<<16)
+#define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI                  (3L<<16)
+#define BNX2_RPM_RC_CNTL_9_MAP_XI                        (1L<<18)
+#define BNX2_RPM_RC_CNTL_9_SBIT_XI                       (1L<<19)
+#define BNX2_RPM_RC_CNTL_9_CMDSEL_XI                     (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_9_DISCARD_XI                    (1L<<25)
+#define BNX2_RPM_RC_CNTL_9_MASK_XI                       (1L<<26)
+#define BNX2_RPM_RC_CNTL_9_P1_XI                         (1L<<27)
+#define BNX2_RPM_RC_CNTL_9_P2_XI                         (1L<<28)
+#define BNX2_RPM_RC_CNTL_9_P3_XI                         (1L<<29)
+#define BNX2_RPM_RC_CNTL_9_NBIT_XI                       (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
+#define BNX2_RPM_RC_VALUE_MASK_9_VALUE                   (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_9_MASK                    (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_10                             0x00001950
 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_10_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_10_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_10_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_10_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_10_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_10_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_10_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_10_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_10_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_10_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_10_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_10_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_10_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_10_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
+#define BNX2_RPM_RC_VALUE_MASK_10_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_10_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_11                             0x00001958
 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_11_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_11_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_11_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_11_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_11_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_11_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_11_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_11_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_11_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_11_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_11_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_11_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_11_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_11_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
+#define BNX2_RPM_RC_VALUE_MASK_11_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_11_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_12                             0x00001960
 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_12_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_12_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_12_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_12_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_12_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_12_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_12_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_12_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_12_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_12_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_12_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_12_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_12_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_12_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
+#define BNX2_RPM_RC_VALUE_MASK_12_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_12_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_13                             0x00001968
 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_13_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_13_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_13_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_13_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_13_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_13_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_13_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_13_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_13_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_13_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_13_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_13_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_13_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_13_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
+#define BNX2_RPM_RC_VALUE_MASK_13_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_13_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_14                             0x00001970
 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_14_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_14_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_14_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_14_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_14_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_14_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_14_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_14_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_14_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_14_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_14_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_14_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_14_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_14_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
+#define BNX2_RPM_RC_VALUE_MASK_14_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_14_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CNTL_15                             0x00001978
 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
+#define BNX2_RPM_RC_CNTL_15_OFFSET_XI                    (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_15_CLASS_XI                     (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_15_PRIORITY_XI                  (1L<<11)
+#define BNX2_RPM_RC_CNTL_15_P4_XI                        (1L<<12)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI                  (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI            (0L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI               (1L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI              (2L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI              (3L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI             (4L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI          (5L<<13)
+#define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI           (6L<<13)
+#define BNX2_RPM_RC_CNTL_15_COMP_XI                      (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI                (0L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI               (1L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI              (2L<<16)
+#define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI                 (3L<<16)
+#define BNX2_RPM_RC_CNTL_15_MAP_XI                       (1L<<18)
+#define BNX2_RPM_RC_CNTL_15_SBIT_XI                      (1L<<19)
+#define BNX2_RPM_RC_CNTL_15_CMDSEL_XI                    (0x1fL<<20)
+#define BNX2_RPM_RC_CNTL_15_DISCARD_XI                   (1L<<25)
+#define BNX2_RPM_RC_CNTL_15_MASK_XI                      (1L<<26)
+#define BNX2_RPM_RC_CNTL_15_P1_XI                        (1L<<27)
+#define BNX2_RPM_RC_CNTL_15_P2_XI                        (1L<<28)
+#define BNX2_RPM_RC_CNTL_15_P3_XI                        (1L<<29)
+#define BNX2_RPM_RC_CNTL_15_NBIT_XI                      (1L<<30)
 
 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
+#define BNX2_RPM_RC_VALUE_MASK_15_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_15_MASK                   (0xffffL<<16)
+
 #define BNX2_RPM_RC_CONFIG                              0x00001980
 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
+#define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI                (0xfffffL<<0)
 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
+#define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE                (1L<<31)
 
 #define BNX2_RPM_DEBUG0                                 0x00001984
 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
@@ -3401,6 +4026,16 @@ struct l2_fhdr {
 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
+#define BNX2_RPM_DEBUG9_BEMEM_R_XI                       (0x1fL<<0)
+#define BNX2_RPM_DEBUG9_EO_XI                            (1L<<5)
+#define BNX2_RPM_DEBUG9_AEOF_DE_XI                       (1L<<6)
+#define BNX2_RPM_DEBUG9_SO_XI                            (1L<<7)
+#define BNX2_RPM_DEBUG9_WD64_CT_XI                       (0x1fL<<8)
+#define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI                   (0x7L<<13)
+#define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI               (0xfL<<16)
+#define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI                 (0x3ffL<<20)
+#define BNX2_RPM_DEBUG9_DATA_IN_VL_XI                    (1L<<30)
+#define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI             (1L<<31)
 
 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
@@ -3418,6 +4053,56 @@ struct l2_fhdr {
 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL                  0x00001a00
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS      (0xffffL<<0)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD           (1L<<28)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE              (1L<<29)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT              (1L<<30)
+#define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR                (1L<<31)
+
+#define BNX2_RPM_ACPI_PATTERN_CTRL                      0x00001a04
+#define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID            (0xfL<<0)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR            (1L<<30)
+#define BNX2_RPM_ACPI_PATTERN_CTRL_WR                    (1L<<31)
+
+#define BNX2_RPM_ACPI_DATA                              0x00001a08
+#define BNX2_RPM_ACPI_DATA_PATTERN_BE                    (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN0                      0x00001a0c
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_LEN1                      0x00001a10
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7          (0xffL<<0)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6          (0xffL<<8)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5          (0xffL<<16)
+#define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4          (0xffL<<24)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC0                      0x00001a18
+#define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC1                      0x00001a1c
+#define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC2                      0x00001a20
+#define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC3                      0x00001a24
+#define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC4                      0x00001a28
+#define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC5                      0x00001a2c
+#define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC6                      0x00001a30
+#define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6          (0xffffffffL<<0)
+
+#define BNX2_RPM_ACPI_PATTERN_CRC7                      0x00001a34
+#define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7          (0xffffffffL<<0)
 
 
 /*
@@ -3428,15 +4113,20 @@ struct l2_fhdr {
 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
+#define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL                (1L<<3)
 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE                (1L<<6)
+#define BNX2_RBUF_COMMAND_CU_ISOLATE_XI                  (1L<<5)
+#define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI               (1L<<6)
+#define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI         (1L<<7)
 
 #define BNX2_RBUF_STATUS1                               0x00200004
 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
 
 #define BNX2_RBUF_STATUS2                               0x00200008
-#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
-#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
+#define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x1ffL<<0)
+#define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x1ffL<<16)
 
 #define BNX2_RBUF_CONFIG                                0x0020000c
 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
@@ -3444,16 +4134,21 @@ struct l2_fhdr {
 
 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
+#define BNX2_RBUF_FW_BUF_ALLOC_TYPE                      (1L<<16)
+#define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ                 (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_FREE_TYPE                       (1L<<25)
+#define BNX2_RBUF_FW_BUF_FREE_FREE_REQ                   (1L<<31)
 
 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
+#define BNX2_RBUF_FW_BUF_SEL_SEL_REQ                     (1L<<31)
 
 #define BNX2_RBUF_CONFIG2                               0x0020001c
 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
@@ -3541,6 +4236,8 @@ struct l2_fhdr {
 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
 
 #define BNX2_RV2P_INSTR_LOW                             0x00002834
+#define BNX2_RV2P_INSTR_LOW_LOW                          (0xffffffffL<<0)
+
 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
@@ -3560,7 +4257,29 @@ struct l2_fhdr {
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_RV2P_PFTQ_DATA                             0x00002b40
+#define BNX2_RV2P_MPFE_PFE_CTL                          0x00002afc
+#define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT             (1L<<0)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE                  (0xfL<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0                (0L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1                (1L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2                (2L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3                (3L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4                (4L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5                (5L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6                (6L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7                (7L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8                (8L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9                (9L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10               (10L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11               (11L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12               (12L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13               (13L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14               (14L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15               (15L<<4)
+#define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT                 (0xfL<<12)
+#define BNX2_RV2P_MPFE_PFE_CTL_OFFSET                    (0x1ffL<<16)
+
+#define BNX2_RV2P_RV2PPQ                                0x00002b40
 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
@@ -3581,7 +4300,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_TFTQ_DATA                             0x00002b80
+#define BNX2_RV2P_RV2PTQ                                0x00002b80
 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
@@ -3602,7 +4321,7 @@ struct l2_fhdr {
 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
 
-#define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
+#define BNX2_RV2P_RV2PMQ                                0x00002bc0
 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
@@ -3631,18 +4350,26 @@ struct l2_fhdr {
  */
 #define BNX2_MQ_COMMAND                                 0x00003c00
 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
+#define BNX2_MQ_COMMAND_INIT                             (1L<<1)
 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
+#define BNX2_MQ_COMMAND_IDB_CFG_ERROR                    (1L<<7)
+#define BNX2_MQ_COMMAND_IDB_OVERFLOW                     (1L<<10)
+#define BNX2_MQ_COMMAND_NO_BIN_ERROR                     (1L<<11)
+#define BNX2_MQ_COMMAND_NO_MAP_ERROR                     (1L<<12)
 
 #define BNX2_MQ_STATUS                                  0x00003c04
 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
+#define BNX2_MQ_STATUS_IDB_OFLOW_STAT                    (1L<<19)
 
 #define BNX2_MQ_CONFIG                                  0x00003c08
 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
+#define BNX2_MQ_CONFIG_BIN_MQ_MODE                       (1L<<2)
+#define BNX2_MQ_CONFIG_DIS_IDB_DROP                      (1L<<3)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
@@ -3698,6 +4425,7 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_WR_DATA2_VALUE_XI                    (0x7fffffffL<<0)
 
 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
@@ -3710,6 +4438,16 @@ struct l2_fhdr {
 
 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
+#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI                    (0x7fffffffL<<0)
+
+
+/*
+ *  tsch_reg definition
+ *  offset: 0x4c00
+ */
+#define BNX2_TSCH_TSS_CFG                               0x00004c1c
+#define BNX2_TSCH_TSS_CFG_TSS_START_CID                  (0x7ffL<<8)
+#define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON                 (0xfL<<24)
 
 
 
@@ -3759,7 +4497,11 @@ struct l2_fhdr {
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
 
-#define BNX2_TBDR_FTQ_DATA                              0x000053c0
+#define BNX2_TBDR_CKSUM_ERROR_STATUS                    0x00005010
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
+#define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
+
+#define BNX2_TBDR_TBDRQ                                 0x000053c0
 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -3789,7 +4531,15 @@ struct l2_fhdr {
 #define BNX2_TDMA_COMMAND                               0x00005c00
 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
+#define BNX2_TDMA_COMMAND_CS16_ERR                       (1L<<5)
 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
+#define BNX2_TDMA_COMMAND_MASK_CS1                       (1L<<20)
+#define BNX2_TDMA_COMMAND_MASK_CS2                       (1L<<21)
+#define BNX2_TDMA_COMMAND_MASK_CS3                       (1L<<22)
+#define BNX2_TDMA_COMMAND_MASK_CS4                       (1L<<23)
+#define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR              (1L<<24)
+#define BNX2_TDMA_COMMAND_OFIFO_CLR                      (1L<<30)
+#define BNX2_TDMA_COMMAND_IFIFO_CLR                      (1L<<31)
 
 #define BNX2_TDMA_STATUS                                0x00005c04
 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
@@ -3798,10 +4548,18 @@ struct l2_fhdr {
 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
+#define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH                 (0x3fL<<20)
+#define BNX2_TDMA_STATUS_OFIFO_OVERFLOW                  (1L<<30)
+#define BNX2_TDMA_STATUS_IFIFO_OVERFLOW                  (1L<<31)
 
 #define BNX2_TDMA_CONFIG                                0x00005c08
 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN                    (0x3L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0                  (0L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1                  (1L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2                  (2L<<2)
+#define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3                  (3L<<2)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
@@ -3814,7 +4572,35 @@ struct l2_fhdr {
 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
+#define BNX2_TDMA_CONFIG_CMPL_ENTRY                      (1L<<17)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP                       (1L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_3                     (0L<<19)
+#define BNX2_TDMA_CONFIG_OFIFO_CMP_2                     (1L<<19)
 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI                  (0x7L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI                (0L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI                (1L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI                (2L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI               (3L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI               (4L<<20)
+#define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI               (5L<<20)
+#define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI                  (1L<<23)
+#define BNX2_TDMA_CONFIG_BYTES_OST_XI                    (0x7L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_512_XI                (0L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI               (1L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI               (2L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI               (3L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI               (4L<<24)
+#define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI              (5L<<24)
+#define BNX2_TDMA_CONFIG_HC_BYPASS_XI                    (1L<<27)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_XI                     (0x7L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI                 (0L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI                 (1L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI                 (2L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI                (3L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI                (4L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI                (5L<<28)
+#define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI                  (1L<<31)
 
 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
@@ -3850,7 +4636,22 @@ struct l2_fhdr {
 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
 
-#define BNX2_TDMA_FTQ_DATA                              0x00005fc0
+#define BNX2_TDMA_PUSH_FSM                              0x00005c90
+#define BNX2_TDMA_BD_IF_DEBUG                           0x00005c94
+#define BNX2_TDMA_DMAD_IF_DEBUG                         0x00005c98
+#define BNX2_TDMA_CTX_IF_DEBUG                          0x00005c9c
+#define BNX2_TDMA_TPBUF_IF_DEBUG                        0x00005ca0
+#define BNX2_TDMA_DR_IF_DEBUG                           0x00005ca4
+#define BNX2_TDMA_TPATQ_IF_DEBUG                        0x00005ca8
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM                      0x00005cac
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED            (0xffffL<<0)
+#define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED              (0xffffL<<16)
+
+#define BNX2_TDMA_TDMA_PCIE_CKSUM                       0x00005cb0
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED             (0xffffL<<0)
+#define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED               (0xffffL<<16)
+
+#define BNX2_TDMA_TDMAQ                                 0x00005fc0
 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -3889,6 +4690,8 @@ struct l2_fhdr {
 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
+#define BNX2_HC_COMMAND_MAIN_PWR_INT                     (1L<<22)
+#define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT               (1L<<27)
 
 #define BNX2_HC_STATUS                                  0x00006804
 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
@@ -3911,6 +4714,23 @@ struct l2_fhdr {
 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
+#define BNX2_HC_CONFIG_PER_MODE                          (1L<<16)
+#define BNX2_HC_CONFIG_ONE_SHOT                          (1L<<17)
+#define BNX2_HC_CONFIG_USE_INT_PARAM                     (1L<<18)
+#define BNX2_HC_CONFIG_SET_MASK_AT_RD                    (1L<<19)
+#define BNX2_HC_CONFIG_PER_COLLECT_LIMIT                 (0xfL<<20)
+#define BNX2_HC_CONFIG_SB_ADDR_INC                       (0x7L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_64B                   (0L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_128B                  (1L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_256B                  (2L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_512B                  (3L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_1024B                 (4L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_2048B                 (5L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_4096B                 (6L<<24)
+#define BNX2_HC_CONFIG_SB_ADDR_INC_8192B                 (7L<<24)
+#define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR                 (1L<<29)
+#define BNX2_HC_CONFIG_UNMASK_ALL                        (1L<<30)
+#define BNX2_HC_CONFIG_TX_SEL                            (1L<<31)
 
 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
@@ -3947,6 +4767,7 @@ struct l2_fhdr {
 
 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS     (0xffffL<<16)
 
 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
@@ -3954,6 +4775,10 @@ struct l2_fhdr {
 #define BNX2_HC_STATS_TICKS                             0x00006844
 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
 
+#define BNX2_HC_STATS_INTERRUPT_STATUS                  0x00006848
+#define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS         (0x1ffL<<0)
+#define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS        (0x1ffL<<16)
+
 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
@@ -4082,24 +4907,108 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI    (52L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI    (57L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI    (58L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI    (85L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI    (86L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI    (87L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI    (88L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI    (89L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI    (90L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI    (91L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI    (92L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI   (93L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI         (94L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI       (123L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI       (124L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI     (125L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI   (126L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI    (128L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI  (129L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI      (130L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI       (131L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI       (132L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI   (133L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI    (134L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI  (135L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI      (136L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI       (137L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI       (138L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI   (139L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI    (140L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI  (141L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI      (142L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI       (143L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI       (144L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI   (145L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI    (146L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI  (147L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI      (148L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI       (149L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI       (150L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI   (151L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI    (152L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI  (153L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI      (154L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI       (155L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI       (156L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI   (157L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI    (158L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI  (159L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI      (160L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI       (161L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI       (162L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI   (163L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI    (164L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI  (165L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI      (166L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI       (167L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI       (168L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI   (169L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI    (170L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI  (171L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI      (172L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI       (173L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI       (174L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI   (175L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI       (176L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI      (177L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI    (178L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI              (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI              (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI              (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI              (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI             (0xffL<<0)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI             (0xffL<<8)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI             (0xffL<<16)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI             (0xffL<<24)
 
 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
@@ -4133,6 +5042,7 @@ struct l2_fhdr {
 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
+#define BNX2_HC_STAT_GEN_STAT_AC                        0x000068c8
 #define BNX2_HC_VIS                                     0x00006908
 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
@@ -4203,6 +5113,349 @@ struct l2_fhdr {
 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
 
+#define BNX2_HC_COALESCE_NOW                            0x00006914
+#define BNX2_HC_COALESCE_NOW_COAL_NOW                    (0x1ffL<<1)
+#define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT             (0x1ffL<<11)
+#define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT           (0x1ffL<<21)
+
+#define BNX2_HC_MSIX_BIT_VECTOR                         0x00006918
+#define BNX2_HC_MSIX_BIT_VECTOR_VAL                      (0x1ffL<<0)
+
+#define BNX2_HC_SB_CONFIG_1                             0x00006a00
+#define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_1_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_1_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1                    0x00006a04
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_1                        0x00006a08
+#define BNX2_HC_COMP_PROD_TRIP_1_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_1_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1                    0x00006a0c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_1                              0x00006a10
+#define BNX2_HC_RX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_1                              0x00006a14
+#define BNX2_HC_TX_TICKS_1_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_1_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_1                             0x00006a18
+#define BNX2_HC_COM_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_1                             0x00006a1c
+#define BNX2_HC_CMD_TICKS_1_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_1_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_1                        0x00006a20
+#define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_2                             0x00006a24
+#define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_2_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_2_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2                    0x00006a28
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_2                        0x00006a2c
+#define BNX2_HC_COMP_PROD_TRIP_2_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_2_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2                    0x00006a30
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_2                              0x00006a34
+#define BNX2_HC_RX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_2                              0x00006a38
+#define BNX2_HC_TX_TICKS_2_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_2_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_2                             0x00006a3c
+#define BNX2_HC_COM_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_2                             0x00006a40
+#define BNX2_HC_CMD_TICKS_2_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_2_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_2                        0x00006a44
+#define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_3                             0x00006a48
+#define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_3_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_3_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3                    0x00006a4c
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_3                        0x00006a50
+#define BNX2_HC_COMP_PROD_TRIP_3_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_3_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3                    0x00006a54
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_3                              0x00006a58
+#define BNX2_HC_RX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_3                              0x00006a5c
+#define BNX2_HC_TX_TICKS_3_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_3_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_3                             0x00006a60
+#define BNX2_HC_COM_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_3                             0x00006a64
+#define BNX2_HC_CMD_TICKS_3_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_3_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_3                        0x00006a68
+#define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_4                             0x00006a6c
+#define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_4_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_4_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4                    0x00006a70
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_4                        0x00006a74
+#define BNX2_HC_COMP_PROD_TRIP_4_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_4_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4                    0x00006a78
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_4                              0x00006a7c
+#define BNX2_HC_RX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_4                              0x00006a80
+#define BNX2_HC_TX_TICKS_4_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_4_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_4                             0x00006a84
+#define BNX2_HC_COM_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_4                             0x00006a88
+#define BNX2_HC_CMD_TICKS_4_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_4_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_4                        0x00006a8c
+#define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_5                             0x00006a90
+#define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_5_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_5_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5                    0x00006a94
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_5                        0x00006a98
+#define BNX2_HC_COMP_PROD_TRIP_5_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_5_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5                    0x00006a9c
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_5                              0x00006aa0
+#define BNX2_HC_RX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_5                              0x00006aa4
+#define BNX2_HC_TX_TICKS_5_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_5_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_5                             0x00006aa8
+#define BNX2_HC_COM_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_5                             0x00006aac
+#define BNX2_HC_CMD_TICKS_5_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_5_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_5                        0x00006ab0
+#define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_6                             0x00006ab4
+#define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_6_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_6_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6                    0x00006ab8
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_6                        0x00006abc
+#define BNX2_HC_COMP_PROD_TRIP_6_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_6_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6                    0x00006ac0
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_6                              0x00006ac4
+#define BNX2_HC_RX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_6                              0x00006ac8
+#define BNX2_HC_TX_TICKS_6_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_6_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_6                             0x00006acc
+#define BNX2_HC_COM_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_6                             0x00006ad0
+#define BNX2_HC_CMD_TICKS_6_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_6_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_6                        0x00006ad4
+#define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_7                             0x00006ad8
+#define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_7_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_7_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7                    0x00006adc
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_7                        0x00006ae0
+#define BNX2_HC_COMP_PROD_TRIP_7_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_7_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7                    0x00006ae4
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_7                              0x00006ae8
+#define BNX2_HC_RX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_7                              0x00006aec
+#define BNX2_HC_TX_TICKS_7_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_7_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_7                             0x00006af0
+#define BNX2_HC_COM_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_7                             0x00006af4
+#define BNX2_HC_CMD_TICKS_7_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_7_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_7                        0x00006af8
+#define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
+
+#define BNX2_HC_SB_CONFIG_8                             0x00006afc
+#define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE                  (1L<<1)
+#define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE                  (1L<<2)
+#define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE                 (1L<<3)
+#define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE                 (1L<<4)
+#define BNX2_HC_SB_CONFIG_8_PER_MODE                     (1L<<16)
+#define BNX2_HC_SB_CONFIG_8_ONE_SHOT                     (1L<<17)
+#define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM                (1L<<18)
+#define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT            (0xfL<<20)
+
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8                    0x00006b00
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP_8                        0x00006b04
+#define BNX2_HC_COMP_PROD_TRIP_8_VALUE                   (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_8_INT                     (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8                    0x00006b08
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS_8                              0x00006b0c
+#define BNX2_HC_RX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS_8                              0x00006b10
+#define BNX2_HC_TX_TICKS_8_VALUE                         (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_8_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS_8                             0x00006b14
+#define BNX2_HC_COM_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS_8                             0x00006b18
+#define BNX2_HC_CMD_TICKS_8_VALUE                        (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_8_INT                          (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS_8                        0x00006b1c
+#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS       (0xffffL<<0)
+#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
 
 
 /*
@@ -4228,7 +5481,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_TXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -4276,7 +5529,7 @@ struct l2_fhdr {
 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
-#define BNX2_TXP_FTQ_DATA                               0x000453c0
+#define BNX2_TXP_TXPQ                                   0x000453c0
 #define BNX2_TXP_FTQ_CMD                                0x000453f8
 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -4323,7 +5576,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
-#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED                (1L<<6)
 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
@@ -4371,7 +5624,7 @@ struct l2_fhdr {
 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
 
 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
-#define BNX2_TPAT_FTQ_DATA                              0x000853c0
+#define BNX2_TPAT_TPATQ                                 0x000853c0
 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
@@ -4418,7 +5671,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_RXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -4466,7 +5719,29 @@ struct l2_fhdr {
 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_RXP_CPU_REG_FILE                           0x000c5200
-#define BNX2_RXP_CFTQ_DATA                              0x000c5380
+#define BNX2_RXP_PFE_PFE_CTL                            0x000c537c
+#define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT               (1L<<0)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE                    (0xfL<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0                  (0L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1                  (1L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2                  (2L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3                  (3L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4                  (4L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5                  (5L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6                  (6L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7                  (7L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8                  (8L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9                  (9L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10                 (10L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11                 (11L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12                 (12L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13                 (13L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14                 (14L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15                 (15L<<4)
+#define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT                   (0xfL<<12)
+#define BNX2_RXP_PFE_PFE_CTL_OFFSET                      (0x1ffL<<16)
+
+#define BNX2_RXP_RXPCQ                                  0x000c5380
 #define BNX2_RXP_CFTQ_CMD                               0x000c53b8
 #define BNX2_RXP_CFTQ_CMD_OFFSET                         (0x3ffL<<0)
 #define BNX2_RXP_CFTQ_CMD_WR_TOP                         (1L<<10)
@@ -4487,7 +5762,7 @@ struct l2_fhdr {
 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
 
-#define BNX2_RXP_FTQ_DATA                               0x000c53c0
+#define BNX2_RXP_RXPQ                                   0x000c53c0
 #define BNX2_RXP_FTQ_CMD                                0x000c53f8
 #define BNX2_RXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
 #define BNX2_RXP_FTQ_CMD_WR_TOP                          (1L<<10)
@@ -4515,6 +5790,10 @@ struct l2_fhdr {
  *  com_reg definition
  *  offset: 0x100000
  */
+#define BNX2_COM_CKSUM_ERROR_STATUS                     0x00100000
+#define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
+#define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
+
 #define BNX2_COM_CPU_MODE                               0x00105000
 #define BNX2_COM_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_COM_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -4534,7 +5813,7 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_COM_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_COM_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_COM_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_COM_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -4582,7 +5861,29 @@ struct l2_fhdr {
 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_COM_CPU_REG_FILE                           0x00105200
-#define BNX2_COM_COMXQ_FTQ_DATA                         0x00105340
+#define BNX2_COM_COMTQ_PFE_PFE_CTL                      0x001052bc
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT         (1L<<0)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE              (0xfL<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0            (0L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1            (1L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2            (2L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3            (3L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4            (4L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5            (5L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6            (6L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7            (7L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8            (8L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9            (9L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10           (10L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11           (11L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12           (12L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13           (13L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14           (14L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15           (15L<<4)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT             (0xfL<<12)
+#define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET                (0x1ffL<<16)
+
+#define BNX2_COM_COMXQ                                  0x00105340
 #define BNX2_COM_COMXQ_FTQ_CMD                          0x00105378
 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -4603,7 +5904,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMTQ_FTQ_DATA                         0x00105380
+#define BNX2_COM_COMTQ                                  0x00105380
 #define BNX2_COM_COMTQ_FTQ_CMD                          0x001053b8
 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                    (1L<<10)
@@ -4624,7 +5925,7 @@ struct l2_fhdr {
 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
 
-#define BNX2_COM_COMQ_FTQ_DATA                          0x001053c0
+#define BNX2_COM_COMQ                                   0x001053c0
 #define BNX2_COM_COMQ_FTQ_CMD                           0x001053f8
 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -4654,6 +5955,10 @@ struct l2_fhdr {
  *  cp_reg definition
  *  offset: 0x180000
  */
+#define BNX2_CP_CKSUM_ERROR_STATUS                      0x00180000
+#define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED            (0xffffL<<0)
+#define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED              (0xffffL<<16)
+
 #define BNX2_CP_CPU_MODE                                0x00185000
 #define BNX2_CP_CPU_MODE_LOCAL_RST                       (1L<<0)
 #define BNX2_CP_CPU_MODE_STEP_ENA                        (1L<<1)
@@ -4673,7 +5978,7 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
-#define BNX2_CP_CPU_STATE_BAD_pc_HALTED                  (1L<<6)
+#define BNX2_CP_CPU_STATE_BAD_PC_HALTED                  (1L<<6)
 #define BNX2_CP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
 #define BNX2_CP_CPU_STATE_SOFT_HALTED                    (1L<<10)
@@ -4721,7 +6026,29 @@ struct l2_fhdr {
 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
 
 #define BNX2_CP_CPU_REG_FILE                            0x00185200
-#define BNX2_CP_CPQ_FTQ_DATA                            0x001853c0
+#define BNX2_CP_CPQ_PFE_PFE_CTL                         0x001853bc
+#define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT            (1L<<0)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE                 (0xfL<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0               (0L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1               (1L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2               (2L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3               (3L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4               (4L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5               (5L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6               (6L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7               (7L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8               (8L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9               (9L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10              (10L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11              (11L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12              (12L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13              (13L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14              (14L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15              (15L<<4)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT                (0xfL<<12)
+#define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET                   (0x1ffL<<16)
+
+#define BNX2_CP_CPQ                                     0x001853c0
 #define BNX2_CP_CPQ_FTQ_CMD                             0x001853f8
 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET                       (0x3ffL<<0)
 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                       (1L<<10)
@@ -4749,6 +6076,59 @@ struct l2_fhdr {
  *  mcp_reg definition
  *  offset: 0x140000
  */
+#define BNX2_MCP_MCP_CONTROL                            0x00140080
+#define BNX2_MCP_MCP_CONTROL_SMBUS_SEL                   (1L<<30)
+#define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE                 (1L<<31)
+
+#define BNX2_MCP_MCP_ATTENTION_STATUS                   0x00140084
+#define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL       (1L<<29)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT   (1L<<30)
+#define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT          (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL                  0x00140088
+#define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE      (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS                   0x0014008c
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD       (0x7ffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID              (1L<<31)
+
+#define BNX2_MCP_MCP_HEARTBEAT                          0x00140090
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT       (0x3fffffffL<<0)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC         (1L<<30)
+#define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET       (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_RESET                         0x00140094
+#define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET           (1L<<31)
+
+#define BNX2_MCP_WATCHDOG_CONTROL                       0x00140098
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT       (0xfffffffL<<0)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN          (1L<<29)
+#define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE         (1L<<30)
+#define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE        (1L<<31)
+
+#define BNX2_MCP_ACCESS_LOCK                            0x0014009c
+#define BNX2_MCP_ACCESS_LOCK_LOCK                        (1L<<31)
+
+#define BNX2_MCP_TOE_ID                                 0x001400a0
+#define BNX2_MCP_TOE_ID_FUNCTION_ID                      (1L<<31)
+
+#define BNX2_MCP_MAILBOX_CFG                            0x001400a4
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET              (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE                (0xfffL<<20)
+
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC                 0x001400a8
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET   (0x3fffL<<0)
+#define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE     (0xfffL<<20)
+
+#define BNX2_MCP_MCP_DOORBELL                           0x001400ac
+#define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL               (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL                        0x001400b0
+#define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL         (1L<<31)
+
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC             0x001400b4
+#define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL      (1L<<31)
+
 #define BNX2_MCP_CPU_MODE                               0x00145000
 #define BNX2_MCP_CPU_MODE_LOCAL_RST                      (1L<<0)
 #define BNX2_MCP_CPU_MODE_STEP_ENA                       (1L<<1)
@@ -4768,7 +6148,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
-#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
+#define BNX2_MCP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
 #define BNX2_MCP_CPU_STATE_SOFT_HALTED                   (1L<<10)
@@ -4816,7 +6196,7 @@ struct l2_fhdr {
 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
 
 #define BNX2_MCP_CPU_REG_FILE                           0x00145200
-#define BNX2_MCP_MCPQ_FTQ_DATA                          0x001453c0
+#define BNX2_MCP_MCPQ                                   0x001453c0
 #define BNX2_MCP_MCPQ_FTQ_CMD                           0x001453f8
 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                     (1L<<10)
@@ -4971,6 +6351,7 @@ struct l2_fhdr {
 #define INVALID_CID_ADDR            0xffffffff
 
 #define TX_CID          16
+#define TX_TSS_CID      32
 #define RX_CID          0
 
 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
@@ -5056,6 +6437,8 @@ struct bnx2 {
 
         u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
         u16             tx_prod;
+        u32             tx_bidx_addr;
+        u32             tx_bseq_addr;
 
         u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
         u16             hw_tx_cons;
@@ -5112,6 +6495,7 @@ struct bnx2 {
 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
 #define CHIP_NUM_5706                   0x57060000
 #define CHIP_NUM_5708                   0x57080000
+#define CHIP_NUM_5709                   0x57090000
 
 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
 #define CHIP_REV_Ax                     0x00000000
@@ -5174,6 +6558,10 @@ struct bnx2 {
         struct statistics_block *stats_blk;
         dma_addr_t              stats_blk_mapping;
 
+        int                     ctx_pages;
+        void                    *ctx_blk[4];
+        dma_addr_t              ctx_blk_mapping[4];
+
         u32                     hc_cmd;
         u32                     rx_mode;