diff options
author | Michael Chan <mchan@broadcom.com> | 2006-11-19 17:09:25 -0500 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2006-12-03 00:24:22 -0500 |
commit | af3ee519c5d6bebbda9bf0ca3b81bc50b4dd2163 (patch) | |
tree | 03c4e5e6c10210239109d8456801d1902fb06a49 /drivers/net/bnx2.c | |
parent | a16dda0e67cea666fb7eb708ab1199892c4a1a13 (diff) |
[BNX2]: Re-organize firmware structures.
Re-organize the firmware handling code and declarations a bit to make
the code more compact.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 164 |
1 files changed, 25 insertions, 139 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 0a46b45f21dd..2633579b8c43 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -2214,11 +2214,12 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, | |||
2214 | } | 2214 | } |
2215 | } | 2215 | } |
2216 | 2216 | ||
2217 | static void | 2217 | static int |
2218 | load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | 2218 | load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) |
2219 | { | 2219 | { |
2220 | u32 offset; | 2220 | u32 offset; |
2221 | u32 val; | 2221 | u32 val; |
2222 | int rc; | ||
2222 | 2223 | ||
2223 | /* Halt the CPU. */ | 2224 | /* Halt the CPU. */ |
2224 | val = REG_RD_IND(bp, cpu_reg->mode); | 2225 | val = REG_RD_IND(bp, cpu_reg->mode); |
@@ -2228,7 +2229,18 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
2228 | 2229 | ||
2229 | /* Load the Text area. */ | 2230 | /* Load the Text area. */ |
2230 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); | 2231 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); |
2231 | if (fw->text) { | 2232 | if (fw->gz_text) { |
2233 | u32 text_len; | ||
2234 | void *text; | ||
2235 | |||
2236 | rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text, | ||
2237 | &text_len); | ||
2238 | if (rc) | ||
2239 | return rc; | ||
2240 | |||
2241 | fw->text = text; | ||
2242 | } | ||
2243 | if (fw->gz_text) { | ||
2232 | int j; | 2244 | int j; |
2233 | 2245 | ||
2234 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { | 2246 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { |
@@ -2286,13 +2298,15 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | |||
2286 | val &= ~cpu_reg->mode_value_halt; | 2298 | val &= ~cpu_reg->mode_value_halt; |
2287 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | 2299 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); |
2288 | REG_WR_IND(bp, cpu_reg->mode, val); | 2300 | REG_WR_IND(bp, cpu_reg->mode, val); |
2301 | |||
2302 | return 0; | ||
2289 | } | 2303 | } |
2290 | 2304 | ||
2291 | static int | 2305 | static int |
2292 | bnx2_init_cpus(struct bnx2 *bp) | 2306 | bnx2_init_cpus(struct bnx2 *bp) |
2293 | { | 2307 | { |
2294 | struct cpu_reg cpu_reg; | 2308 | struct cpu_reg cpu_reg; |
2295 | struct fw_info fw; | 2309 | struct fw_info *fw; |
2296 | int rc = 0; | 2310 | int rc = 0; |
2297 | void *text; | 2311 | void *text; |
2298 | u32 text_len; | 2312 | u32 text_len; |
@@ -2329,44 +2343,12 @@ bnx2_init_cpus(struct bnx2 *bp) | |||
2329 | cpu_reg.spad_base = BNX2_RXP_SCRATCH; | 2343 | cpu_reg.spad_base = BNX2_RXP_SCRATCH; |
2330 | cpu_reg.mips_view_base = 0x8000000; | 2344 | cpu_reg.mips_view_base = 0x8000000; |
2331 | 2345 | ||
2332 | fw.ver_major = bnx2_RXP_b06FwReleaseMajor; | 2346 | fw = &bnx2_rxp_fw_06; |
2333 | fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; | ||
2334 | fw.ver_fix = bnx2_RXP_b06FwReleaseFix; | ||
2335 | fw.start_addr = bnx2_RXP_b06FwStartAddr; | ||
2336 | 2347 | ||
2337 | fw.text_addr = bnx2_RXP_b06FwTextAddr; | 2348 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
2338 | fw.text_len = bnx2_RXP_b06FwTextLen; | ||
2339 | fw.text_index = 0; | ||
2340 | |||
2341 | rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText), | ||
2342 | &text, &text_len); | ||
2343 | if (rc) | 2349 | if (rc) |
2344 | goto init_cpu_err; | 2350 | goto init_cpu_err; |
2345 | 2351 | ||
2346 | fw.text = text; | ||
2347 | |||
2348 | fw.data_addr = bnx2_RXP_b06FwDataAddr; | ||
2349 | fw.data_len = bnx2_RXP_b06FwDataLen; | ||
2350 | fw.data_index = 0; | ||
2351 | fw.data = bnx2_RXP_b06FwData; | ||
2352 | |||
2353 | fw.sbss_addr = bnx2_RXP_b06FwSbssAddr; | ||
2354 | fw.sbss_len = bnx2_RXP_b06FwSbssLen; | ||
2355 | fw.sbss_index = 0; | ||
2356 | fw.sbss = bnx2_RXP_b06FwSbss; | ||
2357 | |||
2358 | fw.bss_addr = bnx2_RXP_b06FwBssAddr; | ||
2359 | fw.bss_len = bnx2_RXP_b06FwBssLen; | ||
2360 | fw.bss_index = 0; | ||
2361 | fw.bss = bnx2_RXP_b06FwBss; | ||
2362 | |||
2363 | fw.rodata_addr = bnx2_RXP_b06FwRodataAddr; | ||
2364 | fw.rodata_len = bnx2_RXP_b06FwRodataLen; | ||
2365 | fw.rodata_index = 0; | ||
2366 | fw.rodata = bnx2_RXP_b06FwRodata; | ||
2367 | |||
2368 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
2369 | |||
2370 | /* Initialize the TX Processor. */ | 2352 | /* Initialize the TX Processor. */ |
2371 | cpu_reg.mode = BNX2_TXP_CPU_MODE; | 2353 | cpu_reg.mode = BNX2_TXP_CPU_MODE; |
2372 | cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; | 2354 | cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; |
@@ -2381,44 +2363,12 @@ bnx2_init_cpus(struct bnx2 *bp) | |||
2381 | cpu_reg.spad_base = BNX2_TXP_SCRATCH; | 2363 | cpu_reg.spad_base = BNX2_TXP_SCRATCH; |
2382 | cpu_reg.mips_view_base = 0x8000000; | 2364 | cpu_reg.mips_view_base = 0x8000000; |
2383 | 2365 | ||
2384 | fw.ver_major = bnx2_TXP_b06FwReleaseMajor; | 2366 | fw = &bnx2_txp_fw_06; |
2385 | fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; | ||
2386 | fw.ver_fix = bnx2_TXP_b06FwReleaseFix; | ||
2387 | fw.start_addr = bnx2_TXP_b06FwStartAddr; | ||
2388 | 2367 | ||
2389 | fw.text_addr = bnx2_TXP_b06FwTextAddr; | 2368 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
2390 | fw.text_len = bnx2_TXP_b06FwTextLen; | ||
2391 | fw.text_index = 0; | ||
2392 | |||
2393 | rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText), | ||
2394 | &text, &text_len); | ||
2395 | if (rc) | 2369 | if (rc) |
2396 | goto init_cpu_err; | 2370 | goto init_cpu_err; |
2397 | 2371 | ||
2398 | fw.text = text; | ||
2399 | |||
2400 | fw.data_addr = bnx2_TXP_b06FwDataAddr; | ||
2401 | fw.data_len = bnx2_TXP_b06FwDataLen; | ||
2402 | fw.data_index = 0; | ||
2403 | fw.data = bnx2_TXP_b06FwData; | ||
2404 | |||
2405 | fw.sbss_addr = bnx2_TXP_b06FwSbssAddr; | ||
2406 | fw.sbss_len = bnx2_TXP_b06FwSbssLen; | ||
2407 | fw.sbss_index = 0; | ||
2408 | fw.sbss = bnx2_TXP_b06FwSbss; | ||
2409 | |||
2410 | fw.bss_addr = bnx2_TXP_b06FwBssAddr; | ||
2411 | fw.bss_len = bnx2_TXP_b06FwBssLen; | ||
2412 | fw.bss_index = 0; | ||
2413 | fw.bss = bnx2_TXP_b06FwBss; | ||
2414 | |||
2415 | fw.rodata_addr = bnx2_TXP_b06FwRodataAddr; | ||
2416 | fw.rodata_len = bnx2_TXP_b06FwRodataLen; | ||
2417 | fw.rodata_index = 0; | ||
2418 | fw.rodata = bnx2_TXP_b06FwRodata; | ||
2419 | |||
2420 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
2421 | |||
2422 | /* Initialize the TX Patch-up Processor. */ | 2372 | /* Initialize the TX Patch-up Processor. */ |
2423 | cpu_reg.mode = BNX2_TPAT_CPU_MODE; | 2373 | cpu_reg.mode = BNX2_TPAT_CPU_MODE; |
2424 | cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; | 2374 | cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; |
@@ -2433,44 +2383,12 @@ bnx2_init_cpus(struct bnx2 *bp) | |||
2433 | cpu_reg.spad_base = BNX2_TPAT_SCRATCH; | 2383 | cpu_reg.spad_base = BNX2_TPAT_SCRATCH; |
2434 | cpu_reg.mips_view_base = 0x8000000; | 2384 | cpu_reg.mips_view_base = 0x8000000; |
2435 | 2385 | ||
2436 | fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; | 2386 | fw = &bnx2_tpat_fw_06; |
2437 | fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; | ||
2438 | fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; | ||
2439 | fw.start_addr = bnx2_TPAT_b06FwStartAddr; | ||
2440 | 2387 | ||
2441 | fw.text_addr = bnx2_TPAT_b06FwTextAddr; | 2388 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
2442 | fw.text_len = bnx2_TPAT_b06FwTextLen; | ||
2443 | fw.text_index = 0; | ||
2444 | |||
2445 | rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText), | ||
2446 | &text, &text_len); | ||
2447 | if (rc) | 2389 | if (rc) |
2448 | goto init_cpu_err; | 2390 | goto init_cpu_err; |
2449 | 2391 | ||
2450 | fw.text = text; | ||
2451 | |||
2452 | fw.data_addr = bnx2_TPAT_b06FwDataAddr; | ||
2453 | fw.data_len = bnx2_TPAT_b06FwDataLen; | ||
2454 | fw.data_index = 0; | ||
2455 | fw.data = bnx2_TPAT_b06FwData; | ||
2456 | |||
2457 | fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr; | ||
2458 | fw.sbss_len = bnx2_TPAT_b06FwSbssLen; | ||
2459 | fw.sbss_index = 0; | ||
2460 | fw.sbss = bnx2_TPAT_b06FwSbss; | ||
2461 | |||
2462 | fw.bss_addr = bnx2_TPAT_b06FwBssAddr; | ||
2463 | fw.bss_len = bnx2_TPAT_b06FwBssLen; | ||
2464 | fw.bss_index = 0; | ||
2465 | fw.bss = bnx2_TPAT_b06FwBss; | ||
2466 | |||
2467 | fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr; | ||
2468 | fw.rodata_len = bnx2_TPAT_b06FwRodataLen; | ||
2469 | fw.rodata_index = 0; | ||
2470 | fw.rodata = bnx2_TPAT_b06FwRodata; | ||
2471 | |||
2472 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
2473 | |||
2474 | /* Initialize the Completion Processor. */ | 2392 | /* Initialize the Completion Processor. */ |
2475 | cpu_reg.mode = BNX2_COM_CPU_MODE; | 2393 | cpu_reg.mode = BNX2_COM_CPU_MODE; |
2476 | cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; | 2394 | cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; |
@@ -2485,44 +2403,12 @@ bnx2_init_cpus(struct bnx2 *bp) | |||
2485 | cpu_reg.spad_base = BNX2_COM_SCRATCH; | 2403 | cpu_reg.spad_base = BNX2_COM_SCRATCH; |
2486 | cpu_reg.mips_view_base = 0x8000000; | 2404 | cpu_reg.mips_view_base = 0x8000000; |
2487 | 2405 | ||
2488 | fw.ver_major = bnx2_COM_b06FwReleaseMajor; | 2406 | fw = &bnx2_com_fw_06; |
2489 | fw.ver_minor = bnx2_COM_b06FwReleaseMinor; | ||
2490 | fw.ver_fix = bnx2_COM_b06FwReleaseFix; | ||
2491 | fw.start_addr = bnx2_COM_b06FwStartAddr; | ||
2492 | |||
2493 | fw.text_addr = bnx2_COM_b06FwTextAddr; | ||
2494 | fw.text_len = bnx2_COM_b06FwTextLen; | ||
2495 | fw.text_index = 0; | ||
2496 | 2407 | ||
2497 | rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText), | 2408 | rc = load_cpu_fw(bp, &cpu_reg, fw); |
2498 | &text, &text_len); | ||
2499 | if (rc) | 2409 | if (rc) |
2500 | goto init_cpu_err; | 2410 | goto init_cpu_err; |
2501 | 2411 | ||
2502 | fw.text = text; | ||
2503 | |||
2504 | fw.data_addr = bnx2_COM_b06FwDataAddr; | ||
2505 | fw.data_len = bnx2_COM_b06FwDataLen; | ||
2506 | fw.data_index = 0; | ||
2507 | fw.data = bnx2_COM_b06FwData; | ||
2508 | |||
2509 | fw.sbss_addr = bnx2_COM_b06FwSbssAddr; | ||
2510 | fw.sbss_len = bnx2_COM_b06FwSbssLen; | ||
2511 | fw.sbss_index = 0; | ||
2512 | fw.sbss = bnx2_COM_b06FwSbss; | ||
2513 | |||
2514 | fw.bss_addr = bnx2_COM_b06FwBssAddr; | ||
2515 | fw.bss_len = bnx2_COM_b06FwBssLen; | ||
2516 | fw.bss_index = 0; | ||
2517 | fw.bss = bnx2_COM_b06FwBss; | ||
2518 | |||
2519 | fw.rodata_addr = bnx2_COM_b06FwRodataAddr; | ||
2520 | fw.rodata_len = bnx2_COM_b06FwRodataLen; | ||
2521 | fw.rodata_index = 0; | ||
2522 | fw.rodata = bnx2_COM_b06FwRodata; | ||
2523 | |||
2524 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
2525 | |||
2526 | init_cpu_err: | 2412 | init_cpu_err: |
2527 | bnx2_gunzip_end(bp); | 2413 | bnx2_gunzip_end(bp); |
2528 | return rc; | 2414 | return rc; |