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authorBenjamin Li <benli@broadcom.com>2010-01-08 03:51:21 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-08 03:51:21 -0500
commite2eb8e38592f28d8be4a518f44d3385272dedddb (patch)
treecdcf465e988219f50d5aff779e0b2d61c462cf5b /drivers/net/bnx2.c
parent368c0ca2f0a69b0818fbc1796d8e21ff02a61b4c (diff)
bnx2: Flush the register writes which setup the MSI-X table
The MSI-X table size needs to be properly set before pci_enable_msix() is called. But on certain machines, the writes are delayed and the MSI-X table size is incorrectly read. By reading the BNX2_PCI_MSIX_CONTROL register, the writes are flushed and now ensure that the MSI-X table is set correctly before MSI-X is enable on the device. This patch was originally diagnosed and authored by Kalyan Ram Chintalapati <kalyanc@vmware.com>. Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Kalyan Ram Chintalapati <kalyanc@vmware.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 65df1de447e4..b1c20e5f7de8 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -6145,6 +6145,10 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6145 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); 6145 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6146 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); 6146 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6147 6147
6148 /* Need to flush the previous three writes to ensure MSI-X
6149 * is setup properly */
6150 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6151
6148 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 6152 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6149 msix_ent[i].entry = i; 6153 msix_ent[i].entry = i;
6150 msix_ent[i].vector = 0; 6154 msix_ent[i].vector = 0;