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authorMichael Chan <mchan@broadcom.com>2007-07-08 01:51:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-07-11 01:18:36 -0400
commitdf149d70e1f34ec4995c8a703dbde38071ff4a05 (patch)
tree09103d4b997158202370619f5a1492a69f85e7af /drivers/net/bnx2.c
parentb8a7ce7bedb2134acb731e08e588ad92087a40ff (diff)
[BNX2]: Enhance the heartbeat.
In addition to the periodic heartbeat, we're adding a heartbeat request interrupt when the heartbeat is late. This is needed during netpoll where the timer is not available. -rt kernels will also benefit since the timer is not as accurate. [ We discussed this patch last time and we decided that the -rt kernel problem alone did not justify this patch. I think the netpoll problem makes this patch necessary. ] Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c26
1 files changed, 22 insertions, 4 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index a806a8edec87..e7551040b096 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -1487,6 +1487,20 @@ bnx2_set_default_link(struct bnx2 *bp)
1487} 1487}
1488 1488
1489static void 1489static void
1490bnx2_send_heart_beat(struct bnx2 *bp)
1491{
1492 u32 msg;
1493 u32 addr;
1494
1495 spin_lock(&bp->indirect_lock);
1496 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1497 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1498 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1499 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1500 spin_unlock(&bp->indirect_lock);
1501}
1502
1503static void
1490bnx2_remote_phy_event(struct bnx2 *bp) 1504bnx2_remote_phy_event(struct bnx2 *bp)
1491{ 1505{
1492 u32 msg; 1506 u32 msg;
@@ -1495,6 +1509,11 @@ bnx2_remote_phy_event(struct bnx2 *bp)
1495 1509
1496 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); 1510 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1497 1511
1512 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1513 bnx2_send_heart_beat(bp);
1514
1515 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1516
1498 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) 1517 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1499 bp->link_up = 0; 1518 bp->link_up = 0;
1500 else { 1519 else {
@@ -1572,6 +1591,7 @@ bnx2_set_remote_link(struct bnx2 *bp)
1572 break; 1591 break;
1573 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: 1592 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1574 default: 1593 default:
1594 bnx2_send_heart_beat(bp);
1575 break; 1595 break;
1576 } 1596 }
1577 return 0; 1597 return 0;
@@ -4122,7 +4142,7 @@ bnx2_init_chip(struct bnx2 *bp)
4122 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 4142 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4123 0); 4143 0);
4124 4144
4125 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff); 4145 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4126 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 4146 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4127 4147
4128 udelay(20); 4148 udelay(20);
@@ -4930,7 +4950,6 @@ static void
4930bnx2_timer(unsigned long data) 4950bnx2_timer(unsigned long data)
4931{ 4951{
4932 struct bnx2 *bp = (struct bnx2 *) data; 4952 struct bnx2 *bp = (struct bnx2 *) data;
4933 u32 msg;
4934 4953
4935 if (!netif_running(bp->dev)) 4954 if (!netif_running(bp->dev))
4936 return; 4955 return;
@@ -4938,8 +4957,7 @@ bnx2_timer(unsigned long data)
4938 if (atomic_read(&bp->intr_sem) != 0) 4957 if (atomic_read(&bp->intr_sem) != 0)
4939 goto bnx2_restart_timer; 4958 goto bnx2_restart_timer;
4940 4959
4941 msg = (u32) ++bp->fw_drv_pulse_wr_seq; 4960 bnx2_send_heart_beat(bp);
4942 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4943 4961
4944 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); 4962 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4945 4963