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authorMichael Chan <mchan@broadcom.com>2009-04-04 19:51:14 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-04 19:51:14 -0400
commit57579f7629a3d46c307405fbd2ea6bdb650d692f (patch)
treec407da542bfa50989bfc4f41daf7c1a181207d93 /drivers/net/bnx2.c
parent5d4d9e8ad6c646c4811bf0049df761dee6affc3d (diff)
bnx2: Use request_firmware()
Based on original patch by Ben Hutchings <ben@decadent.org.uk> and Bastian Blank <waldi@debian.org>, with the following main changes: Separated the mips firmware and rv2p firmware into different files to make it easier to update them separately. Added some code to fixup the rv2p code with run-time information such as PAGE_SIZE. Update version to 2.0.0. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c351
1 files changed, 210 insertions, 141 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index ad446db8e186..17cbc8c6be37 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -46,19 +46,20 @@
46#include <linux/crc32.h> 46#include <linux/crc32.h>
47#include <linux/prefetch.h> 47#include <linux/prefetch.h>
48#include <linux/cache.h> 48#include <linux/cache.h>
49#include <linux/zlib.h> 49#include <linux/firmware.h>
50#include <linux/log2.h> 50#include <linux/log2.h>
51 51
52#include "bnx2.h" 52#include "bnx2.h"
53#include "bnx2_fw.h" 53#include "bnx2_fw.h"
54#include "bnx2_fw2.h"
55
56#define FW_BUF_SIZE 0x10000
57 54
58#define DRV_MODULE_NAME "bnx2" 55#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": " 56#define PFX DRV_MODULE_NAME ": "
60#define DRV_MODULE_VERSION "1.9.3" 57#define DRV_MODULE_VERSION "2.0.0"
61#define DRV_MODULE_RELDATE "March 17, 2009" 58#define DRV_MODULE_RELDATE "April 2, 2009"
59#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-4.6.16.fw"
60#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-4.6.16.fw"
61#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-4.6.17.fw"
62#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-4.6.15.fw"
62 63
63#define RUN_AT(x) (jiffies + (x)) 64#define RUN_AT(x) (jiffies + (x))
64 65
@@ -72,6 +73,10 @@ MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
72MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); 73MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
73MODULE_LICENSE("GPL"); 74MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_MODULE_VERSION); 75MODULE_VERSION(DRV_MODULE_VERSION);
76MODULE_FIRMWARE(FW_MIPS_FILE_06);
77MODULE_FIRMWARE(FW_RV2P_FILE_06);
78MODULE_FIRMWARE(FW_MIPS_FILE_09);
79MODULE_FIRMWARE(FW_RV2P_FILE_09);
75 80
76static int disable_msi = 0; 81static int disable_msi = 0;
77 82
@@ -3391,33 +3396,143 @@ bnx2_set_rx_mode(struct net_device *dev)
3391 spin_unlock_bh(&bp->phy_lock); 3396 spin_unlock_bh(&bp->phy_lock);
3392} 3397}
3393 3398
3394static void 3399static int __devinit
3395load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len, 3400check_fw_section(const struct firmware *fw,
3396 u32 rv2p_proc) 3401 const struct bnx2_fw_file_section *section,
3402 u32 alignment, bool non_empty)
3403{
3404 u32 offset = be32_to_cpu(section->offset);
3405 u32 len = be32_to_cpu(section->len);
3406
3407 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3408 return -EINVAL;
3409 if ((non_empty && len == 0) || len > fw->size - offset ||
3410 len & (alignment - 1))
3411 return -EINVAL;
3412 return 0;
3413}
3414
3415static int __devinit
3416check_mips_fw_entry(const struct firmware *fw,
3417 const struct bnx2_mips_fw_file_entry *entry)
3418{
3419 if (check_fw_section(fw, &entry->text, 4, true) ||
3420 check_fw_section(fw, &entry->data, 4, false) ||
3421 check_fw_section(fw, &entry->rodata, 4, false))
3422 return -EINVAL;
3423 return 0;
3424}
3425
3426static int __devinit
3427bnx2_request_firmware(struct bnx2 *bp)
3397{ 3428{
3429 const char *mips_fw_file, *rv2p_fw_file;
3430 const struct bnx2_mips_fw_file *mips;
3431 const struct bnx2_rv2p_fw_file *rv2p;
3432 int rc;
3433
3434 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3435 mips_fw_file = FW_MIPS_FILE_09;
3436 rv2p_fw_file = FW_RV2P_FILE_09;
3437 } else {
3438 mips_fw_file = FW_MIPS_FILE_06;
3439 rv2p_fw_file = FW_RV2P_FILE_06;
3440 }
3441
3442 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3443 if (rc) {
3444 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3445 mips_fw_file);
3446 return rc;
3447 }
3448
3449 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3450 if (rc) {
3451 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3452 rv2p_fw_file);
3453 return rc;
3454 }
3455 mips = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3456 rv2p = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3457 if (bp->mips_firmware->size < sizeof(*mips) ||
3458 check_mips_fw_entry(bp->mips_firmware, &mips->com) ||
3459 check_mips_fw_entry(bp->mips_firmware, &mips->cp) ||
3460 check_mips_fw_entry(bp->mips_firmware, &mips->rxp) ||
3461 check_mips_fw_entry(bp->mips_firmware, &mips->tpat) ||
3462 check_mips_fw_entry(bp->mips_firmware, &mips->txp)) {
3463 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3464 mips_fw_file);
3465 return -EINVAL;
3466 }
3467 if (bp->rv2p_firmware->size < sizeof(*rv2p) ||
3468 check_fw_section(bp->rv2p_firmware, &rv2p->proc1.rv2p, 8, true) ||
3469 check_fw_section(bp->rv2p_firmware, &rv2p->proc2.rv2p, 8, true)) {
3470 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3471 rv2p_fw_file);
3472 return -EINVAL;
3473 }
3474
3475 return 0;
3476}
3477
3478static u32
3479rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3480{
3481 switch (idx) {
3482 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3483 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3484 rv2p_code |= RV2P_BD_PAGE_SIZE;
3485 break;
3486 }
3487 return rv2p_code;
3488}
3489
3490static int
3491load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3492 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3493{
3494 u32 rv2p_code_len, file_offset;
3495 __be32 *rv2p_code;
3398 int i; 3496 int i;
3399 u32 val; 3497 u32 val, cmd, addr;
3498
3499 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3500 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3501
3502 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3400 3503
3401 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) { 3504 if (rv2p_proc == RV2P_PROC1) {
3402 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]); 3505 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3403 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK; 3506 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3404 val |= XI_RV2P_PROC2_BD_PAGE_SIZE; 3507 } else {
3405 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val); 3508 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3509 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3406 } 3510 }
3407 3511
3408 for (i = 0; i < rv2p_code_len; i += 8) { 3512 for (i = 0; i < rv2p_code_len; i += 8) {
3409 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code)); 3513 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3410 rv2p_code++; 3514 rv2p_code++;
3411 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code)); 3515 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3412 rv2p_code++; 3516 rv2p_code++;
3413 3517
3414 if (rv2p_proc == RV2P_PROC1) { 3518 val = (i / 8) | cmd;
3415 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR; 3519 REG_WR(bp, addr, val);
3416 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val); 3520 }
3417 } 3521
3418 else { 3522 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3419 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR; 3523 for (i = 0; i < 8; i++) {
3420 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val); 3524 u32 loc, code;
3525
3526 loc = be32_to_cpu(fw_entry->fixup[i]);
3527 if (loc && ((loc * 4) < rv2p_code_len)) {
3528 code = be32_to_cpu(*(rv2p_code + loc - 1));
3529 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3530 code = be32_to_cpu(*(rv2p_code + loc));
3531 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3532 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3533
3534 val = (loc / 2) | cmd;
3535 REG_WR(bp, addr, val);
3421 } 3536 }
3422 } 3537 }
3423 3538
@@ -3428,14 +3543,18 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3428 else { 3543 else {
3429 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); 3544 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3430 } 3545 }
3546
3547 return 0;
3431} 3548}
3432 3549
3433static int 3550static int
3434load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw) 3551load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3552 const struct bnx2_mips_fw_file_entry *fw_entry)
3435{ 3553{
3554 u32 addr, len, file_offset;
3555 __be32 *data;
3436 u32 offset; 3556 u32 offset;
3437 u32 val; 3557 u32 val;
3438 int rc;
3439 3558
3440 /* Halt the CPU. */ 3559 /* Halt the CPU. */
3441 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3560 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
@@ -3444,64 +3563,52 @@ load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3444 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3563 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3445 3564
3446 /* Load the Text area. */ 3565 /* Load the Text area. */
3447 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3566 addr = be32_to_cpu(fw_entry->text.addr);
3448 if (fw->gz_text) { 3567 len = be32_to_cpu(fw_entry->text.len);
3449 int j; 3568 file_offset = be32_to_cpu(fw_entry->text.offset);
3450 3569 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3451 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3452 fw->gz_text_len);
3453 if (rc < 0)
3454 return rc;
3455 3570
3456 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3571 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3457 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j])); 3572 if (len) {
3458 }
3459 }
3460
3461 /* Load the Data area. */
3462 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3463 if (fw->data) {
3464 int j; 3573 int j;
3465 3574
3466 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3575 for (j = 0; j < (len / 4); j++, offset += 4)
3467 bnx2_reg_wr_ind(bp, offset, fw->data[j]); 3576 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3468 }
3469 } 3577 }
3470 3578
3471 /* Load the SBSS area. */ 3579 /* Load the Data area. */
3472 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3580 addr = be32_to_cpu(fw_entry->data.addr);
3473 if (fw->sbss_len) { 3581 len = be32_to_cpu(fw_entry->data.len);
3474 int j; 3582 file_offset = be32_to_cpu(fw_entry->data.offset);
3475 3583 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3476 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3477 bnx2_reg_wr_ind(bp, offset, 0);
3478 }
3479 }
3480 3584
3481 /* Load the BSS area. */ 3585 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3482 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3586 if (len) {
3483 if (fw->bss_len) {
3484 int j; 3587 int j;
3485 3588
3486 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3589 for (j = 0; j < (len / 4); j++, offset += 4)
3487 bnx2_reg_wr_ind(bp, offset, 0); 3590 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3488 }
3489 } 3591 }
3490 3592
3491 /* Load the Read-Only area. */ 3593 /* Load the Read-Only area. */
3492 offset = cpu_reg->spad_base + 3594 addr = be32_to_cpu(fw_entry->rodata.addr);
3493 (fw->rodata_addr - cpu_reg->mips_view_base); 3595 len = be32_to_cpu(fw_entry->rodata.len);
3494 if (fw->rodata) { 3596 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3597 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3598
3599 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3600 if (len) {
3495 int j; 3601 int j;
3496 3602
3497 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3603 for (j = 0; j < (len / 4); j++, offset += 4)
3498 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]); 3604 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3499 }
3500 } 3605 }
3501 3606
3502 /* Clear the pre-fetch instruction. */ 3607 /* Clear the pre-fetch instruction. */
3503 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); 3608 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3504 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr); 3609
3610 val = be32_to_cpu(fw_entry->start_addr);
3611 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3505 3612
3506 /* Start the CPU. */ 3613 /* Start the CPU. */
3507 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3614 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
@@ -3515,95 +3622,40 @@ load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3515static int 3622static int
3516bnx2_init_cpus(struct bnx2 *bp) 3623bnx2_init_cpus(struct bnx2 *bp)
3517{ 3624{
3518 struct fw_info *fw; 3625 const struct bnx2_mips_fw_file *mips_fw =
3519 int rc, rv2p_len; 3626 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3520 void *text, *rv2p; 3627 const struct bnx2_rv2p_fw_file *rv2p_fw =
3628 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3629 int rc;
3521 3630
3522 /* Initialize the RV2P processor. */ 3631 /* Initialize the RV2P processor. */
3523 text = vmalloc(FW_BUF_SIZE); 3632 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3524 if (!text) 3633 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3525 return -ENOMEM;
3526 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3527 rv2p = bnx2_xi_rv2p_proc1;
3528 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3529 } else {
3530 rv2p = bnx2_rv2p_proc1;
3531 rv2p_len = sizeof(bnx2_rv2p_proc1);
3532 }
3533 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3534 if (rc < 0)
3535 goto init_cpu_err;
3536
3537 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3538
3539 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3540 rv2p = bnx2_xi_rv2p_proc2;
3541 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3542 } else {
3543 rv2p = bnx2_rv2p_proc2;
3544 rv2p_len = sizeof(bnx2_rv2p_proc2);
3545 }
3546 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3547 if (rc < 0)
3548 goto init_cpu_err;
3549
3550 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3551 3634
3552 /* Initialize the RX Processor. */ 3635 /* Initialize the RX Processor. */
3553 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3636 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3554 fw = &bnx2_rxp_fw_09;
3555 else
3556 fw = &bnx2_rxp_fw_06;
3557
3558 fw->text = text;
3559 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3560 if (rc) 3637 if (rc)
3561 goto init_cpu_err; 3638 goto init_cpu_err;
3562 3639
3563 /* Initialize the TX Processor. */ 3640 /* Initialize the TX Processor. */
3564 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3641 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3565 fw = &bnx2_txp_fw_09;
3566 else
3567 fw = &bnx2_txp_fw_06;
3568
3569 fw->text = text;
3570 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3571 if (rc) 3642 if (rc)
3572 goto init_cpu_err; 3643 goto init_cpu_err;
3573 3644
3574 /* Initialize the TX Patch-up Processor. */ 3645 /* Initialize the TX Patch-up Processor. */
3575 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3646 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3576 fw = &bnx2_tpat_fw_09;
3577 else
3578 fw = &bnx2_tpat_fw_06;
3579
3580 fw->text = text;
3581 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3582 if (rc) 3647 if (rc)
3583 goto init_cpu_err; 3648 goto init_cpu_err;
3584 3649
3585 /* Initialize the Completion Processor. */ 3650 /* Initialize the Completion Processor. */
3586 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3651 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3587 fw = &bnx2_com_fw_09;
3588 else
3589 fw = &bnx2_com_fw_06;
3590
3591 fw->text = text;
3592 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3593 if (rc) 3652 if (rc)
3594 goto init_cpu_err; 3653 goto init_cpu_err;
3595 3654
3596 /* Initialize the Command Processor. */ 3655 /* Initialize the Command Processor. */
3597 if (CHIP_NUM(bp) == CHIP_NUM_5709) 3656 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3598 fw = &bnx2_cp_fw_09;
3599 else
3600 fw = &bnx2_cp_fw_06;
3601
3602 fw->text = text;
3603 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3604 3657
3605init_cpu_err: 3658init_cpu_err:
3606 vfree(text);
3607 return rc; 3659 return rc;
3608} 3660}
3609 3661
@@ -7807,6 +7859,10 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7807 7859
7808 pci_set_drvdata(pdev, dev); 7860 pci_set_drvdata(pdev, dev);
7809 7861
7862 rc = bnx2_request_firmware(bp);
7863 if (rc)
7864 goto error;
7865
7810 memcpy(dev->dev_addr, bp->mac_addr, 6); 7866 memcpy(dev->dev_addr, bp->mac_addr, 6);
7811 memcpy(dev->perm_addr, bp->mac_addr, 6); 7867 memcpy(dev->perm_addr, bp->mac_addr, 6);
7812 7868
@@ -7823,13 +7879,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7823 7879
7824 if ((rc = register_netdev(dev))) { 7880 if ((rc = register_netdev(dev))) {
7825 dev_err(&pdev->dev, "Cannot register net device\n"); 7881 dev_err(&pdev->dev, "Cannot register net device\n");
7826 if (bp->regview) 7882 goto error;
7827 iounmap(bp->regview);
7828 pci_release_regions(pdev);
7829 pci_disable_device(pdev);
7830 pci_set_drvdata(pdev, NULL);
7831 free_netdev(dev);
7832 return rc;
7833 } 7883 }
7834 7884
7835 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " 7885 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
@@ -7843,6 +7893,20 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7843 bp->pdev->irq, dev->dev_addr); 7893 bp->pdev->irq, dev->dev_addr);
7844 7894
7845 return 0; 7895 return 0;
7896
7897error:
7898 if (bp->mips_firmware)
7899 release_firmware(bp->mips_firmware);
7900 if (bp->rv2p_firmware)
7901 release_firmware(bp->rv2p_firmware);
7902
7903 if (bp->regview)
7904 iounmap(bp->regview);
7905 pci_release_regions(pdev);
7906 pci_disable_device(pdev);
7907 pci_set_drvdata(pdev, NULL);
7908 free_netdev(dev);
7909 return rc;
7846} 7910}
7847 7911
7848static void __devexit 7912static void __devexit
@@ -7855,6 +7919,11 @@ bnx2_remove_one(struct pci_dev *pdev)
7855 7919
7856 unregister_netdev(dev); 7920 unregister_netdev(dev);
7857 7921
7922 if (bp->mips_firmware)
7923 release_firmware(bp->mips_firmware);
7924 if (bp->rv2p_firmware)
7925 release_firmware(bp->rv2p_firmware);
7926
7858 if (bp->regview) 7927 if (bp->regview)
7859 iounmap(bp->regview); 7928 iounmap(bp->regview);
7860 7929