bnx2: Set rx buffer water marks based on MTU.

The default rx buffer water marks for XOFF/XON are for 1500 MTU.  At
larger MTUs, these water marks need to be adjusted for effective
flow control.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 10 insertions, 2 deletions

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index d28cbce0ec48..a52ffdc3b40a 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -4473,7 +4473,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
 static int
 bnx2_init_chip(struct bnx2 *bp)
 {
-        u32 val;
+        u32 val, mtu;
         int rc, i;
 
         /* Make sure the interrupt is not active. */
@@ -4565,11 +4565,19 @@ bnx2_init_chip(struct bnx2 *bp)
         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
 
         /* Program the MTU.  Also include 4 bytes for CRC32. */
-        val = bp->dev->mtu + ETH_HLEN + 4;
+        mtu = bp->dev->mtu;
+        val = mtu + ETH_HLEN + ETH_FCS_LEN;
         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
 
+        if (mtu < 1500)
+                mtu = 1500;
+
+        bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
+        bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
+        bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
+
         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
                 bp->bnx2_napi[i].last_status_idx = 0;