diff options
author | Michael Chan <mchan@broadcom.com> | 2007-06-05 00:17:10 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-06-07 16:38:36 -0400 |
commit | 7947b20ebae785ba25154aa1a9a00a98a22de75a (patch) | |
tree | 6e9076d1d28c3ba12f5483a56129d6bd812fe240 /drivers/net/bnx2.c | |
parent | 7244d545c123ff33a3a5bff7fcb96a07778c32d1 (diff) |
[BNX2]: Fix netdev watchdog on 5708.
There's a bug in the driver that only initializes half of the context
memory on the 5708. Surprisingly, this works most of the time except
for some occasional netdev watchdogs when sending a lot of 64-byte
packets. The fix is to add the missing code to initialize the 2nd
halves of all context memory.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index da7c3b0c533c..9789f05cbc99 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -1811,6 +1811,7 @@ bnx2_init_context(struct bnx2 *bp) | |||
1811 | vcid = 96; | 1811 | vcid = 96; |
1812 | while (vcid) { | 1812 | while (vcid) { |
1813 | u32 vcid_addr, pcid_addr, offset; | 1813 | u32 vcid_addr, pcid_addr, offset; |
1814 | int i; | ||
1814 | 1815 | ||
1815 | vcid--; | 1816 | vcid--; |
1816 | 1817 | ||
@@ -1831,16 +1832,20 @@ bnx2_init_context(struct bnx2 *bp) | |||
1831 | pcid_addr = vcid_addr; | 1832 | pcid_addr = vcid_addr; |
1832 | } | 1833 | } |
1833 | 1834 | ||
1834 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); | 1835 | for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { |
1835 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | 1836 | vcid_addr += (i << PHY_CTX_SHIFT); |
1837 | pcid_addr += (i << PHY_CTX_SHIFT); | ||
1836 | 1838 | ||
1837 | /* Zero out the context. */ | 1839 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); |
1838 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { | 1840 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); |
1839 | CTX_WR(bp, 0x00, offset, 0); | ||
1840 | } | ||
1841 | 1841 | ||
1842 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); | 1842 | /* Zero out the context. */ |
1843 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | 1843 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) |
1844 | CTX_WR(bp, 0x00, offset, 0); | ||
1845 | |||
1846 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); | ||
1847 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | ||
1848 | } | ||
1844 | } | 1849 | } |
1845 | } | 1850 | } |
1846 | 1851 | ||