diff options
author | Michael Chan <mchan@broadcom.com> | 2008-01-30 00:35:40 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-31 22:27:15 -0500 |
commit | 62a8313cddbea04f2a28d1d76acf317c2a56cfae (patch) | |
tree | fc4f14124044b98b417df64b607386e24e0789c4 /drivers/net/bnx2.c | |
parent | 2726d6e126c0c16efeba30356d4ae105f1854d1e (diff) |
[BNX2]: Remove CTX_WR macro.
The CTX_WR macro is unnecessary and obfuscates the code.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r-- | drivers/net/bnx2.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 8e9fe486934e..8af63b4ec67d 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -2237,7 +2237,7 @@ bnx2_init_context(struct bnx2 *bp) | |||
2237 | 2237 | ||
2238 | /* Zero out the context. */ | 2238 | /* Zero out the context. */ |
2239 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) | 2239 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) |
2240 | CTX_WR(bp, vcid_addr, offset, 0); | 2240 | bnx2_ctx_wr(bp, vcid_addr, offset, 0); |
2241 | } | 2241 | } |
2242 | } | 2242 | } |
2243 | } | 2243 | } |
@@ -4523,6 +4523,7 @@ static void | |||
4523 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid) | 4523 | bnx2_init_tx_context(struct bnx2 *bp, u32 cid) |
4524 | { | 4524 | { |
4525 | u32 val, offset0, offset1, offset2, offset3; | 4525 | u32 val, offset0, offset1, offset2, offset3; |
4526 | u32 cid_addr = GET_CID_ADDR(cid); | ||
4526 | 4527 | ||
4527 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | 4528 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
4528 | offset0 = BNX2_L2CTX_TYPE_XI; | 4529 | offset0 = BNX2_L2CTX_TYPE_XI; |
@@ -4536,16 +4537,16 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid) | |||
4536 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; | 4537 | offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; |
4537 | } | 4538 | } |
4538 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; | 4539 | val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; |
4539 | CTX_WR(bp, GET_CID_ADDR(cid), offset0, val); | 4540 | bnx2_ctx_wr(bp, cid_addr, offset0, val); |
4540 | 4541 | ||
4541 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); | 4542 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); |
4542 | CTX_WR(bp, GET_CID_ADDR(cid), offset1, val); | 4543 | bnx2_ctx_wr(bp, cid_addr, offset1, val); |
4543 | 4544 | ||
4544 | val = (u64) bp->tx_desc_mapping >> 32; | 4545 | val = (u64) bp->tx_desc_mapping >> 32; |
4545 | CTX_WR(bp, GET_CID_ADDR(cid), offset2, val); | 4546 | bnx2_ctx_wr(bp, cid_addr, offset2, val); |
4546 | 4547 | ||
4547 | val = (u64) bp->tx_desc_mapping & 0xffffffff; | 4548 | val = (u64) bp->tx_desc_mapping & 0xffffffff; |
4548 | CTX_WR(bp, GET_CID_ADDR(cid), offset3, val); | 4549 | bnx2_ctx_wr(bp, cid_addr, offset3, val); |
4549 | } | 4550 | } |
4550 | 4551 | ||
4551 | static void | 4552 | static void |
@@ -4615,21 +4616,21 @@ bnx2_init_rx_ring(struct bnx2 *bp) | |||
4615 | bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, | 4616 | bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping, |
4616 | bp->rx_buf_use_size, bp->rx_max_ring); | 4617 | bp->rx_buf_use_size, bp->rx_max_ring); |
4617 | 4618 | ||
4618 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); | 4619 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); |
4619 | if (bp->rx_pg_ring_size) { | 4620 | if (bp->rx_pg_ring_size) { |
4620 | bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, | 4621 | bnx2_init_rxbd_rings(bp->rx_pg_desc_ring, |
4621 | bp->rx_pg_desc_mapping, | 4622 | bp->rx_pg_desc_mapping, |
4622 | PAGE_SIZE, bp->rx_max_pg_ring); | 4623 | PAGE_SIZE, bp->rx_max_pg_ring); |
4623 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; | 4624 | val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; |
4624 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); | 4625 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); |
4625 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, | 4626 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, |
4626 | BNX2_L2CTX_RBDC_JUMBO_KEY); | 4627 | BNX2_L2CTX_RBDC_JUMBO_KEY); |
4627 | 4628 | ||
4628 | val = (u64) bp->rx_pg_desc_mapping[0] >> 32; | 4629 | val = (u64) bp->rx_pg_desc_mapping[0] >> 32; |
4629 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); | 4630 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); |
4630 | 4631 | ||
4631 | val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; | 4632 | val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff; |
4632 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); | 4633 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); |
4633 | 4634 | ||
4634 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | 4635 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
4635 | REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); | 4636 | REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); |
@@ -4638,13 +4639,13 @@ bnx2_init_rx_ring(struct bnx2 *bp) | |||
4638 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | 4639 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; |
4639 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | 4640 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; |
4640 | val |= 0x02 << 8; | 4641 | val |= 0x02 << 8; |
4641 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); | 4642 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); |
4642 | 4643 | ||
4643 | val = (u64) bp->rx_desc_mapping[0] >> 32; | 4644 | val = (u64) bp->rx_desc_mapping[0] >> 32; |
4644 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); | 4645 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); |
4645 | 4646 | ||
4646 | val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; | 4647 | val = (u64) bp->rx_desc_mapping[0] & 0xffffffff; |
4647 | CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); | 4648 | bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); |
4648 | 4649 | ||
4649 | ring_prod = prod = bnapi->rx_pg_prod; | 4650 | ring_prod = prod = bnapi->rx_pg_prod; |
4650 | for (i = 0; i < bp->rx_pg_ring_size; i++) { | 4651 | for (i = 0; i < bp->rx_pg_ring_size; i++) { |