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authorMichael Chan <mchan@broadcom.com>2007-03-30 17:53:06 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-04-02 16:30:55 -0400
commitc873879c4db31bab414655e191cf56019b48c751 (patch)
tree66823c4e4b9cd88fc4c4d7df91746a043894840f /drivers/net/bnx2.c
parentb59e139bbd5c789700aa9cefe7eb6590bc516b86 (diff)
[BNX2]: Fix nvram write logic.
The nvram dword alignment logic was broken when writing less than 4 bytes on a non-aligned offset. It was missing logic to round the length to 4 bytes. The page erase code is also moved so that it is only called when using non-buffered flash for better code clarity. Update version to 1.5.7. Based on initial patch from Tony Cureington <tony.cureington@hp.com>. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.c')
-rw-r--r--drivers/net/bnx2.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index d43fe2863095..0b7aded8dcfd 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -54,8 +54,8 @@
54 54
55#define DRV_MODULE_NAME "bnx2" 55#define DRV_MODULE_NAME "bnx2"
56#define PFX DRV_MODULE_NAME ": " 56#define PFX DRV_MODULE_NAME ": "
57#define DRV_MODULE_VERSION "1.5.6" 57#define DRV_MODULE_VERSION "1.5.7"
58#define DRV_MODULE_RELDATE "March 28, 2007" 58#define DRV_MODULE_RELDATE "March 29, 2007"
59 59
60#define RUN_AT(x) (jiffies + (x)) 60#define RUN_AT(x) (jiffies + (x))
61 61
@@ -3099,20 +3099,18 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3099 3099
3100 if ((align_start = (offset32 & 3))) { 3100 if ((align_start = (offset32 & 3))) {
3101 offset32 &= ~3; 3101 offset32 &= ~3;
3102 len32 += (4 - align_start); 3102 len32 += align_start;
3103 if (len32 < 4)
3104 len32 = 4;
3103 if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) 3105 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3104 return rc; 3106 return rc;
3105 } 3107 }
3106 3108
3107 if (len32 & 3) { 3109 if (len32 & 3) {
3108 if ((len32 > 4) || !align_start) { 3110 align_end = 4 - (len32 & 3);
3109 align_end = 4 - (len32 & 3); 3111 len32 += align_end;
3110 len32 += align_end; 3112 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3111 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, 3113 return rc;
3112 end, 4))) {
3113 return rc;
3114 }
3115 }
3116 } 3114 }
3117 3115
3118 if (align_start || align_end) { 3116 if (align_start || align_end) {
@@ -3187,17 +3185,17 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3187 if ((rc = bnx2_enable_nvram_write(bp)) != 0) 3185 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3188 goto nvram_write_end; 3186 goto nvram_write_end;
3189 3187
3190 /* Erase the page */
3191 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3192 goto nvram_write_end;
3193
3194 /* Re-enable the write again for the actual write */
3195 bnx2_enable_nvram_write(bp);
3196
3197 /* Loop to write back the buffer data from page_start to 3188 /* Loop to write back the buffer data from page_start to
3198 * data_start */ 3189 * data_start */
3199 i = 0; 3190 i = 0;
3200 if (bp->flash_info->buffered == 0) { 3191 if (bp->flash_info->buffered == 0) {
3192 /* Erase the page */
3193 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3194 goto nvram_write_end;
3195
3196 /* Re-enable the write again for the actual write */
3197 bnx2_enable_nvram_write(bp);
3198
3201 for (addr = page_start; addr < data_start; 3199 for (addr = page_start; addr < data_start;
3202 addr += 4, i += 4) { 3200 addr += 4, i += 4) {
3203 3201