diff options
| author | Ajit Khaparde <ajitk@serverengines.com> | 2010-07-29 02:16:33 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-07-31 02:59:05 -0400 |
| commit | 7c185276e8d820fa50a678c61abd611ee599920e (patch) | |
| tree | 5c8b5ac0e55eb2bafca470da939177ecc52a9755 /drivers/net/benet/be_hw.h | |
| parent | 6dedec818ac2a3783581a761b0680e713f78afde (diff) | |
be2net: add code to dump registers for debug
when the BE device becomes unresponsive, dump the registers to help debugging
Signed-off-by: Somnath K <somnathk@serverengines.com>
Signed-off-by: Ajit Khaparde <ajitk@serverengines.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/benet/be_hw.h')
| -rw-r--r-- | drivers/net/benet/be_hw.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h index 06839676e3c4..6c8f9bb8bfe6 100644 --- a/drivers/net/benet/be_hw.h +++ b/drivers/net/benet/be_hw.h | |||
| @@ -56,6 +56,16 @@ | |||
| 56 | #define PCICFG_PM_CONTROL_OFFSET 0x44 | 56 | #define PCICFG_PM_CONTROL_OFFSET 0x44 |
| 57 | #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ | 57 | #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ |
| 58 | 58 | ||
| 59 | /********* Online Control Registers *******/ | ||
| 60 | #define PCICFG_ONLINE0 0xB0 | ||
| 61 | #define PCICFG_ONLINE1 0xB4 | ||
| 62 | |||
| 63 | /********* UE Status and Mask Registers ***/ | ||
| 64 | #define PCICFG_UE_STATUS_LOW 0xA0 | ||
| 65 | #define PCICFG_UE_STATUS_HIGH 0xA4 | ||
| 66 | #define PCICFG_UE_STATUS_LOW_MASK 0xA8 | ||
| 67 | #define PCICFG_UE_STATUS_HI_MASK 0xAC | ||
| 68 | |||
| 59 | /********* ISR0 Register offset **********/ | 69 | /********* ISR0 Register offset **********/ |
| 60 | #define CEV_ISR0_OFFSET 0xC18 | 70 | #define CEV_ISR0_OFFSET 0xC18 |
| 61 | #define CEV_ISR_SIZE 4 | 71 | #define CEV_ISR_SIZE 4 |