be2net: memory barrier fixes on IBM p7 platform

The ibm p7 architecure seems to reorder memory accesses more
aggressively than previous ppc64 architectures. This requires memory
barriers to ensure that rx/tx doorbells are pressed only after
memory to be DMAed is written.

Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
index ee1ad9693c8f..65e3260d0f08 100644
--- a/drivers/net/benet/be_cmds.c
+++ b/drivers/net/benet/be_cmds.c
@@ -25,6 +25,8 @@ static void be_mcc_notify(struct be_adapter *adapter)
 
         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
+
+        wmb();
         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 }