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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-20 09:55:16 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-11 19:29:59 -0400
commit2b133ad6e9e96798007e64eb912c42fa00adef0a (patch)
tree34d1760a9257b150289893cda05b4adfa1990306 /drivers/net/atl1e
parent3401299a1b9e747cbf7de2cc0c8f6376c3cbe565 (diff)
atl*: Move the Atheros drivers
Move the Atheros drivers into drivers/net/ethernet/atheros/ and make the necessary Kconfig and Makefile changes. CC: Jay Cliburn <jcliburn@gmail.com> CC: Chris Snook <chris.snook@gmail.com> CC: Jie Yang <jie.yang@atheros.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/atl1e')
-rw-r--r--drivers/net/atl1e/Makefile2
-rw-r--r--drivers/net/atl1e/atl1e.h509
-rw-r--r--drivers/net/atl1e/atl1e_ethtool.c390
-rw-r--r--drivers/net/atl1e/atl1e_hw.c651
-rw-r--r--drivers/net/atl1e/atl1e_hw.h690
-rw-r--r--drivers/net/atl1e/atl1e_main.c2558
-rw-r--r--drivers/net/atl1e/atl1e_param.c268
7 files changed, 0 insertions, 5068 deletions
diff --git a/drivers/net/atl1e/Makefile b/drivers/net/atl1e/Makefile
deleted file mode 100644
index bc11be824e76..000000000000
--- a/drivers/net/atl1e/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ATL1E) += atl1e.o
2atl1e-objs += atl1e_main.o atl1e_hw.o atl1e_ethtool.o atl1e_param.o
diff --git a/drivers/net/atl1e/atl1e.h b/drivers/net/atl1e/atl1e.h
deleted file mode 100644
index 829b5ad71d0d..000000000000
--- a/drivers/net/atl1e/atl1e.h
+++ /dev/null
@@ -1,509 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#ifndef _ATL1E_H_
24#define _ATL1E_H_
25
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/types.h>
29#include <linux/errno.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/list.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/udp.h>
44#include <linux/mii.h>
45#include <linux/io.h>
46#include <linux/vmalloc.h>
47#include <linux/pagemap.h>
48#include <linux/tcp.h>
49#include <linux/ethtool.h>
50#include <linux/if_vlan.h>
51#include <linux/workqueue.h>
52#include <net/checksum.h>
53#include <net/ip6_checksum.h>
54
55#include "atl1e_hw.h"
56
57#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
58#define CMD_IO_SPACE 0x0001
59#define CMD_MEMORY_SPACE 0x0002
60#define CMD_BUS_MASTER 0x0004
61
62#define BAR_0 0
63#define BAR_1 1
64#define BAR_5 5
65
66/* Wake Up Filter Control */
67#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
68#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
69#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
70#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
71#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
72
73#define SPEED_0 0xffff
74#define HALF_DUPLEX 1
75#define FULL_DUPLEX 2
76
77/* Error Codes */
78#define AT_ERR_EEPROM 1
79#define AT_ERR_PHY 2
80#define AT_ERR_CONFIG 3
81#define AT_ERR_PARAM 4
82#define AT_ERR_MAC_TYPE 5
83#define AT_ERR_PHY_TYPE 6
84#define AT_ERR_PHY_SPEED 7
85#define AT_ERR_PHY_RES 8
86#define AT_ERR_TIMEOUT 9
87
88#define MAX_JUMBO_FRAME_SIZE 0x2000
89
90#define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) \
91 _tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
92 (((_vlan) >> 9) & 8))
93
94#define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) \
95 _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
96 (((_tdp) & 0x88) << 5))
97
98#define AT_MAX_RECEIVE_QUEUE 4
99#define AT_PAGE_NUM_PER_QUEUE 2
100
101#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
102#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
103
104#define AT_TX_WATCHDOG (5 * HZ)
105#define AT_MAX_INT_WORK 10
106#define AT_TWSI_EEPROM_TIMEOUT 100
107#define AT_HW_MAX_IDLE_DELAY 10
108#define AT_SUSPEND_LINK_TIMEOUT 28
109
110#define AT_REGS_LEN 75
111#define AT_EEPROM_LEN 512
112#define AT_ADV_MASK (ADVERTISE_10_HALF |\
113 ADVERTISE_10_FULL |\
114 ADVERTISE_100_HALF |\
115 ADVERTISE_100_FULL |\
116 ADVERTISE_1000_FULL)
117
118/* tpd word 2 */
119#define TPD_BUFLEN_MASK 0x3FFF
120#define TPD_BUFLEN_SHIFT 0
121#define TPD_DMAINT_MASK 0x0001
122#define TPD_DMAINT_SHIFT 14
123#define TPD_PKTNT_MASK 0x0001
124#define TPD_PKTINT_SHIFT 15
125#define TPD_VLANTAG_MASK 0xFFFF
126#define TPD_VLAN_SHIFT 16
127
128/* tpd word 3 bits 0:4 */
129#define TPD_EOP_MASK 0x0001
130#define TPD_EOP_SHIFT 0
131#define TPD_IP_VERSION_MASK 0x0001
132#define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */
133#define TPD_INS_VL_TAG_MASK 0x0001
134#define TPD_INS_VL_TAG_SHIFT 2
135#define TPD_CC_SEGMENT_EN_MASK 0x0001
136#define TPD_CC_SEGMENT_EN_SHIFT 3
137#define TPD_SEGMENT_EN_MASK 0x0001
138#define TPD_SEGMENT_EN_SHIFT 4
139
140/* tdp word 3 bits 5:7 if ip version is 0 */
141#define TPD_IP_CSUM_MASK 0x0001
142#define TPD_IP_CSUM_SHIFT 5
143#define TPD_TCP_CSUM_MASK 0x0001
144#define TPD_TCP_CSUM_SHIFT 6
145#define TPD_UDP_CSUM_MASK 0x0001
146#define TPD_UDP_CSUM_SHIFT 7
147
148/* tdp word 3 bits 5:7 if ip version is 1 */
149#define TPD_V6_IPHLLO_MASK 0x0007
150#define TPD_V6_IPHLLO_SHIFT 7
151
152/* tpd word 3 bits 8:9 bit */
153#define TPD_VL_TAGGED_MASK 0x0001
154#define TPD_VL_TAGGED_SHIFT 8
155#define TPD_ETHTYPE_MASK 0x0001
156#define TPD_ETHTYPE_SHIFT 9
157
158/* tdp word 3 bits 10:13 if ip version is 0 */
159#define TDP_V4_IPHL_MASK 0x000F
160#define TPD_V4_IPHL_SHIFT 10
161
162/* tdp word 3 bits 10:13 if ip version is 1 */
163#define TPD_V6_IPHLHI_MASK 0x000F
164#define TPD_V6_IPHLHI_SHIFT 10
165
166/* tpd word 3 bit 14:31 if segment enabled */
167#define TPD_TCPHDRLEN_MASK 0x000F
168#define TPD_TCPHDRLEN_SHIFT 14
169#define TPD_HDRFLAG_MASK 0x0001
170#define TPD_HDRFLAG_SHIFT 18
171#define TPD_MSS_MASK 0x1FFF
172#define TPD_MSS_SHIFT 19
173
174/* tdp word 3 bit 16:31 if custom csum enabled */
175#define TPD_PLOADOFFSET_MASK 0x00FF
176#define TPD_PLOADOFFSET_SHIFT 16
177#define TPD_CCSUMOFFSET_MASK 0x00FF
178#define TPD_CCSUMOFFSET_SHIFT 24
179
180struct atl1e_tpd_desc {
181 __le64 buffer_addr;
182 __le32 word2;
183 __le32 word3;
184};
185
186/* how about 0x2000 */
187#define MAX_TX_BUF_LEN 0x2000
188#define MAX_TX_BUF_SHIFT 13
189/*#define MAX_TX_BUF_LEN 0x3000 */
190
191/* rrs word 1 bit 0:31 */
192#define RRS_RX_CSUM_MASK 0xFFFF
193#define RRS_RX_CSUM_SHIFT 0
194#define RRS_PKT_SIZE_MASK 0x3FFF
195#define RRS_PKT_SIZE_SHIFT 16
196#define RRS_CPU_NUM_MASK 0x0003
197#define RRS_CPU_NUM_SHIFT 30
198
199#define RRS_IS_RSS_IPV4 0x0001
200#define RRS_IS_RSS_IPV4_TCP 0x0002
201#define RRS_IS_RSS_IPV6 0x0004
202#define RRS_IS_RSS_IPV6_TCP 0x0008
203#define RRS_IS_IPV6 0x0010
204#define RRS_IS_IP_FRAG 0x0020
205#define RRS_IS_IP_DF 0x0040
206#define RRS_IS_802_3 0x0080
207#define RRS_IS_VLAN_TAG 0x0100
208#define RRS_IS_ERR_FRAME 0x0200
209#define RRS_IS_IPV4 0x0400
210#define RRS_IS_UDP 0x0800
211#define RRS_IS_TCP 0x1000
212#define RRS_IS_BCAST 0x2000
213#define RRS_IS_MCAST 0x4000
214#define RRS_IS_PAUSE 0x8000
215
216#define RRS_ERR_BAD_CRC 0x0001
217#define RRS_ERR_CODE 0x0002
218#define RRS_ERR_DRIBBLE 0x0004
219#define RRS_ERR_RUNT 0x0008
220#define RRS_ERR_RX_OVERFLOW 0x0010
221#define RRS_ERR_TRUNC 0x0020
222#define RRS_ERR_IP_CSUM 0x0040
223#define RRS_ERR_L4_CSUM 0x0080
224#define RRS_ERR_LENGTH 0x0100
225#define RRS_ERR_DES_ADDR 0x0200
226
227struct atl1e_recv_ret_status {
228 u16 seq_num;
229 u16 hash_lo;
230 __le32 word1;
231 u16 pkt_flag;
232 u16 err_flag;
233 u16 hash_hi;
234 u16 vtag;
235};
236
237enum atl1e_dma_req_block {
238 atl1e_dma_req_128 = 0,
239 atl1e_dma_req_256 = 1,
240 atl1e_dma_req_512 = 2,
241 atl1e_dma_req_1024 = 3,
242 atl1e_dma_req_2048 = 4,
243 atl1e_dma_req_4096 = 5
244};
245
246enum atl1e_rrs_type {
247 atl1e_rrs_disable = 0,
248 atl1e_rrs_ipv4 = 1,
249 atl1e_rrs_ipv4_tcp = 2,
250 atl1e_rrs_ipv6 = 4,
251 atl1e_rrs_ipv6_tcp = 8
252};
253
254enum atl1e_nic_type {
255 athr_l1e = 0,
256 athr_l2e_revA = 1,
257 athr_l2e_revB = 2
258};
259
260struct atl1e_hw_stats {
261 /* rx */
262 unsigned long rx_ok; /* The number of good packet received. */
263 unsigned long rx_bcast; /* The number of good broadcast packet received. */
264 unsigned long rx_mcast; /* The number of good multicast packet received. */
265 unsigned long rx_pause; /* The number of Pause packet received. */
266 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
267 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
268 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
269 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
270 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
271 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
272 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
273 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
274 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
275 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
276 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
277 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
278 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
279 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
280 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
281 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
282 unsigned long rx_align_err; /* Alignment Error */
283 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
284 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
285 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
286
287 /* tx */
288 unsigned long tx_ok; /* The number of good packet transmitted. */
289 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
290 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
291 unsigned long tx_pause; /* The number of Pause packet transmitted. */
292 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
293 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
294 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
295 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
296 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
297 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
298 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
299 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
300 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
301 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
302 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
303 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
304 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
305 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
306 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
307 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
308 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
309 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
310 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
311 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
312 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
313};
314
315struct atl1e_hw {
316 u8 __iomem *hw_addr; /* inner register address */
317 resource_size_t mem_rang;
318 struct atl1e_adapter *adapter;
319 enum atl1e_nic_type nic_type;
320 u16 device_id;
321 u16 vendor_id;
322 u16 subsystem_id;
323 u16 subsystem_vendor_id;
324 u8 revision_id;
325 u16 pci_cmd_word;
326 u8 mac_addr[ETH_ALEN];
327 u8 perm_mac_addr[ETH_ALEN];
328 u8 preamble_len;
329 u16 max_frame_size;
330 u16 rx_jumbo_th;
331 u16 tx_jumbo_th;
332
333 u16 media_type;
334#define MEDIA_TYPE_AUTO_SENSOR 0
335#define MEDIA_TYPE_100M_FULL 1
336#define MEDIA_TYPE_100M_HALF 2
337#define MEDIA_TYPE_10M_FULL 3
338#define MEDIA_TYPE_10M_HALF 4
339
340 u16 autoneg_advertised;
341#define ADVERTISE_10_HALF 0x0001
342#define ADVERTISE_10_FULL 0x0002
343#define ADVERTISE_100_HALF 0x0004
344#define ADVERTISE_100_FULL 0x0008
345#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
346#define ADVERTISE_1000_FULL 0x0020
347 u16 mii_autoneg_adv_reg;
348 u16 mii_1000t_ctrl_reg;
349
350 u16 imt; /* Interrupt Moderator timer ( 2us resolution) */
351 u16 ict; /* Interrupt Clear timer (2us resolution) */
352 u32 smb_timer;
353 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
354 interrupt request */
355 u16 tpd_thresh;
356 u16 rx_count_down; /* 2us resolution */
357 u16 tx_count_down;
358
359 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
360 enum atl1e_rrs_type rrs_type;
361 u32 base_cpu;
362 u32 indirect_tab;
363
364 enum atl1e_dma_req_block dmar_block;
365 enum atl1e_dma_req_block dmaw_block;
366 u8 dmaw_dly_cnt;
367 u8 dmar_dly_cnt;
368
369 bool phy_configured;
370 bool re_autoneg;
371 bool emi_ca;
372};
373
374/*
375 * wrapper around a pointer to a socket buffer,
376 * so a DMA handle can be stored along with the buffer
377 */
378struct atl1e_tx_buffer {
379 struct sk_buff *skb;
380 u16 flags;
381#define ATL1E_TX_PCIMAP_SINGLE 0x0001
382#define ATL1E_TX_PCIMAP_PAGE 0x0002
383#define ATL1E_TX_PCIMAP_TYPE_MASK 0x0003
384 u16 length;
385 dma_addr_t dma;
386};
387
388#define ATL1E_SET_PCIMAP_TYPE(tx_buff, type) do { \
389 ((tx_buff)->flags) &= ~ATL1E_TX_PCIMAP_TYPE_MASK; \
390 ((tx_buff)->flags) |= (type); \
391 } while (0)
392
393struct atl1e_rx_page {
394 dma_addr_t dma; /* receive rage DMA address */
395 u8 *addr; /* receive rage virtual address */
396 dma_addr_t write_offset_dma; /* the DMA address which contain the
397 receive data offset in the page */
398 u32 *write_offset_addr; /* the virtaul address which contain
399 the receive data offset in the page */
400 u32 read_offset; /* the offset where we have read */
401};
402
403struct atl1e_rx_page_desc {
404 struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE];
405 u8 rx_using;
406 u16 rx_nxseq;
407};
408
409/* transmit packet descriptor (tpd) ring */
410struct atl1e_tx_ring {
411 struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */
412 dma_addr_t dma; /* descriptor ring physical address */
413 u16 count; /* the count of transmit rings */
414 rwlock_t tx_lock;
415 u16 next_to_use;
416 atomic_t next_to_clean;
417 struct atl1e_tx_buffer *tx_buffer;
418 dma_addr_t cmb_dma;
419 u32 *cmb;
420};
421
422/* receive packet descriptor ring */
423struct atl1e_rx_ring {
424 void *desc;
425 dma_addr_t dma;
426 int size;
427 u32 page_size; /* bytes length of rxf page */
428 u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
429 struct atl1e_rx_page_desc rx_page_desc[AT_MAX_RECEIVE_QUEUE];
430};
431
432/* board specific private data structure */
433struct atl1e_adapter {
434 struct net_device *netdev;
435 struct pci_dev *pdev;
436 struct napi_struct napi;
437 struct mii_if_info mii; /* MII interface info */
438 struct atl1e_hw hw;
439 struct atl1e_hw_stats hw_stats;
440
441 bool have_msi;
442 u32 wol;
443 u16 link_speed;
444 u16 link_duplex;
445
446 spinlock_t mdio_lock;
447 spinlock_t tx_lock;
448 atomic_t irq_sem;
449
450 struct work_struct reset_task;
451 struct work_struct link_chg_task;
452 struct timer_list watchdog_timer;
453 struct timer_list phy_config_timer;
454
455 /* All Descriptor memory */
456 dma_addr_t ring_dma;
457 void *ring_vir_addr;
458 u32 ring_size;
459
460 struct atl1e_tx_ring tx_ring;
461 struct atl1e_rx_ring rx_ring;
462 int num_rx_queues;
463 unsigned long flags;
464#define __AT_TESTING 0x0001
465#define __AT_RESETTING 0x0002
466#define __AT_DOWN 0x0003
467
468 u32 bd_number; /* board number;*/
469 u32 pci_state[16];
470 u32 *config_space;
471};
472
473#define AT_WRITE_REG(a, reg, value) ( \
474 writel((value), ((a)->hw_addr + reg)))
475
476#define AT_WRITE_FLUSH(a) (\
477 readl((a)->hw_addr))
478
479#define AT_READ_REG(a, reg) ( \
480 readl((a)->hw_addr + reg))
481
482#define AT_WRITE_REGB(a, reg, value) (\
483 writeb((value), ((a)->hw_addr + reg)))
484
485#define AT_READ_REGB(a, reg) (\
486 readb((a)->hw_addr + reg))
487
488#define AT_WRITE_REGW(a, reg, value) (\
489 writew((value), ((a)->hw_addr + reg)))
490
491#define AT_READ_REGW(a, reg) (\
492 readw((a)->hw_addr + reg))
493
494#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
495 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
496
497#define AT_READ_REG_ARRAY(a, reg, offset) ( \
498 readl(((a)->hw_addr + reg) + ((offset) << 2)))
499
500extern char atl1e_driver_name[];
501extern char atl1e_driver_version[];
502
503extern void atl1e_check_options(struct atl1e_adapter *adapter);
504extern int atl1e_up(struct atl1e_adapter *adapter);
505extern void atl1e_down(struct atl1e_adapter *adapter);
506extern void atl1e_reinit_locked(struct atl1e_adapter *adapter);
507extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
508extern void atl1e_set_ethtool_ops(struct net_device *netdev);
509#endif /* _ATL1_E_H_ */
diff --git a/drivers/net/atl1e/atl1e_ethtool.c b/drivers/net/atl1e/atl1e_ethtool.c
deleted file mode 100644
index 6269438d365f..000000000000
--- a/drivers/net/atl1e/atl1e_ethtool.c
+++ /dev/null
@@ -1,390 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 */
22
23#include <linux/netdevice.h>
24#include <linux/ethtool.h>
25#include <linux/slab.h>
26
27#include "atl1e.h"
28
29static int atl1e_get_settings(struct net_device *netdev,
30 struct ethtool_cmd *ecmd)
31{
32 struct atl1e_adapter *adapter = netdev_priv(netdev);
33 struct atl1e_hw *hw = &adapter->hw;
34
35 ecmd->supported = (SUPPORTED_10baseT_Half |
36 SUPPORTED_10baseT_Full |
37 SUPPORTED_100baseT_Half |
38 SUPPORTED_100baseT_Full |
39 SUPPORTED_Autoneg |
40 SUPPORTED_TP);
41 if (hw->nic_type == athr_l1e)
42 ecmd->supported |= SUPPORTED_1000baseT_Full;
43
44 ecmd->advertising = ADVERTISED_TP;
45
46 ecmd->advertising |= ADVERTISED_Autoneg;
47 ecmd->advertising |= hw->autoneg_advertised;
48
49 ecmd->port = PORT_TP;
50 ecmd->phy_address = 0;
51 ecmd->transceiver = XCVR_INTERNAL;
52
53 if (adapter->link_speed != SPEED_0) {
54 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
55 if (adapter->link_duplex == FULL_DUPLEX)
56 ecmd->duplex = DUPLEX_FULL;
57 else
58 ecmd->duplex = DUPLEX_HALF;
59 } else {
60 ethtool_cmd_speed_set(ecmd, -1);
61 ecmd->duplex = -1;
62 }
63
64 ecmd->autoneg = AUTONEG_ENABLE;
65 return 0;
66}
67
68static int atl1e_set_settings(struct net_device *netdev,
69 struct ethtool_cmd *ecmd)
70{
71 struct atl1e_adapter *adapter = netdev_priv(netdev);
72 struct atl1e_hw *hw = &adapter->hw;
73
74 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
75 msleep(1);
76
77 if (ecmd->autoneg == AUTONEG_ENABLE) {
78 u16 adv4, adv9;
79
80 if ((ecmd->advertising&ADVERTISE_1000_FULL)) {
81 if (hw->nic_type == athr_l1e) {
82 hw->autoneg_advertised =
83 ecmd->advertising & AT_ADV_MASK;
84 } else {
85 clear_bit(__AT_RESETTING, &adapter->flags);
86 return -EINVAL;
87 }
88 } else if (ecmd->advertising&ADVERTISE_1000_HALF) {
89 clear_bit(__AT_RESETTING, &adapter->flags);
90 return -EINVAL;
91 } else {
92 hw->autoneg_advertised =
93 ecmd->advertising & AT_ADV_MASK;
94 }
95 ecmd->advertising = hw->autoneg_advertised |
96 ADVERTISED_TP | ADVERTISED_Autoneg;
97
98 adv4 = hw->mii_autoneg_adv_reg & ~ADVERTISE_ALL;
99 adv9 = hw->mii_1000t_ctrl_reg & ~MII_AT001_CR_1000T_SPEED_MASK;
100 if (hw->autoneg_advertised & ADVERTISE_10_HALF)
101 adv4 |= ADVERTISE_10HALF;
102 if (hw->autoneg_advertised & ADVERTISE_10_FULL)
103 adv4 |= ADVERTISE_10FULL;
104 if (hw->autoneg_advertised & ADVERTISE_100_HALF)
105 adv4 |= ADVERTISE_100HALF;
106 if (hw->autoneg_advertised & ADVERTISE_100_FULL)
107 adv4 |= ADVERTISE_100FULL;
108 if (hw->autoneg_advertised & ADVERTISE_1000_FULL)
109 adv9 |= ADVERTISE_1000FULL;
110
111 if (adv4 != hw->mii_autoneg_adv_reg ||
112 adv9 != hw->mii_1000t_ctrl_reg) {
113 hw->mii_autoneg_adv_reg = adv4;
114 hw->mii_1000t_ctrl_reg = adv9;
115 hw->re_autoneg = true;
116 }
117
118 } else {
119 clear_bit(__AT_RESETTING, &adapter->flags);
120 return -EINVAL;
121 }
122
123 /* reset the link */
124
125 if (netif_running(adapter->netdev)) {
126 atl1e_down(adapter);
127 atl1e_up(adapter);
128 } else
129 atl1e_reset_hw(&adapter->hw);
130
131 clear_bit(__AT_RESETTING, &adapter->flags);
132 return 0;
133}
134
135static u32 atl1e_get_msglevel(struct net_device *netdev)
136{
137#ifdef DBG
138 return 1;
139#else
140 return 0;
141#endif
142}
143
144static int atl1e_get_regs_len(struct net_device *netdev)
145{
146 return AT_REGS_LEN * sizeof(u32);
147}
148
149static void atl1e_get_regs(struct net_device *netdev,
150 struct ethtool_regs *regs, void *p)
151{
152 struct atl1e_adapter *adapter = netdev_priv(netdev);
153 struct atl1e_hw *hw = &adapter->hw;
154 u32 *regs_buff = p;
155 u16 phy_data;
156
157 memset(p, 0, AT_REGS_LEN * sizeof(u32));
158
159 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
160
161 regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP);
162 regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
163 regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG);
164 regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL);
165 regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
166 regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL);
167 regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT);
168 regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
169 regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL);
170 regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER);
171 regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS);
172 regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL);
173 regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK);
174 regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL);
175 regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG);
176 regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
177 regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4);
178 regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE);
179 regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4);
180 regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
181 regs_buff[20] = AT_READ_REG(hw, REG_MTU);
182 regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL);
183 regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR);
184 regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN);
185 regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR);
186 regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
187 regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR);
188 regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN);
189 regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR);
190 regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR);
191
192 atl1e_read_phy_reg(hw, MII_BMCR, &phy_data);
193 regs_buff[73] = (u32)phy_data;
194 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
195 regs_buff[74] = (u32)phy_data;
196}
197
198static int atl1e_get_eeprom_len(struct net_device *netdev)
199{
200 struct atl1e_adapter *adapter = netdev_priv(netdev);
201
202 if (!atl1e_check_eeprom_exist(&adapter->hw))
203 return AT_EEPROM_LEN;
204 else
205 return 0;
206}
207
208static int atl1e_get_eeprom(struct net_device *netdev,
209 struct ethtool_eeprom *eeprom, u8 *bytes)
210{
211 struct atl1e_adapter *adapter = netdev_priv(netdev);
212 struct atl1e_hw *hw = &adapter->hw;
213 u32 *eeprom_buff;
214 int first_dword, last_dword;
215 int ret_val = 0;
216 int i;
217
218 if (eeprom->len == 0)
219 return -EINVAL;
220
221 if (atl1e_check_eeprom_exist(hw)) /* not exist */
222 return -EINVAL;
223
224 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
225
226 first_dword = eeprom->offset >> 2;
227 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
228
229 eeprom_buff = kmalloc(sizeof(u32) *
230 (last_dword - first_dword + 1), GFP_KERNEL);
231 if (eeprom_buff == NULL)
232 return -ENOMEM;
233
234 for (i = first_dword; i < last_dword; i++) {
235 if (!atl1e_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
236 kfree(eeprom_buff);
237 return -EIO;
238 }
239 }
240
241 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
242 eeprom->len);
243 kfree(eeprom_buff);
244
245 return ret_val;
246}
247
248static int atl1e_set_eeprom(struct net_device *netdev,
249 struct ethtool_eeprom *eeprom, u8 *bytes)
250{
251 struct atl1e_adapter *adapter = netdev_priv(netdev);
252 struct atl1e_hw *hw = &adapter->hw;
253 u32 *eeprom_buff;
254 u32 *ptr;
255 int first_dword, last_dword;
256 int ret_val = 0;
257 int i;
258
259 if (eeprom->len == 0)
260 return -EOPNOTSUPP;
261
262 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
263 return -EINVAL;
264
265 first_dword = eeprom->offset >> 2;
266 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
267 eeprom_buff = kmalloc(AT_EEPROM_LEN, GFP_KERNEL);
268 if (eeprom_buff == NULL)
269 return -ENOMEM;
270
271 ptr = (u32 *)eeprom_buff;
272
273 if (eeprom->offset & 3) {
274 /* need read/modify/write of first changed EEPROM word */
275 /* only the second byte of the word is being modified */
276 if (!atl1e_read_eeprom(hw, first_dword * 4, &(eeprom_buff[0]))) {
277 ret_val = -EIO;
278 goto out;
279 }
280 ptr++;
281 }
282 if (((eeprom->offset + eeprom->len) & 3)) {
283 /* need read/modify/write of last changed EEPROM word */
284 /* only the first byte of the word is being modified */
285
286 if (!atl1e_read_eeprom(hw, last_dword * 4,
287 &(eeprom_buff[last_dword - first_dword]))) {
288 ret_val = -EIO;
289 goto out;
290 }
291 }
292
293 /* Device's eeprom is always little-endian, word addressable */
294 memcpy(ptr, bytes, eeprom->len);
295
296 for (i = 0; i < last_dword - first_dword + 1; i++) {
297 if (!atl1e_write_eeprom(hw, ((first_dword + i) * 4),
298 eeprom_buff[i])) {
299 ret_val = -EIO;
300 goto out;
301 }
302 }
303out:
304 kfree(eeprom_buff);
305 return ret_val;
306}
307
308static void atl1e_get_drvinfo(struct net_device *netdev,
309 struct ethtool_drvinfo *drvinfo)
310{
311 struct atl1e_adapter *adapter = netdev_priv(netdev);
312
313 strncpy(drvinfo->driver, atl1e_driver_name, 32);
314 strncpy(drvinfo->version, atl1e_driver_version, 32);
315 strncpy(drvinfo->fw_version, "L1e", 32);
316 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
317 drvinfo->n_stats = 0;
318 drvinfo->testinfo_len = 0;
319 drvinfo->regdump_len = atl1e_get_regs_len(netdev);
320 drvinfo->eedump_len = atl1e_get_eeprom_len(netdev);
321}
322
323static void atl1e_get_wol(struct net_device *netdev,
324 struct ethtool_wolinfo *wol)
325{
326 struct atl1e_adapter *adapter = netdev_priv(netdev);
327
328 wol->supported = WAKE_MAGIC | WAKE_PHY;
329 wol->wolopts = 0;
330
331 if (adapter->wol & AT_WUFC_EX)
332 wol->wolopts |= WAKE_UCAST;
333 if (adapter->wol & AT_WUFC_MC)
334 wol->wolopts |= WAKE_MCAST;
335 if (adapter->wol & AT_WUFC_BC)
336 wol->wolopts |= WAKE_BCAST;
337 if (adapter->wol & AT_WUFC_MAG)
338 wol->wolopts |= WAKE_MAGIC;
339 if (adapter->wol & AT_WUFC_LNKC)
340 wol->wolopts |= WAKE_PHY;
341}
342
343static int atl1e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
344{
345 struct atl1e_adapter *adapter = netdev_priv(netdev);
346
347 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
348 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
349 return -EOPNOTSUPP;
350 /* these settings will always override what we currently have */
351 adapter->wol = 0;
352
353 if (wol->wolopts & WAKE_MAGIC)
354 adapter->wol |= AT_WUFC_MAG;
355 if (wol->wolopts & WAKE_PHY)
356 adapter->wol |= AT_WUFC_LNKC;
357
358 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
359
360 return 0;
361}
362
363static int atl1e_nway_reset(struct net_device *netdev)
364{
365 struct atl1e_adapter *adapter = netdev_priv(netdev);
366 if (netif_running(netdev))
367 atl1e_reinit_locked(adapter);
368 return 0;
369}
370
371static const struct ethtool_ops atl1e_ethtool_ops = {
372 .get_settings = atl1e_get_settings,
373 .set_settings = atl1e_set_settings,
374 .get_drvinfo = atl1e_get_drvinfo,
375 .get_regs_len = atl1e_get_regs_len,
376 .get_regs = atl1e_get_regs,
377 .get_wol = atl1e_get_wol,
378 .set_wol = atl1e_set_wol,
379 .get_msglevel = atl1e_get_msglevel,
380 .nway_reset = atl1e_nway_reset,
381 .get_link = ethtool_op_get_link,
382 .get_eeprom_len = atl1e_get_eeprom_len,
383 .get_eeprom = atl1e_get_eeprom,
384 .set_eeprom = atl1e_set_eeprom,
385};
386
387void atl1e_set_ethtool_ops(struct net_device *netdev)
388{
389 SET_ETHTOOL_OPS(netdev, &atl1e_ethtool_ops);
390}
diff --git a/drivers/net/atl1e/atl1e_hw.c b/drivers/net/atl1e/atl1e_hw.c
deleted file mode 100644
index 923063d2e5bb..000000000000
--- a/drivers/net/atl1e/atl1e_hw.c
+++ /dev/null
@@ -1,651 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/mii.h>
24#include <linux/crc32.h>
25
26#include "atl1e.h"
27
28/*
29 * check_eeprom_exist
30 * return 0 if eeprom exist
31 */
32int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
33{
34 u32 value;
35
36 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
37 if (value & SPI_FLASH_CTRL_EN_VPD) {
38 value &= ~SPI_FLASH_CTRL_EN_VPD;
39 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
40 }
41 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
42 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
43}
44
45void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
46{
47 u32 value;
48 /*
49 * 00-0B-6A-F6-00-DC
50 * 0: 6AF600DC 1: 000B
51 * low dword
52 */
53 value = (((u32)hw->mac_addr[2]) << 24) |
54 (((u32)hw->mac_addr[3]) << 16) |
55 (((u32)hw->mac_addr[4]) << 8) |
56 (((u32)hw->mac_addr[5])) ;
57 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
58 /* hight dword */
59 value = (((u32)hw->mac_addr[0]) << 8) |
60 (((u32)hw->mac_addr[1])) ;
61 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
62}
63
64/*
65 * atl1e_get_permanent_address
66 * return 0 if get valid mac address,
67 */
68static int atl1e_get_permanent_address(struct atl1e_hw *hw)
69{
70 u32 addr[2];
71 u32 i;
72 u32 twsi_ctrl_data;
73 u8 eth_addr[ETH_ALEN];
74
75 if (is_valid_ether_addr(hw->perm_mac_addr))
76 return 0;
77
78 /* init */
79 addr[0] = addr[1] = 0;
80
81 if (!atl1e_check_eeprom_exist(hw)) {
82 /* eeprom exist */
83 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
84 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
85 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
86 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
87 msleep(10);
88 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
89 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
90 break;
91 }
92 if (i >= AT_TWSI_EEPROM_TIMEOUT)
93 return AT_ERR_TIMEOUT;
94 }
95
96 /* maybe MAC-address is from BIOS */
97 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
98 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
99 *(u32 *) &eth_addr[2] = swab32(addr[0]);
100 *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
101
102 if (is_valid_ether_addr(eth_addr)) {
103 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
104 return 0;
105 }
106
107 return AT_ERR_EEPROM;
108}
109
110bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
111{
112 return true;
113}
114
115bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
116{
117 int i;
118 u32 control;
119
120 if (offset & 3)
121 return false; /* address do not align */
122
123 AT_WRITE_REG(hw, REG_VPD_DATA, 0);
124 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
125 AT_WRITE_REG(hw, REG_VPD_CAP, control);
126
127 for (i = 0; i < 10; i++) {
128 msleep(2);
129 control = AT_READ_REG(hw, REG_VPD_CAP);
130 if (control & VPD_CAP_VPD_FLAG)
131 break;
132 }
133 if (control & VPD_CAP_VPD_FLAG) {
134 *p_value = AT_READ_REG(hw, REG_VPD_DATA);
135 return true;
136 }
137 return false; /* timeout */
138}
139
140void atl1e_force_ps(struct atl1e_hw *hw)
141{
142 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
143 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
144}
145
146/*
147 * Reads the adapter's MAC address from the EEPROM
148 *
149 * hw - Struct containing variables accessed by shared code
150 */
151int atl1e_read_mac_addr(struct atl1e_hw *hw)
152{
153 int err = 0;
154
155 err = atl1e_get_permanent_address(hw);
156 if (err)
157 return AT_ERR_EEPROM;
158 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
159 return 0;
160}
161
162/*
163 * atl1e_hash_mc_addr
164 * purpose
165 * set hash value for a multicast address
166 */
167u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
168{
169 u32 crc32;
170 u32 value = 0;
171 int i;
172
173 crc32 = ether_crc_le(6, mc_addr);
174 for (i = 0; i < 32; i++)
175 value |= (((crc32 >> i) & 1) << (31 - i));
176
177 return value;
178}
179
180/*
181 * Sets the bit in the multicast table corresponding to the hash value.
182 * hw - Struct containing variables accessed by shared code
183 * hash_value - Multicast address hash value
184 */
185void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
186{
187 u32 hash_bit, hash_reg;
188 u32 mta;
189
190 /*
191 * The HASH Table is a register array of 2 32-bit registers.
192 * It is treated like an array of 64 bits. We want to set
193 * bit BitArray[hash_value]. So we figure out what register
194 * the bit is in, read it, OR in the new bit, then write
195 * back the new value. The register is determined by the
196 * upper 7 bits of the hash value and the bit within that
197 * register are determined by the lower 5 bits of the value.
198 */
199 hash_reg = (hash_value >> 31) & 0x1;
200 hash_bit = (hash_value >> 26) & 0x1F;
201
202 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
203
204 mta |= (1 << hash_bit);
205
206 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
207}
208/*
209 * Reads the value from a PHY register
210 * hw - Struct containing variables accessed by shared code
211 * reg_addr - address of the PHY register to read
212 */
213int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
214{
215 u32 val;
216 int i;
217
218 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
219 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
220 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
221
222 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
223
224 wmb();
225
226 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
227 udelay(2);
228 val = AT_READ_REG(hw, REG_MDIO_CTRL);
229 if (!(val & (MDIO_START | MDIO_BUSY)))
230 break;
231 wmb();
232 }
233 if (!(val & (MDIO_START | MDIO_BUSY))) {
234 *phy_data = (u16)val;
235 return 0;
236 }
237
238 return AT_ERR_PHY;
239}
240
241/*
242 * Writes a value to a PHY register
243 * hw - Struct containing variables accessed by shared code
244 * reg_addr - address of the PHY register to write
245 * data - data to write to the PHY
246 */
247int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
248{
249 int i;
250 u32 val;
251
252 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
253 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
254 MDIO_SUP_PREAMBLE |
255 MDIO_START |
256 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
257
258 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
259 wmb();
260
261 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
262 udelay(2);
263 val = AT_READ_REG(hw, REG_MDIO_CTRL);
264 if (!(val & (MDIO_START | MDIO_BUSY)))
265 break;
266 wmb();
267 }
268
269 if (!(val & (MDIO_START | MDIO_BUSY)))
270 return 0;
271
272 return AT_ERR_PHY;
273}
274
275/*
276 * atl1e_init_pcie - init PCIE module
277 */
278static void atl1e_init_pcie(struct atl1e_hw *hw)
279{
280 u32 value;
281 /* comment 2lines below to save more power when sususpend
282 value = LTSSM_TEST_MODE_DEF;
283 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
284 */
285
286 /* pcie flow control mode change */
287 value = AT_READ_REG(hw, 0x1008);
288 value |= 0x8000;
289 AT_WRITE_REG(hw, 0x1008, value);
290}
291/*
292 * Configures PHY autoneg and flow control advertisement settings
293 *
294 * hw - Struct containing variables accessed by shared code
295 */
296static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
297{
298 s32 ret_val;
299 u16 mii_autoneg_adv_reg;
300 u16 mii_1000t_ctrl_reg;
301
302 if (0 != hw->mii_autoneg_adv_reg)
303 return 0;
304 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
305 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
306 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
307
308 /*
309 * Need to parse autoneg_advertised and set up
310 * the appropriate PHY registers. First we will parse for
311 * autoneg_advertised software override. Since we can advertise
312 * a plethora of combinations, we need to check each bit
313 * individually.
314 */
315
316 /*
317 * First we clear all the 10/100 mb speed bits in the Auto-Neg
318 * Advertisement Register (Address 4) and the 1000 mb speed bits in
319 * the 1000Base-T control Register (Address 9).
320 */
321 mii_autoneg_adv_reg &= ~ADVERTISE_ALL;
322 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
323
324 /*
325 * Need to parse MediaType and setup the
326 * appropriate PHY registers.
327 */
328 switch (hw->media_type) {
329 case MEDIA_TYPE_AUTO_SENSOR:
330 mii_autoneg_adv_reg |= ADVERTISE_ALL;
331 hw->autoneg_advertised = ADVERTISE_ALL;
332 if (hw->nic_type == athr_l1e) {
333 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
334 hw->autoneg_advertised |= ADVERTISE_1000_FULL;
335 }
336 break;
337
338 case MEDIA_TYPE_100M_FULL:
339 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
340 hw->autoneg_advertised = ADVERTISE_100_FULL;
341 break;
342
343 case MEDIA_TYPE_100M_HALF:
344 mii_autoneg_adv_reg |= ADVERTISE_100_HALF;
345 hw->autoneg_advertised = ADVERTISE_100_HALF;
346 break;
347
348 case MEDIA_TYPE_10M_FULL:
349 mii_autoneg_adv_reg |= ADVERTISE_10_FULL;
350 hw->autoneg_advertised = ADVERTISE_10_FULL;
351 break;
352
353 default:
354 mii_autoneg_adv_reg |= ADVERTISE_10_HALF;
355 hw->autoneg_advertised = ADVERTISE_10_HALF;
356 break;
357 }
358
359 /* flow control fixed to enable all */
360 mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
361
362 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
363 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
364
365 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
366 if (ret_val)
367 return ret_val;
368
369 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
370 ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
371 mii_1000t_ctrl_reg);
372 if (ret_val)
373 return ret_val;
374 }
375
376 return 0;
377}
378
379
380/*
381 * Resets the PHY and make all config validate
382 *
383 * hw - Struct containing variables accessed by shared code
384 *
385 * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
386 */
387int atl1e_phy_commit(struct atl1e_hw *hw)
388{
389 struct atl1e_adapter *adapter = hw->adapter;
390 int ret_val;
391 u16 phy_data;
392
393 phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
394
395 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
396 if (ret_val) {
397 u32 val;
398 int i;
399 /**************************************
400 * pcie serdes link may be down !
401 **************************************/
402 for (i = 0; i < 25; i++) {
403 msleep(1);
404 val = AT_READ_REG(hw, REG_MDIO_CTRL);
405 if (!(val & (MDIO_START | MDIO_BUSY)))
406 break;
407 }
408
409 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
410 netdev_err(adapter->netdev,
411 "pcie linkdown at least for 25ms\n");
412 return ret_val;
413 }
414
415 netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i);
416 }
417 return 0;
418}
419
420int atl1e_phy_init(struct atl1e_hw *hw)
421{
422 struct atl1e_adapter *adapter = hw->adapter;
423 s32 ret_val;
424 u16 phy_val;
425
426 if (hw->phy_configured) {
427 if (hw->re_autoneg) {
428 hw->re_autoneg = false;
429 return atl1e_restart_autoneg(hw);
430 }
431 return 0;
432 }
433
434 /* RESET GPHY Core */
435 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
436 msleep(2);
437 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
438 GPHY_CTRL_EXT_RESET);
439 msleep(2);
440
441 /* patches */
442 /* p1. eable hibernation mode */
443 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
444 if (ret_val)
445 return ret_val;
446 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
447 if (ret_val)
448 return ret_val;
449 /* p2. set Class A/B for all modes */
450 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
451 if (ret_val)
452 return ret_val;
453 phy_val = 0x02ef;
454 /* remove Class AB */
455 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
456 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
457 if (ret_val)
458 return ret_val;
459 /* p3. 10B ??? */
460 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
461 if (ret_val)
462 return ret_val;
463 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
464 if (ret_val)
465 return ret_val;
466 /* p4. 1000T power */
467 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
468 if (ret_val)
469 return ret_val;
470 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
471 if (ret_val)
472 return ret_val;
473
474 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
475 if (ret_val)
476 return ret_val;
477 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
478 if (ret_val)
479 return ret_val;
480
481 msleep(1);
482
483 /*Enable PHY LinkChange Interrupt */
484 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
485 if (ret_val) {
486 netdev_err(adapter->netdev,
487 "Error enable PHY linkChange Interrupt\n");
488 return ret_val;
489 }
490 /* setup AutoNeg parameters */
491 ret_val = atl1e_phy_setup_autoneg_adv(hw);
492 if (ret_val) {
493 netdev_err(adapter->netdev,
494 "Error Setting up Auto-Negotiation\n");
495 return ret_val;
496 }
497 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
498 netdev_dbg(adapter->netdev, "Restarting Auto-Negotiation\n");
499 ret_val = atl1e_phy_commit(hw);
500 if (ret_val) {
501 netdev_err(adapter->netdev, "Error resetting the phy\n");
502 return ret_val;
503 }
504
505 hw->phy_configured = true;
506
507 return 0;
508}
509
510/*
511 * Reset the transmit and receive units; mask and clear all interrupts.
512 * hw - Struct containing variables accessed by shared code
513 * return : 0 or idle status (if error)
514 */
515int atl1e_reset_hw(struct atl1e_hw *hw)
516{
517 struct atl1e_adapter *adapter = hw->adapter;
518 struct pci_dev *pdev = adapter->pdev;
519
520 u32 idle_status_data = 0;
521 u16 pci_cfg_cmd_word = 0;
522 int timeout = 0;
523
524 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
525 pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word);
526 if ((pci_cfg_cmd_word & (CMD_IO_SPACE |
527 CMD_MEMORY_SPACE | CMD_BUS_MASTER))
528 != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) {
529 pci_cfg_cmd_word |= (CMD_IO_SPACE |
530 CMD_MEMORY_SPACE | CMD_BUS_MASTER);
531 pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word);
532 }
533
534 /*
535 * Issue Soft Reset to the MAC. This will reset the chip's
536 * transmit, receive, DMA. It will not effect
537 * the current PCI configuration. The global reset bit is self-
538 * clearing, and should clear within a microsecond.
539 */
540 AT_WRITE_REG(hw, REG_MASTER_CTRL,
541 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
542 wmb();
543 msleep(1);
544
545 /* Wait at least 10ms for All module to be Idle */
546 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
547 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
548 if (idle_status_data == 0)
549 break;
550 msleep(1);
551 cpu_relax();
552 }
553
554 if (timeout >= AT_HW_MAX_IDLE_DELAY) {
555 netdev_err(adapter->netdev,
556 "MAC state machine can't be idle since disabled for 10ms second\n");
557 return AT_ERR_TIMEOUT;
558 }
559
560 return 0;
561}
562
563
564/*
565 * Performs basic configuration of the adapter.
566 *
567 * hw - Struct containing variables accessed by shared code
568 * Assumes that the controller has previously been reset and is in a
569 * post-reset uninitialized state. Initializes multicast table,
570 * and Calls routines to setup link
571 * Leaves the transmit and receive units disabled and uninitialized.
572 */
573int atl1e_init_hw(struct atl1e_hw *hw)
574{
575 s32 ret_val = 0;
576
577 atl1e_init_pcie(hw);
578
579 /* Zero out the Multicast HASH table */
580 /* clear the old settings from the multicast hash table */
581 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
582 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
583
584 ret_val = atl1e_phy_init(hw);
585
586 return ret_val;
587}
588
589/*
590 * Detects the current speed and duplex settings of the hardware.
591 *
592 * hw - Struct containing variables accessed by shared code
593 * speed - Speed of the connection
594 * duplex - Duplex setting of the connection
595 */
596int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
597{
598 int err;
599 u16 phy_data;
600
601 /* Read PHY Specific Status Register (17) */
602 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
603 if (err)
604 return err;
605
606 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
607 return AT_ERR_PHY_RES;
608
609 switch (phy_data & MII_AT001_PSSR_SPEED) {
610 case MII_AT001_PSSR_1000MBS:
611 *speed = SPEED_1000;
612 break;
613 case MII_AT001_PSSR_100MBS:
614 *speed = SPEED_100;
615 break;
616 case MII_AT001_PSSR_10MBS:
617 *speed = SPEED_10;
618 break;
619 default:
620 return AT_ERR_PHY_SPEED;
621 break;
622 }
623
624 if (phy_data & MII_AT001_PSSR_DPLX)
625 *duplex = FULL_DUPLEX;
626 else
627 *duplex = HALF_DUPLEX;
628
629 return 0;
630}
631
632int atl1e_restart_autoneg(struct atl1e_hw *hw)
633{
634 int err = 0;
635
636 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
637 if (err)
638 return err;
639
640 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
641 err = atl1e_write_phy_reg(hw, MII_CTRL1000,
642 hw->mii_1000t_ctrl_reg);
643 if (err)
644 return err;
645 }
646
647 err = atl1e_write_phy_reg(hw, MII_BMCR,
648 BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
649 return err;
650}
651
diff --git a/drivers/net/atl1e/atl1e_hw.h b/drivers/net/atl1e/atl1e_hw.h
deleted file mode 100644
index 74df16aef793..000000000000
--- a/drivers/net/atl1e/atl1e_hw.h
+++ /dev/null
@@ -1,690 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATHL1E_HW_H_
23#define _ATHL1E_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1e_adapter;
29struct atl1e_hw;
30
31/* function prototype */
32s32 atl1e_reset_hw(struct atl1e_hw *hw);
33s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
34s32 atl1e_init_hw(struct atl1e_hw *hw);
35s32 atl1e_phy_commit(struct atl1e_hw *hw);
36s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
38u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr);
39void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value);
40s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
41s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
42s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
43void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
44bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value);
45bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value);
46s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
47s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
48s32 atl1e_phy_init(struct atl1e_hw *hw);
49int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
50void atl1e_force_ps(struct atl1e_hw *hw);
51s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
52
53/* register definition */
54#define REG_PM_CTRLSTAT 0x44
55
56#define REG_PCIE_CAP_LIST 0x58
57
58#define REG_DEVICE_CAP 0x5C
59#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
60#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
61
62#define REG_DEVICE_CTRL 0x60
63#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
64#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
65#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
66#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
67
68#define REG_VPD_CAP 0x6C
69#define VPD_CAP_ID_MASK 0xff
70#define VPD_CAP_ID_SHIFT 0
71#define VPD_CAP_NEXT_PTR_MASK 0xFF
72#define VPD_CAP_NEXT_PTR_SHIFT 8
73#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
74#define VPD_CAP_VPD_ADDR_SHIFT 16
75#define VPD_CAP_VPD_FLAG 0x80000000
76
77#define REG_VPD_DATA 0x70
78
79#define REG_SPI_FLASH_CTRL 0x200
80#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
81#define SPI_FLASH_CTRL_STS_WEN 0x2
82#define SPI_FLASH_CTRL_STS_WPEN 0x80
83#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
84#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
85#define SPI_FLASH_CTRL_INS_MASK 0x7
86#define SPI_FLASH_CTRL_INS_SHIFT 8
87#define SPI_FLASH_CTRL_START 0x800
88#define SPI_FLASH_CTRL_EN_VPD 0x2000
89#define SPI_FLASH_CTRL_LDSTART 0x8000
90#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
91#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
92#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
93#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
94#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
95#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
96#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
97#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
98#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
99#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
100#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
101#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
102#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
103
104#define REG_SPI_ADDR 0x204
105
106#define REG_SPI_DATA 0x208
107
108#define REG_SPI_FLASH_CONFIG 0x20C
109#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
110#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
111#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
112#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
113#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
114
115
116#define REG_SPI_FLASH_OP_PROGRAM 0x210
117#define REG_SPI_FLASH_OP_SC_ERASE 0x211
118#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
119#define REG_SPI_FLASH_OP_RDID 0x213
120#define REG_SPI_FLASH_OP_WREN 0x214
121#define REG_SPI_FLASH_OP_RDSR 0x215
122#define REG_SPI_FLASH_OP_WRSR 0x216
123#define REG_SPI_FLASH_OP_READ 0x217
124
125#define REG_TWSI_CTRL 0x218
126#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
127#define TWSI_CTRL_LD_OFFSET_SHIFT 0
128#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
129#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
130#define TWSI_CTRL_SW_LDSTART 0x800
131#define TWSI_CTRL_HW_LDSTART 0x1000
132#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
133#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
134#define TWSI_CTRL_LD_EXIST 0x400000
135#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
136#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
137#define TWSI_CTRL_FREQ_SEL_100K 0
138#define TWSI_CTRL_FREQ_SEL_200K 1
139#define TWSI_CTRL_FREQ_SEL_300K 2
140#define TWSI_CTRL_FREQ_SEL_400K 3
141#define TWSI_CTRL_SMB_SLV_ADDR
142#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
143#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
144
145
146#define REG_PCIE_DEV_MISC_CTRL 0x21C
147#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
148#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
149#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
150#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
151#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
152
153#define REG_PCIE_PHYMISC 0x1000
154#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
155
156#define REG_LTSSM_TEST_MODE 0x12FC
157#define LTSSM_TEST_MODE_DEF 0xE000
158
159/* Selene Master Control Register */
160#define REG_MASTER_CTRL 0x1400
161#define MASTER_CTRL_SOFT_RST 0x1
162#define MASTER_CTRL_MTIMER_EN 0x2
163#define MASTER_CTRL_ITIMER_EN 0x4
164#define MASTER_CTRL_MANUAL_INT 0x8
165#define MASTER_CTRL_ITIMER2_EN 0x20
166#define MASTER_CTRL_INT_RDCLR 0x40
167#define MASTER_CTRL_LED_MODE 0x200
168#define MASTER_CTRL_REV_NUM_SHIFT 16
169#define MASTER_CTRL_REV_NUM_MASK 0xff
170#define MASTER_CTRL_DEV_ID_SHIFT 24
171#define MASTER_CTRL_DEV_ID_MASK 0xff
172
173/* Timer Initial Value Register */
174#define REG_MANUAL_TIMER_INIT 0x1404
175
176
177/* IRQ ModeratorTimer Initial Value Register */
178#define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
179#define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
180
181
182#define REG_GPHY_CTRL 0x140C
183#define GPHY_CTRL_EXT_RESET 1
184#define GPHY_CTRL_PIPE_MOD 2
185#define GPHY_CTRL_TEST_MODE_MASK 3
186#define GPHY_CTRL_TEST_MODE_SHIFT 2
187#define GPHY_CTRL_BERT_START 0x10
188#define GPHY_CTRL_GATE_25M_EN 0x20
189#define GPHY_CTRL_LPW_EXIT 0x40
190#define GPHY_CTRL_PHY_IDDQ 0x80
191#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
192#define GPHY_CTRL_PCLK_SEL_DIS 0x200
193#define GPHY_CTRL_HIB_EN 0x400
194#define GPHY_CTRL_HIB_PULSE 0x800
195#define GPHY_CTRL_SEL_ANA_RST 0x1000
196#define GPHY_CTRL_PHY_PLL_ON 0x2000
197#define GPHY_CTRL_PWDOWN_HW 0x4000
198#define GPHY_CTRL_DEFAULT (\
199 GPHY_CTRL_PHY_PLL_ON |\
200 GPHY_CTRL_SEL_ANA_RST |\
201 GPHY_CTRL_HIB_PULSE |\
202 GPHY_CTRL_HIB_EN)
203
204#define GPHY_CTRL_PW_WOL_DIS (\
205 GPHY_CTRL_PHY_PLL_ON |\
206 GPHY_CTRL_SEL_ANA_RST |\
207 GPHY_CTRL_HIB_PULSE |\
208 GPHY_CTRL_HIB_EN |\
209 GPHY_CTRL_PWDOWN_HW |\
210 GPHY_CTRL_PCLK_SEL_DIS |\
211 GPHY_CTRL_PHY_IDDQ)
212
213/* IRQ Anti-Lost Timer Initial Value Register */
214#define REG_CMBDISDMA_TIMER 0x140E
215
216
217/* Block IDLE Status Register */
218#define REG_IDLE_STATUS 0x1410
219#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
220#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
221#define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
222#define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
223#define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
224#define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
225#define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
226#define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
227
228/* MDIO Control Register */
229#define REG_MDIO_CTRL 0x1414
230#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
231#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
232#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
233#define MDIO_REG_ADDR_SHIFT 16
234#define MDIO_RW 0x200000 /* 1: read, 0: write */
235#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
236#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
237#define MDIO_CLK_SEL_SHIFT 24
238#define MDIO_CLK_25_4 0
239#define MDIO_CLK_25_6 2
240#define MDIO_CLK_25_8 3
241#define MDIO_CLK_25_10 4
242#define MDIO_CLK_25_14 5
243#define MDIO_CLK_25_20 6
244#define MDIO_CLK_25_28 7
245#define MDIO_BUSY 0x8000000
246#define MDIO_AP_EN 0x10000000
247#define MDIO_WAIT_TIMES 10
248
249/* MII PHY Status Register */
250#define REG_PHY_STATUS 0x1418
251#define PHY_STATUS_100M 0x20000
252#define PHY_STATUS_EMI_CA 0x40000
253
254/* BIST Control and Status Register0 (for the Packet Memory) */
255#define REG_BIST0_CTRL 0x141c
256#define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
257/* BIST process and reset to zero when BIST is done */
258#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
259/* decoder failure or more than 1 cell stuck-to-x failure */
260#define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
261
262/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
263#define REG_BIST1_CTRL 0x1420
264#define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
265/* BIST process and reset to zero when BIST is done */
266#define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
267/* decoder failure or more than 1 cell stuck-to-x failure.*/
268#define BIST1_FUSE_FLAG 0x4
269
270/* SerDes Lock Detect Control and Status Register */
271#define REG_SERDES_LOCK 0x1424
272#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
273#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
274
275/* MAC Control Register */
276#define REG_MAC_CTRL 0x1480
277#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
278#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
279#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
280#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
281#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
282#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
283#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
284#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
285#define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
286#define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
287#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
288#define MAC_CTRL_PRMLEN_MASK 0xf
289#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
290#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
291#define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
292#define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
293#define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
294#define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
295#define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
296#define MAC_CTRL_SPEED_MASK 0x300000
297#define MAC_CTRL_SPEED_1000 2
298#define MAC_CTRL_SPEED_10_100 1
299#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
300#define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
301#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
302#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
303#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
304#define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
305
306/* MAC IPG/IFG Control Register */
307#define REG_MAC_IPG_IFG 0x1484
308#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
309#define MAC_IPG_IFG_IPGT_MASK 0x7f
310#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
311#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
312#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
313#define MAC_IPG_IFG_IPGR1_MASK 0x7f
314#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
315#define MAC_IPG_IFG_IPGR2_MASK 0x7f
316
317/* MAC STATION ADDRESS */
318#define REG_MAC_STA_ADDR 0x1488
319
320/* Hash table for multicast address */
321#define REG_RX_HASH_TABLE 0x1490
322
323
324/* MAC Half-Duplex Control Register */
325#define REG_MAC_HALF_DUPLX_CTRL 0x1498
326#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
327#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
328#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
329#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
330#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
331#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
332#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
333#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
334#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
335#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
336#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
337#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
338
339/* Maximum Frame Length Control Register */
340#define REG_MTU 0x149c
341
342/* Wake-On-Lan control register */
343#define REG_WOL_CTRL 0x14a0
344#define WOL_PATTERN_EN 0x00000001
345#define WOL_PATTERN_PME_EN 0x00000002
346#define WOL_MAGIC_EN 0x00000004
347#define WOL_MAGIC_PME_EN 0x00000008
348#define WOL_LINK_CHG_EN 0x00000010
349#define WOL_LINK_CHG_PME_EN 0x00000020
350#define WOL_PATTERN_ST 0x00000100
351#define WOL_MAGIC_ST 0x00000200
352#define WOL_LINKCHG_ST 0x00000400
353#define WOL_CLK_SWITCH_EN 0x00008000
354#define WOL_PT0_EN 0x00010000
355#define WOL_PT1_EN 0x00020000
356#define WOL_PT2_EN 0x00040000
357#define WOL_PT3_EN 0x00080000
358#define WOL_PT4_EN 0x00100000
359#define WOL_PT5_EN 0x00200000
360#define WOL_PT6_EN 0x00400000
361/* WOL Length ( 2 DWORD ) */
362#define REG_WOL_PATTERN_LEN 0x14a4
363#define WOL_PT_LEN_MASK 0x7f
364#define WOL_PT0_LEN_SHIFT 0
365#define WOL_PT1_LEN_SHIFT 8
366#define WOL_PT2_LEN_SHIFT 16
367#define WOL_PT3_LEN_SHIFT 24
368#define WOL_PT4_LEN_SHIFT 0
369#define WOL_PT5_LEN_SHIFT 8
370#define WOL_PT6_LEN_SHIFT 16
371
372/* Internal SRAM Partition Register */
373#define REG_SRAM_TRD_ADDR 0x1518
374#define REG_SRAM_TRD_LEN 0x151C
375#define REG_SRAM_RXF_ADDR 0x1520
376#define REG_SRAM_RXF_LEN 0x1524
377#define REG_SRAM_TXF_ADDR 0x1528
378#define REG_SRAM_TXF_LEN 0x152C
379#define REG_SRAM_TCPH_ADDR 0x1530
380#define REG_SRAM_PKTH_ADDR 0x1532
381
382/* Load Ptr Register */
383#define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
384
385/*
386 * addresses of all descriptors, as well as the following descriptor
387 * control register, which triggers each function block to load the head
388 * pointer to prepare for the operation. This bit is then self-cleared
389 * after one cycle.
390 */
391
392/* Descriptor Control register */
393#define REG_RXF3_BASE_ADDR_HI 0x153C
394#define REG_DESC_BASE_ADDR_HI 0x1540
395#define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
396#define REG_HOST_RXF0_PAGE0_LO 0x1544
397#define REG_HOST_RXF0_PAGE1_LO 0x1548
398#define REG_TPD_BASE_ADDR_LO 0x154C
399#define REG_RXF1_BASE_ADDR_HI 0x1550
400#define REG_RXF2_BASE_ADDR_HI 0x1554
401#define REG_HOST_RXFPAGE_SIZE 0x1558
402#define REG_TPD_RING_SIZE 0x155C
403/* RSS about */
404#define REG_RSS_KEY0 0x14B0
405#define REG_RSS_KEY1 0x14B4
406#define REG_RSS_KEY2 0x14B8
407#define REG_RSS_KEY3 0x14BC
408#define REG_RSS_KEY4 0x14C0
409#define REG_RSS_KEY5 0x14C4
410#define REG_RSS_KEY6 0x14C8
411#define REG_RSS_KEY7 0x14CC
412#define REG_RSS_KEY8 0x14D0
413#define REG_RSS_KEY9 0x14D4
414#define REG_IDT_TABLE4 0x14E0
415#define REG_IDT_TABLE5 0x14E4
416#define REG_IDT_TABLE6 0x14E8
417#define REG_IDT_TABLE7 0x14EC
418#define REG_IDT_TABLE0 0x1560
419#define REG_IDT_TABLE1 0x1564
420#define REG_IDT_TABLE2 0x1568
421#define REG_IDT_TABLE3 0x156C
422#define REG_IDT_TABLE REG_IDT_TABLE0
423#define REG_RSS_HASH_VALUE 0x1570
424#define REG_RSS_HASH_FLAG 0x1574
425#define REG_BASE_CPU_NUMBER 0x157C
426
427
428/* TXQ Control Register */
429#define REG_TXQ_CTRL 0x1580
430#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
431#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
432#define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
433#define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
434#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
435#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
436
437/* Jumbo packet Threshold for task offload */
438#define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
439/* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
440#define TX_TX_EARLY_TH_MASK 0x7ff
441#define TX_TX_EARLY_TH_SHIFT 0
442
443
444/* RXQ Control Register */
445#define REG_RXQ_CTRL 0x15A0
446#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
447#define RXQ_CTRL_PBA_ALIGN_64 1
448#define RXQ_CTRL_PBA_ALIGN_128 2
449#define RXQ_CTRL_PBA_ALIGN_256 3
450#define RXQ_CTRL_Q1_EN 0x10
451#define RXQ_CTRL_Q2_EN 0x20
452#define RXQ_CTRL_Q3_EN 0x40
453#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
454#define RXQ_CTRL_HASH_TLEN_SHIFT 8
455#define RXQ_CTRL_HASH_TLEN_MASK 0xFF
456#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
457#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
458#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
459#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
460#define RXQ_CTRL_RSS_MODE_DISABLE 0
461#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
462#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
463#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
464#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
465#define RXQ_CTRL_HASH_ENABLE 0x20000000
466#define RXQ_CTRL_CUT_THRU_EN 0x40000000
467#define RXQ_CTRL_EN 0x80000000
468
469/* Rx jumbo packet threshold and rrd retirement timer */
470#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
471/*
472 * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
473 * When the packet length greater than or equal to this value, RXQ
474 * shall start cut-through forwarding of the received packet.
475 */
476#define RXQ_JMBOSZ_TH_MASK 0x7ff
477#define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
478#define RXQ_JMBO_LKAH_MASK 0xf
479#define RXQ_JMBO_LKAH_SHIFT 11
480
481/* RXF flow control register */
482#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
483#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
484#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
485#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
486#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
487
488
489/* DMA Engine Control Register */
490#define REG_DMA_CTRL 0x15C0
491#define DMA_CTRL_DMAR_IN_ORDER 0x1
492#define DMA_CTRL_DMAR_ENH_ORDER 0x2
493#define DMA_CTRL_DMAR_OUT_ORDER 0x4
494#define DMA_CTRL_RCB_VALUE 0x8
495#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
496#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
497#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
498#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
499#define DMA_CTRL_DMAR_REQ_PRI 0x400
500#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
501#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
502#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
503#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
504#define DMA_CTRL_TXCMB_EN 0x100000
505#define DMA_CTRL_RXCMB_EN 0x200000
506
507
508/* CMB/SMB Control Register */
509#define REG_SMB_STAT_TIMER 0x15C4
510#define REG_TRIG_RRD_THRESH 0x15CA
511#define REG_TRIG_TPD_THRESH 0x15C8
512#define REG_TRIG_TXTIMER 0x15CC
513#define REG_TRIG_RXTIMER 0x15CE
514
515/* HOST RXF Page 1,2,3 address */
516#define REG_HOST_RXF1_PAGE0_LO 0x15D0
517#define REG_HOST_RXF1_PAGE1_LO 0x15D4
518#define REG_HOST_RXF2_PAGE0_LO 0x15D8
519#define REG_HOST_RXF2_PAGE1_LO 0x15DC
520#define REG_HOST_RXF3_PAGE0_LO 0x15E0
521#define REG_HOST_RXF3_PAGE1_LO 0x15E4
522
523/* Mail box */
524#define REG_MB_RXF1_RADDR 0x15B4
525#define REG_MB_RXF2_RADDR 0x15B8
526#define REG_MB_RXF3_RADDR 0x15BC
527#define REG_MB_TPD_PROD_IDX 0x15F0
528
529/* RXF-Page 0-3 PageNo & Valid bit */
530#define REG_HOST_RXF0_PAGE0_VLD 0x15F4
531#define HOST_RXF_VALID 1
532#define HOST_RXF_PAGENO_SHIFT 1
533#define HOST_RXF_PAGENO_MASK 0x7F
534#define REG_HOST_RXF0_PAGE1_VLD 0x15F5
535#define REG_HOST_RXF1_PAGE0_VLD 0x15F6
536#define REG_HOST_RXF1_PAGE1_VLD 0x15F7
537#define REG_HOST_RXF2_PAGE0_VLD 0x15F8
538#define REG_HOST_RXF2_PAGE1_VLD 0x15F9
539#define REG_HOST_RXF3_PAGE0_VLD 0x15FA
540#define REG_HOST_RXF3_PAGE1_VLD 0x15FB
541
542/* Interrupt Status Register */
543#define REG_ISR 0x1600
544#define ISR_SMB 1
545#define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
546/*
547 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
548 * in Table 51 Selene Master Control Register (Offset 0x1400).
549 */
550#define ISR_MANUAL 4
551#define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
552#define ISR_HOST_RXF0_OV 0x10
553#define ISR_HOST_RXF1_OV 0x20
554#define ISR_HOST_RXF2_OV 0x40
555#define ISR_HOST_RXF3_OV 0x80
556#define ISR_TXF_UN 0x100
557#define ISR_RX0_PAGE_FULL 0x200
558#define ISR_DMAR_TO_RST 0x400
559#define ISR_DMAW_TO_RST 0x800
560#define ISR_GPHY 0x1000
561#define ISR_TX_CREDIT 0x2000
562#define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
563#define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
564#define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
565#define ISR_TX_DMA 0x40000
566#define ISR_RX_PKT_1 0x80000
567#define ISR_RX_PKT_2 0x100000
568#define ISR_RX_PKT_3 0x200000
569#define ISR_MAC_RX 0x400000
570#define ISR_MAC_TX 0x800000
571#define ISR_UR_DETECTED 0x1000000
572#define ISR_FERR_DETECTED 0x2000000
573#define ISR_NFERR_DETECTED 0x4000000
574#define ISR_CERR_DETECTED 0x8000000
575#define ISR_PHY_LINKDOWN 0x10000000
576#define ISR_DIS_INT 0x80000000
577
578
579/* Interrupt Mask Register */
580#define REG_IMR 0x1604
581
582
583#define IMR_NORMAL_MASK (\
584 ISR_SMB |\
585 ISR_TXF_UN |\
586 ISR_HW_RXF_OV |\
587 ISR_HOST_RXF0_OV|\
588 ISR_MANUAL |\
589 ISR_GPHY |\
590 ISR_GPHY_LPW |\
591 ISR_DMAR_TO_RST |\
592 ISR_DMAW_TO_RST |\
593 ISR_PHY_LINKDOWN|\
594 ISR_RX_PKT |\
595 ISR_TX_PKT)
596
597#define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
598#define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
599
600#define REG_MAC_RX_STATUS_BIN 0x1700
601#define REG_MAC_RX_STATUS_END 0x175c
602#define REG_MAC_TX_STATUS_BIN 0x1760
603#define REG_MAC_TX_STATUS_END 0x17c0
604
605/* Hardware Offset Register */
606#define REG_HOST_RXF0_PAGEOFF 0x1800
607#define REG_TPD_CONS_IDX 0x1804
608#define REG_HOST_RXF1_PAGEOFF 0x1808
609#define REG_HOST_RXF2_PAGEOFF 0x180C
610#define REG_HOST_RXF3_PAGEOFF 0x1810
611
612/* RXF-Page 0-3 Offset DMA Address */
613#define REG_HOST_RXF0_MB0_LO 0x1820
614#define REG_HOST_RXF0_MB1_LO 0x1824
615#define REG_HOST_RXF1_MB0_LO 0x1828
616#define REG_HOST_RXF1_MB1_LO 0x182C
617#define REG_HOST_RXF2_MB0_LO 0x1830
618#define REG_HOST_RXF2_MB1_LO 0x1834
619#define REG_HOST_RXF3_MB0_LO 0x1838
620#define REG_HOST_RXF3_MB1_LO 0x183C
621
622/* Tpd CMB DMA Address */
623#define REG_HOST_TX_CMB_LO 0x1840
624#define REG_HOST_SMB_ADDR_LO 0x1844
625
626/* DEBUG ADDR */
627#define REG_DEBUG_DATA0 0x1900
628#define REG_DEBUG_DATA1 0x1904
629
630/***************************** MII definition ***************************************/
631/* PHY Common Register */
632#define MII_AT001_PSCR 0x10
633#define MII_AT001_PSSR 0x11
634#define MII_INT_CTRL 0x12
635#define MII_INT_STATUS 0x13
636#define MII_SMARTSPEED 0x14
637#define MII_LBRERROR 0x18
638#define MII_RESV2 0x1a
639
640#define MII_DBG_ADDR 0x1D
641#define MII_DBG_DATA 0x1E
642
643/* Autoneg Advertisement Register */
644#define MII_AR_DEFAULT_CAP_MASK 0
645
646/* 1000BASE-T Control Register */
647#define MII_AT001_CR_1000T_SPEED_MASK \
648 (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
649#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK
650
651/* AT001 PHY Specific Control Register */
652#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
653#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
654#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
655#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
656#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
657 * 0=CLK125 toggling
658 */
659#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
660/* Manual MDI configuration */
661#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
662#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
663 * 100BASE-TX/10BASE-T:
664 * MDI Mode
665 */
666#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
667 * all speeds.
668 */
669#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
670/* 1=Enable Extended 10BASE-T distance
671 * (Lower 10BASE-T RX Threshold)
672 * 0=Normal 10BASE-T RX Threshold */
673#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
674/* 1=5-Bit interface in 100BASE-TX
675 * 0=MII interface in 100BASE-TX */
676#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
677#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
678#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
679#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
680#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
681#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
682/* AT001 PHY Specific Status Register */
683#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
684#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
685#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
686#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
687#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
688#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
689
690#endif /*_ATHL1E_HW_H_*/
diff --git a/drivers/net/atl1e/atl1e_main.c b/drivers/net/atl1e/atl1e_main.c
deleted file mode 100644
index d8d411998fa3..000000000000
--- a/drivers/net/atl1e/atl1e_main.c
+++ /dev/null
@@ -1,2558 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1e.h"
23
24#define DRV_VERSION "1.0.0.7-NAPI"
25
26char atl1e_driver_name[] = "ATL1E";
27char atl1e_driver_version[] = DRV_VERSION;
28#define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29/*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38static DEFINE_PCI_DEVICE_TABLE(atl1e_pci_tbl) = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
41 /* required last entry */
42 { 0 }
43};
44MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
45
46MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
47MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48MODULE_LICENSE("GPL");
49MODULE_VERSION(DRV_VERSION);
50
51static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
52
53static const u16
54atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
55{
56 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
57 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
58 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
59 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
60};
61
62static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
63{
64 REG_RXF0_BASE_ADDR_HI,
65 REG_RXF1_BASE_ADDR_HI,
66 REG_RXF2_BASE_ADDR_HI,
67 REG_RXF3_BASE_ADDR_HI
68};
69
70static const u16
71atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
72{
73 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
74 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
75 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
76 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
77};
78
79static const u16
80atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
81{
82 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
83 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
84 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
85 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
86};
87
88static const u16 atl1e_pay_load_size[] = {
89 128, 256, 512, 1024, 2048, 4096,
90};
91
92/*
93 * atl1e_irq_enable - Enable default interrupt generation settings
94 * @adapter: board private structure
95 */
96static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
97{
98 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
102 }
103}
104
105/*
106 * atl1e_irq_disable - Mask off interrupt generation on the NIC
107 * @adapter: board private structure
108 */
109static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
110{
111 atomic_inc(&adapter->irq_sem);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
114 synchronize_irq(adapter->pdev->irq);
115}
116
117/*
118 * atl1e_irq_reset - reset interrupt confiure on the NIC
119 * @adapter: board private structure
120 */
121static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
122{
123 atomic_set(&adapter->irq_sem, 0);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
127}
128
129/*
130 * atl1e_phy_config - Timer Call-back
131 * @data: pointer to netdev cast into an unsigned long
132 */
133static void atl1e_phy_config(unsigned long data)
134{
135 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
136 struct atl1e_hw *hw = &adapter->hw;
137 unsigned long flags;
138
139 spin_lock_irqsave(&adapter->mdio_lock, flags);
140 atl1e_restart_autoneg(hw);
141 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
142}
143
144void atl1e_reinit_locked(struct atl1e_adapter *adapter)
145{
146
147 WARN_ON(in_interrupt());
148 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
149 msleep(1);
150 atl1e_down(adapter);
151 atl1e_up(adapter);
152 clear_bit(__AT_RESETTING, &adapter->flags);
153}
154
155static void atl1e_reset_task(struct work_struct *work)
156{
157 struct atl1e_adapter *adapter;
158 adapter = container_of(work, struct atl1e_adapter, reset_task);
159
160 atl1e_reinit_locked(adapter);
161}
162
163static int atl1e_check_link(struct atl1e_adapter *adapter)
164{
165 struct atl1e_hw *hw = &adapter->hw;
166 struct net_device *netdev = adapter->netdev;
167 int err = 0;
168 u16 speed, duplex, phy_data;
169
170 /* MII_BMSR must read twice */
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 if ((phy_data & BMSR_LSTATUS) == 0) {
174 /* link down */
175 if (netif_carrier_ok(netdev)) { /* old link state: Up */
176 u32 value;
177 /* disable rx */
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
179 value &= ~MAC_CTRL_RX_EN;
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
181 adapter->link_speed = SPEED_0;
182 netif_carrier_off(netdev);
183 netif_stop_queue(netdev);
184 }
185 } else {
186 /* Link Up */
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
188 if (unlikely(err))
189 return err;
190
191 /* link result is our setting */
192 if (adapter->link_speed != speed ||
193 adapter->link_duplex != duplex) {
194 adapter->link_speed = speed;
195 adapter->link_duplex = duplex;
196 atl1e_setup_mac_ctrl(adapter);
197 netdev_info(netdev,
198 "NIC Link is Up <%d Mbps %s Duplex>\n",
199 adapter->link_speed,
200 adapter->link_duplex == FULL_DUPLEX ?
201 "Full" : "Half");
202 }
203
204 if (!netif_carrier_ok(netdev)) {
205 /* Link down -> Up */
206 netif_carrier_on(netdev);
207 netif_wake_queue(netdev);
208 }
209 }
210 return 0;
211}
212
213/*
214 * atl1e_link_chg_task - deal with link change event Out of interrupt context
215 * @netdev: network interface device structure
216 */
217static void atl1e_link_chg_task(struct work_struct *work)
218{
219 struct atl1e_adapter *adapter;
220 unsigned long flags;
221
222 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
223 spin_lock_irqsave(&adapter->mdio_lock, flags);
224 atl1e_check_link(adapter);
225 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
226}
227
228static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
229{
230 struct net_device *netdev = adapter->netdev;
231 u16 phy_data = 0;
232 u16 link_up = 0;
233
234 spin_lock(&adapter->mdio_lock);
235 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
236 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
237 spin_unlock(&adapter->mdio_lock);
238 link_up = phy_data & BMSR_LSTATUS;
239 /* notify upper layer link down ASAP */
240 if (!link_up) {
241 if (netif_carrier_ok(netdev)) {
242 /* old link state: Up */
243 netdev_info(netdev, "NIC Link is Down\n");
244 adapter->link_speed = SPEED_0;
245 netif_stop_queue(netdev);
246 }
247 }
248 schedule_work(&adapter->link_chg_task);
249}
250
251static void atl1e_del_timer(struct atl1e_adapter *adapter)
252{
253 del_timer_sync(&adapter->phy_config_timer);
254}
255
256static void atl1e_cancel_work(struct atl1e_adapter *adapter)
257{
258 cancel_work_sync(&adapter->reset_task);
259 cancel_work_sync(&adapter->link_chg_task);
260}
261
262/*
263 * atl1e_tx_timeout - Respond to a Tx Hang
264 * @netdev: network interface device structure
265 */
266static void atl1e_tx_timeout(struct net_device *netdev)
267{
268 struct atl1e_adapter *adapter = netdev_priv(netdev);
269
270 /* Do the reset outside of interrupt context */
271 schedule_work(&adapter->reset_task);
272}
273
274/*
275 * atl1e_set_multi - Multicast and Promiscuous mode set
276 * @netdev: network interface device structure
277 *
278 * The set_multi entry point is called whenever the multicast address
279 * list or the network interface flags are updated. This routine is
280 * responsible for configuring the hardware for proper multicast,
281 * promiscuous mode, and all-multi behavior.
282 */
283static void atl1e_set_multi(struct net_device *netdev)
284{
285 struct atl1e_adapter *adapter = netdev_priv(netdev);
286 struct atl1e_hw *hw = &adapter->hw;
287 struct netdev_hw_addr *ha;
288 u32 mac_ctrl_data = 0;
289 u32 hash_value;
290
291 /* Check for Promiscuous and All Multicast modes */
292 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
293
294 if (netdev->flags & IFF_PROMISC) {
295 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
296 } else if (netdev->flags & IFF_ALLMULTI) {
297 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
298 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
299 } else {
300 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
301 }
302
303 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
304
305 /* clear the old settings from the multicast hash table */
306 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
307 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
308
309 /* comoute mc addresses' hash value ,and put it into hash table */
310 netdev_for_each_mc_addr(ha, netdev) {
311 hash_value = atl1e_hash_mc_addr(hw, ha->addr);
312 atl1e_hash_set(hw, hash_value);
313 }
314}
315
316static void __atl1e_vlan_mode(u32 features, u32 *mac_ctrl_data)
317{
318 if (features & NETIF_F_HW_VLAN_RX) {
319 /* enable VLAN tag insert/strip */
320 *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
321 } else {
322 /* disable VLAN tag insert/strip */
323 *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
324 }
325}
326
327static void atl1e_vlan_mode(struct net_device *netdev, u32 features)
328{
329 struct atl1e_adapter *adapter = netdev_priv(netdev);
330 u32 mac_ctrl_data = 0;
331
332 netdev_dbg(adapter->netdev, "%s\n", __func__);
333
334 atl1e_irq_disable(adapter);
335 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
336 __atl1e_vlan_mode(features, &mac_ctrl_data);
337 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
338 atl1e_irq_enable(adapter);
339}
340
341static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
342{
343 netdev_dbg(adapter->netdev, "%s\n", __func__);
344 atl1e_vlan_mode(adapter->netdev, adapter->netdev->features);
345}
346
347/*
348 * atl1e_set_mac - Change the Ethernet Address of the NIC
349 * @netdev: network interface device structure
350 * @p: pointer to an address structure
351 *
352 * Returns 0 on success, negative on failure
353 */
354static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
355{
356 struct atl1e_adapter *adapter = netdev_priv(netdev);
357 struct sockaddr *addr = p;
358
359 if (!is_valid_ether_addr(addr->sa_data))
360 return -EADDRNOTAVAIL;
361
362 if (netif_running(netdev))
363 return -EBUSY;
364
365 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
366 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
367
368 atl1e_hw_set_mac_addr(&adapter->hw);
369
370 return 0;
371}
372
373static u32 atl1e_fix_features(struct net_device *netdev, u32 features)
374{
375 /*
376 * Since there is no support for separate rx/tx vlan accel
377 * enable/disable make sure tx flag is always in same state as rx.
378 */
379 if (features & NETIF_F_HW_VLAN_RX)
380 features |= NETIF_F_HW_VLAN_TX;
381 else
382 features &= ~NETIF_F_HW_VLAN_TX;
383
384 return features;
385}
386
387static int atl1e_set_features(struct net_device *netdev, u32 features)
388{
389 u32 changed = netdev->features ^ features;
390
391 if (changed & NETIF_F_HW_VLAN_RX)
392 atl1e_vlan_mode(netdev, features);
393
394 return 0;
395}
396
397/*
398 * atl1e_change_mtu - Change the Maximum Transfer Unit
399 * @netdev: network interface device structure
400 * @new_mtu: new value for maximum frame size
401 *
402 * Returns 0 on success, negative on failure
403 */
404static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
405{
406 struct atl1e_adapter *adapter = netdev_priv(netdev);
407 int old_mtu = netdev->mtu;
408 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
409
410 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
411 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
412 netdev_warn(adapter->netdev, "invalid MTU setting\n");
413 return -EINVAL;
414 }
415 /* set MTU */
416 if (old_mtu != new_mtu && netif_running(netdev)) {
417 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
418 msleep(1);
419 netdev->mtu = new_mtu;
420 adapter->hw.max_frame_size = new_mtu;
421 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
422 atl1e_down(adapter);
423 atl1e_up(adapter);
424 clear_bit(__AT_RESETTING, &adapter->flags);
425 }
426 return 0;
427}
428
429/*
430 * caller should hold mdio_lock
431 */
432static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
433{
434 struct atl1e_adapter *adapter = netdev_priv(netdev);
435 u16 result;
436
437 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
438 return result;
439}
440
441static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
442 int reg_num, int val)
443{
444 struct atl1e_adapter *adapter = netdev_priv(netdev);
445
446 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
447}
448
449/*
450 * atl1e_mii_ioctl -
451 * @netdev:
452 * @ifreq:
453 * @cmd:
454 */
455static int atl1e_mii_ioctl(struct net_device *netdev,
456 struct ifreq *ifr, int cmd)
457{
458 struct atl1e_adapter *adapter = netdev_priv(netdev);
459 struct mii_ioctl_data *data = if_mii(ifr);
460 unsigned long flags;
461 int retval = 0;
462
463 if (!netif_running(netdev))
464 return -EINVAL;
465
466 spin_lock_irqsave(&adapter->mdio_lock, flags);
467 switch (cmd) {
468 case SIOCGMIIPHY:
469 data->phy_id = 0;
470 break;
471
472 case SIOCGMIIREG:
473 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
474 &data->val_out)) {
475 retval = -EIO;
476 goto out;
477 }
478 break;
479
480 case SIOCSMIIREG:
481 if (data->reg_num & ~(0x1F)) {
482 retval = -EFAULT;
483 goto out;
484 }
485
486 netdev_dbg(adapter->netdev, "<atl1e_mii_ioctl> write %x %x\n",
487 data->reg_num, data->val_in);
488 if (atl1e_write_phy_reg(&adapter->hw,
489 data->reg_num, data->val_in)) {
490 retval = -EIO;
491 goto out;
492 }
493 break;
494
495 default:
496 retval = -EOPNOTSUPP;
497 break;
498 }
499out:
500 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
501 return retval;
502
503}
504
505/*
506 * atl1e_ioctl -
507 * @netdev:
508 * @ifreq:
509 * @cmd:
510 */
511static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
512{
513 switch (cmd) {
514 case SIOCGMIIPHY:
515 case SIOCGMIIREG:
516 case SIOCSMIIREG:
517 return atl1e_mii_ioctl(netdev, ifr, cmd);
518 default:
519 return -EOPNOTSUPP;
520 }
521}
522
523static void atl1e_setup_pcicmd(struct pci_dev *pdev)
524{
525 u16 cmd;
526
527 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
528 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
529 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
530 pci_write_config_word(pdev, PCI_COMMAND, cmd);
531
532 /*
533 * some motherboards BIOS(PXE/EFI) driver may set PME
534 * while they transfer control to OS (Windows/Linux)
535 * so we should clear this bit before NIC work normally
536 */
537 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
538 msleep(1);
539}
540
541/*
542 * atl1e_alloc_queues - Allocate memory for all rings
543 * @adapter: board private structure to initialize
544 *
545 */
546static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
547{
548 return 0;
549}
550
551/*
552 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
553 * @adapter: board private structure to initialize
554 *
555 * atl1e_sw_init initializes the Adapter private data structure.
556 * Fields are initialized based on PCI device information and
557 * OS network device settings (MTU size).
558 */
559static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
560{
561 struct atl1e_hw *hw = &adapter->hw;
562 struct pci_dev *pdev = adapter->pdev;
563 u32 phy_status_data = 0;
564
565 adapter->wol = 0;
566 adapter->link_speed = SPEED_0; /* hardware init */
567 adapter->link_duplex = FULL_DUPLEX;
568 adapter->num_rx_queues = 1;
569
570 /* PCI config space info */
571 hw->vendor_id = pdev->vendor;
572 hw->device_id = pdev->device;
573 hw->subsystem_vendor_id = pdev->subsystem_vendor;
574 hw->subsystem_id = pdev->subsystem_device;
575 hw->revision_id = pdev->revision;
576
577 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
578
579 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
580 /* nic type */
581 if (hw->revision_id >= 0xF0) {
582 hw->nic_type = athr_l2e_revB;
583 } else {
584 if (phy_status_data & PHY_STATUS_100M)
585 hw->nic_type = athr_l1e;
586 else
587 hw->nic_type = athr_l2e_revA;
588 }
589
590 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
591
592 if (phy_status_data & PHY_STATUS_EMI_CA)
593 hw->emi_ca = true;
594 else
595 hw->emi_ca = false;
596
597 hw->phy_configured = false;
598 hw->preamble_len = 7;
599 hw->max_frame_size = adapter->netdev->mtu;
600 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
601 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
602
603 hw->rrs_type = atl1e_rrs_disable;
604 hw->indirect_tab = 0;
605 hw->base_cpu = 0;
606
607 /* need confirm */
608
609 hw->ict = 50000; /* 100ms */
610 hw->smb_timer = 200000; /* 200ms */
611 hw->tpd_burst = 5;
612 hw->rrd_thresh = 1;
613 hw->tpd_thresh = adapter->tx_ring.count / 2;
614 hw->rx_count_down = 4; /* 2us resolution */
615 hw->tx_count_down = hw->imt * 4 / 3;
616 hw->dmar_block = atl1e_dma_req_1024;
617 hw->dmaw_block = atl1e_dma_req_1024;
618 hw->dmar_dly_cnt = 15;
619 hw->dmaw_dly_cnt = 4;
620
621 if (atl1e_alloc_queues(adapter)) {
622 netdev_err(adapter->netdev, "Unable to allocate memory for queues\n");
623 return -ENOMEM;
624 }
625
626 atomic_set(&adapter->irq_sem, 1);
627 spin_lock_init(&adapter->mdio_lock);
628 spin_lock_init(&adapter->tx_lock);
629
630 set_bit(__AT_DOWN, &adapter->flags);
631
632 return 0;
633}
634
635/*
636 * atl1e_clean_tx_ring - Free Tx-skb
637 * @adapter: board private structure
638 */
639static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
640{
641 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
642 &adapter->tx_ring;
643 struct atl1e_tx_buffer *tx_buffer = NULL;
644 struct pci_dev *pdev = adapter->pdev;
645 u16 index, ring_count;
646
647 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
648 return;
649
650 ring_count = tx_ring->count;
651 /* first unmmap dma */
652 for (index = 0; index < ring_count; index++) {
653 tx_buffer = &tx_ring->tx_buffer[index];
654 if (tx_buffer->dma) {
655 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
656 pci_unmap_single(pdev, tx_buffer->dma,
657 tx_buffer->length, PCI_DMA_TODEVICE);
658 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
659 pci_unmap_page(pdev, tx_buffer->dma,
660 tx_buffer->length, PCI_DMA_TODEVICE);
661 tx_buffer->dma = 0;
662 }
663 }
664 /* second free skb */
665 for (index = 0; index < ring_count; index++) {
666 tx_buffer = &tx_ring->tx_buffer[index];
667 if (tx_buffer->skb) {
668 dev_kfree_skb_any(tx_buffer->skb);
669 tx_buffer->skb = NULL;
670 }
671 }
672 /* Zero out Tx-buffers */
673 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
674 ring_count);
675 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
676 ring_count);
677}
678
679/*
680 * atl1e_clean_rx_ring - Free rx-reservation skbs
681 * @adapter: board private structure
682 */
683static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
684{
685 struct atl1e_rx_ring *rx_ring =
686 (struct atl1e_rx_ring *)&adapter->rx_ring;
687 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
688 u16 i, j;
689
690
691 if (adapter->ring_vir_addr == NULL)
692 return;
693 /* Zero out the descriptor ring */
694 for (i = 0; i < adapter->num_rx_queues; i++) {
695 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
696 if (rx_page_desc[i].rx_page[j].addr != NULL) {
697 memset(rx_page_desc[i].rx_page[j].addr, 0,
698 rx_ring->real_page_size);
699 }
700 }
701 }
702}
703
704static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
705{
706 *ring_size = ((u32)(adapter->tx_ring.count *
707 sizeof(struct atl1e_tpd_desc) + 7
708 /* tx ring, qword align */
709 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
710 adapter->num_rx_queues + 31
711 /* rx ring, 32 bytes align */
712 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
713 sizeof(u32) + 3));
714 /* tx, rx cmd, dword align */
715}
716
717static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
718{
719 struct atl1e_rx_ring *rx_ring = NULL;
720
721 rx_ring = &adapter->rx_ring;
722
723 rx_ring->real_page_size = adapter->rx_ring.page_size
724 + adapter->hw.max_frame_size
725 + ETH_HLEN + VLAN_HLEN
726 + ETH_FCS_LEN;
727 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
728 atl1e_cal_ring_size(adapter, &adapter->ring_size);
729
730 adapter->ring_vir_addr = NULL;
731 adapter->rx_ring.desc = NULL;
732 rwlock_init(&adapter->tx_ring.tx_lock);
733}
734
735/*
736 * Read / Write Ptr Initialize:
737 */
738static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
739{
740 struct atl1e_tx_ring *tx_ring = NULL;
741 struct atl1e_rx_ring *rx_ring = NULL;
742 struct atl1e_rx_page_desc *rx_page_desc = NULL;
743 int i, j;
744
745 tx_ring = &adapter->tx_ring;
746 rx_ring = &adapter->rx_ring;
747 rx_page_desc = rx_ring->rx_page_desc;
748
749 tx_ring->next_to_use = 0;
750 atomic_set(&tx_ring->next_to_clean, 0);
751
752 for (i = 0; i < adapter->num_rx_queues; i++) {
753 rx_page_desc[i].rx_using = 0;
754 rx_page_desc[i].rx_nxseq = 0;
755 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
756 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
757 rx_page_desc[i].rx_page[j].read_offset = 0;
758 }
759 }
760}
761
762/*
763 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
764 * @adapter: board private structure
765 *
766 * Free all transmit software resources
767 */
768static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
769{
770 struct pci_dev *pdev = adapter->pdev;
771
772 atl1e_clean_tx_ring(adapter);
773 atl1e_clean_rx_ring(adapter);
774
775 if (adapter->ring_vir_addr) {
776 pci_free_consistent(pdev, adapter->ring_size,
777 adapter->ring_vir_addr, adapter->ring_dma);
778 adapter->ring_vir_addr = NULL;
779 }
780
781 if (adapter->tx_ring.tx_buffer) {
782 kfree(adapter->tx_ring.tx_buffer);
783 adapter->tx_ring.tx_buffer = NULL;
784 }
785}
786
787/*
788 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
789 * @adapter: board private structure
790 *
791 * Return 0 on success, negative on failure
792 */
793static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
794{
795 struct pci_dev *pdev = adapter->pdev;
796 struct atl1e_tx_ring *tx_ring;
797 struct atl1e_rx_ring *rx_ring;
798 struct atl1e_rx_page_desc *rx_page_desc;
799 int size, i, j;
800 u32 offset = 0;
801 int err = 0;
802
803 if (adapter->ring_vir_addr != NULL)
804 return 0; /* alloced already */
805
806 tx_ring = &adapter->tx_ring;
807 rx_ring = &adapter->rx_ring;
808
809 /* real ring DMA buffer */
810
811 size = adapter->ring_size;
812 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
813 adapter->ring_size, &adapter->ring_dma);
814
815 if (adapter->ring_vir_addr == NULL) {
816 netdev_err(adapter->netdev,
817 "pci_alloc_consistent failed, size = D%d\n", size);
818 return -ENOMEM;
819 }
820
821 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
822
823 rx_page_desc = rx_ring->rx_page_desc;
824
825 /* Init TPD Ring */
826 tx_ring->dma = roundup(adapter->ring_dma, 8);
827 offset = tx_ring->dma - adapter->ring_dma;
828 tx_ring->desc = adapter->ring_vir_addr + offset;
829 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
830 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
831 if (tx_ring->tx_buffer == NULL) {
832 netdev_err(adapter->netdev, "kzalloc failed, size = D%d\n",
833 size);
834 err = -ENOMEM;
835 goto failed;
836 }
837
838 /* Init RXF-Pages */
839 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
840 offset = roundup(offset, 32);
841
842 for (i = 0; i < adapter->num_rx_queues; i++) {
843 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
844 rx_page_desc[i].rx_page[j].dma =
845 adapter->ring_dma + offset;
846 rx_page_desc[i].rx_page[j].addr =
847 adapter->ring_vir_addr + offset;
848 offset += rx_ring->real_page_size;
849 }
850 }
851
852 /* Init CMB dma address */
853 tx_ring->cmb_dma = adapter->ring_dma + offset;
854 tx_ring->cmb = adapter->ring_vir_addr + offset;
855 offset += sizeof(u32);
856
857 for (i = 0; i < adapter->num_rx_queues; i++) {
858 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
859 rx_page_desc[i].rx_page[j].write_offset_dma =
860 adapter->ring_dma + offset;
861 rx_page_desc[i].rx_page[j].write_offset_addr =
862 adapter->ring_vir_addr + offset;
863 offset += sizeof(u32);
864 }
865 }
866
867 if (unlikely(offset > adapter->ring_size)) {
868 netdev_err(adapter->netdev, "offset(%d) > ring size(%d) !!\n",
869 offset, adapter->ring_size);
870 err = -1;
871 goto failed;
872 }
873
874 return 0;
875failed:
876 if (adapter->ring_vir_addr != NULL) {
877 pci_free_consistent(pdev, adapter->ring_size,
878 adapter->ring_vir_addr, adapter->ring_dma);
879 adapter->ring_vir_addr = NULL;
880 }
881 return err;
882}
883
884static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
885{
886
887 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
888 struct atl1e_rx_ring *rx_ring =
889 (struct atl1e_rx_ring *)&adapter->rx_ring;
890 struct atl1e_tx_ring *tx_ring =
891 (struct atl1e_tx_ring *)&adapter->tx_ring;
892 struct atl1e_rx_page_desc *rx_page_desc = NULL;
893 int i, j;
894
895 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
896 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
897 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
898 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
899 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
900 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
901 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
902
903 rx_page_desc = rx_ring->rx_page_desc;
904 /* RXF Page Physical address / Page Length */
905 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
906 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
907 (u32)((adapter->ring_dma &
908 AT_DMA_HI_ADDR_MASK) >> 32));
909 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
910 u32 page_phy_addr;
911 u32 offset_phy_addr;
912
913 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
914 offset_phy_addr =
915 rx_page_desc[i].rx_page[j].write_offset_dma;
916
917 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
918 page_phy_addr & AT_DMA_LO_ADDR_MASK);
919 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
920 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
921 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
922 }
923 }
924 /* Page Length */
925 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
926 /* Load all of base address above */
927 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
928}
929
930static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
931{
932 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
933 u32 dev_ctrl_data = 0;
934 u32 max_pay_load = 0;
935 u32 jumbo_thresh = 0;
936 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
937
938 /* configure TXQ param */
939 if (hw->nic_type != athr_l2e_revB) {
940 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
941 if (hw->max_frame_size <= 1500) {
942 jumbo_thresh = hw->max_frame_size + extra_size;
943 } else if (hw->max_frame_size < 6*1024) {
944 jumbo_thresh =
945 (hw->max_frame_size + extra_size) * 2 / 3;
946 } else {
947 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
948 }
949 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
950 }
951
952 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
953
954 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
955 DEVICE_CTRL_MAX_PAYLOAD_MASK;
956
957 hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
958
959 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
960 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
961 hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
962
963 if (hw->nic_type != athr_l2e_revB)
964 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
965 atl1e_pay_load_size[hw->dmar_block]);
966 /* enable TXQ */
967 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
968 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
969 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
970 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
971}
972
973static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
974{
975 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
976 u32 rxf_len = 0;
977 u32 rxf_low = 0;
978 u32 rxf_high = 0;
979 u32 rxf_thresh_data = 0;
980 u32 rxq_ctrl_data = 0;
981
982 if (hw->nic_type != athr_l2e_revB) {
983 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
984 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
985 RXQ_JMBOSZ_TH_SHIFT |
986 (1 & RXQ_JMBO_LKAH_MASK) <<
987 RXQ_JMBO_LKAH_SHIFT));
988
989 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
990 rxf_high = rxf_len * 4 / 5;
991 rxf_low = rxf_len / 5;
992 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
993 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
994 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
995 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
996
997 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
998 }
999
1000 /* RRS */
1001 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1002 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1003
1004 if (hw->rrs_type & atl1e_rrs_ipv4)
1005 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
1006
1007 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
1008 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
1009
1010 if (hw->rrs_type & atl1e_rrs_ipv6)
1011 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
1012
1013 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1014 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1015
1016 if (hw->rrs_type != atl1e_rrs_disable)
1017 rxq_ctrl_data |=
1018 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1019
1020 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1021 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1022
1023 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1024}
1025
1026static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1027{
1028 struct atl1e_hw *hw = &adapter->hw;
1029 u32 dma_ctrl_data = 0;
1030
1031 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1032 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1033 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1034 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1035 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1036 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1037 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1038 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1039 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1040 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1041
1042 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1043}
1044
1045static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1046{
1047 u32 value;
1048 struct atl1e_hw *hw = &adapter->hw;
1049 struct net_device *netdev = adapter->netdev;
1050
1051 /* Config MAC CTRL Register */
1052 value = MAC_CTRL_TX_EN |
1053 MAC_CTRL_RX_EN ;
1054
1055 if (FULL_DUPLEX == adapter->link_duplex)
1056 value |= MAC_CTRL_DUPLX;
1057
1058 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1059 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1060 MAC_CTRL_SPEED_SHIFT);
1061 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1062
1063 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1064 value |= (((u32)adapter->hw.preamble_len &
1065 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1066
1067 __atl1e_vlan_mode(netdev->features, &value);
1068
1069 value |= MAC_CTRL_BC_EN;
1070 if (netdev->flags & IFF_PROMISC)
1071 value |= MAC_CTRL_PROMIS_EN;
1072 if (netdev->flags & IFF_ALLMULTI)
1073 value |= MAC_CTRL_MC_ALL_EN;
1074
1075 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1076}
1077
1078/*
1079 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1080 * @adapter: board private structure
1081 *
1082 * Configure the Tx /Rx unit of the MAC after a reset.
1083 */
1084static int atl1e_configure(struct atl1e_adapter *adapter)
1085{
1086 struct atl1e_hw *hw = &adapter->hw;
1087
1088 u32 intr_status_data = 0;
1089
1090 /* clear interrupt status */
1091 AT_WRITE_REG(hw, REG_ISR, ~0);
1092
1093 /* 1. set MAC Address */
1094 atl1e_hw_set_mac_addr(hw);
1095
1096 /* 2. Init the Multicast HASH table done by set_muti */
1097
1098 /* 3. Clear any WOL status */
1099 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1100
1101 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1102 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1103 * High 32bits memory */
1104 atl1e_configure_des_ring(adapter);
1105
1106 /* 5. set Interrupt Moderator Timer */
1107 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1108 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1109 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1110 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1111
1112 /* 6. rx/tx threshold to trig interrupt */
1113 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1114 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1115 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1116 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1117
1118 /* 7. set Interrupt Clear Timer */
1119 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1120
1121 /* 8. set MTU */
1122 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1123 VLAN_HLEN + ETH_FCS_LEN);
1124
1125 /* 9. config TXQ early tx threshold */
1126 atl1e_configure_tx(adapter);
1127
1128 /* 10. config RXQ */
1129 atl1e_configure_rx(adapter);
1130
1131 /* 11. config DMA Engine */
1132 atl1e_configure_dma(adapter);
1133
1134 /* 12. smb timer to trig interrupt */
1135 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1136
1137 intr_status_data = AT_READ_REG(hw, REG_ISR);
1138 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1139 netdev_err(adapter->netdev,
1140 "atl1e_configure failed, PCIE phy link down\n");
1141 return -1;
1142 }
1143
1144 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1145 return 0;
1146}
1147
1148/*
1149 * atl1e_get_stats - Get System Network Statistics
1150 * @netdev: network interface device structure
1151 *
1152 * Returns the address of the device statistics structure.
1153 * The statistics are actually updated from the timer callback.
1154 */
1155static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1156{
1157 struct atl1e_adapter *adapter = netdev_priv(netdev);
1158 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1159 struct net_device_stats *net_stats = &netdev->stats;
1160
1161 net_stats->rx_packets = hw_stats->rx_ok;
1162 net_stats->tx_packets = hw_stats->tx_ok;
1163 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1164 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1165 net_stats->multicast = hw_stats->rx_mcast;
1166 net_stats->collisions = hw_stats->tx_1_col +
1167 hw_stats->tx_2_col * 2 +
1168 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1169
1170 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1171 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1172 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1173 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1174 net_stats->rx_length_errors = hw_stats->rx_len_err;
1175 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1176 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1177 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1178
1179 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1180
1181 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1182 hw_stats->tx_underrun + hw_stats->tx_trunc;
1183 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1184 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1185 net_stats->tx_window_errors = hw_stats->tx_late_col;
1186
1187 return net_stats;
1188}
1189
1190static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1191{
1192 u16 hw_reg_addr = 0;
1193 unsigned long *stats_item = NULL;
1194
1195 /* update rx status */
1196 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1197 stats_item = &adapter->hw_stats.rx_ok;
1198 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1199 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1200 stats_item++;
1201 hw_reg_addr += 4;
1202 }
1203 /* update tx status */
1204 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1205 stats_item = &adapter->hw_stats.tx_ok;
1206 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1207 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1208 stats_item++;
1209 hw_reg_addr += 4;
1210 }
1211}
1212
1213static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1214{
1215 u16 phy_data;
1216
1217 spin_lock(&adapter->mdio_lock);
1218 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1219 spin_unlock(&adapter->mdio_lock);
1220}
1221
1222static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1223{
1224 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1225 &adapter->tx_ring;
1226 struct atl1e_tx_buffer *tx_buffer = NULL;
1227 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1228 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1229
1230 while (next_to_clean != hw_next_to_clean) {
1231 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1232 if (tx_buffer->dma) {
1233 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
1234 pci_unmap_single(adapter->pdev, tx_buffer->dma,
1235 tx_buffer->length, PCI_DMA_TODEVICE);
1236 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
1237 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1238 tx_buffer->length, PCI_DMA_TODEVICE);
1239 tx_buffer->dma = 0;
1240 }
1241
1242 if (tx_buffer->skb) {
1243 dev_kfree_skb_irq(tx_buffer->skb);
1244 tx_buffer->skb = NULL;
1245 }
1246
1247 if (++next_to_clean == tx_ring->count)
1248 next_to_clean = 0;
1249 }
1250
1251 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1252
1253 if (netif_queue_stopped(adapter->netdev) &&
1254 netif_carrier_ok(adapter->netdev)) {
1255 netif_wake_queue(adapter->netdev);
1256 }
1257
1258 return true;
1259}
1260
1261/*
1262 * atl1e_intr - Interrupt Handler
1263 * @irq: interrupt number
1264 * @data: pointer to a network interface device structure
1265 * @pt_regs: CPU registers structure
1266 */
1267static irqreturn_t atl1e_intr(int irq, void *data)
1268{
1269 struct net_device *netdev = data;
1270 struct atl1e_adapter *adapter = netdev_priv(netdev);
1271 struct atl1e_hw *hw = &adapter->hw;
1272 int max_ints = AT_MAX_INT_WORK;
1273 int handled = IRQ_NONE;
1274 u32 status;
1275
1276 do {
1277 status = AT_READ_REG(hw, REG_ISR);
1278 if ((status & IMR_NORMAL_MASK) == 0 ||
1279 (status & ISR_DIS_INT) != 0) {
1280 if (max_ints != AT_MAX_INT_WORK)
1281 handled = IRQ_HANDLED;
1282 break;
1283 }
1284 /* link event */
1285 if (status & ISR_GPHY)
1286 atl1e_clear_phy_int(adapter);
1287 /* Ack ISR */
1288 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1289
1290 handled = IRQ_HANDLED;
1291 /* check if PCIE PHY Link down */
1292 if (status & ISR_PHY_LINKDOWN) {
1293 netdev_err(adapter->netdev,
1294 "pcie phy linkdown %x\n", status);
1295 if (netif_running(adapter->netdev)) {
1296 /* reset MAC */
1297 atl1e_irq_reset(adapter);
1298 schedule_work(&adapter->reset_task);
1299 break;
1300 }
1301 }
1302
1303 /* check if DMA read/write error */
1304 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1305 netdev_err(adapter->netdev,
1306 "PCIE DMA RW error (status = 0x%x)\n",
1307 status);
1308 atl1e_irq_reset(adapter);
1309 schedule_work(&adapter->reset_task);
1310 break;
1311 }
1312
1313 if (status & ISR_SMB)
1314 atl1e_update_hw_stats(adapter);
1315
1316 /* link event */
1317 if (status & (ISR_GPHY | ISR_MANUAL)) {
1318 netdev->stats.tx_carrier_errors++;
1319 atl1e_link_chg_event(adapter);
1320 break;
1321 }
1322
1323 /* transmit event */
1324 if (status & ISR_TX_EVENT)
1325 atl1e_clean_tx_irq(adapter);
1326
1327 if (status & ISR_RX_EVENT) {
1328 /*
1329 * disable rx interrupts, without
1330 * the synchronize_irq bit
1331 */
1332 AT_WRITE_REG(hw, REG_IMR,
1333 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1334 AT_WRITE_FLUSH(hw);
1335 if (likely(napi_schedule_prep(
1336 &adapter->napi)))
1337 __napi_schedule(&adapter->napi);
1338 }
1339 } while (--max_ints > 0);
1340 /* re-enable Interrupt*/
1341 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1342
1343 return handled;
1344}
1345
1346static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1347 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1348{
1349 u8 *packet = (u8 *)(prrs + 1);
1350 struct iphdr *iph;
1351 u16 head_len = ETH_HLEN;
1352 u16 pkt_flags;
1353 u16 err_flags;
1354
1355 skb_checksum_none_assert(skb);
1356 pkt_flags = prrs->pkt_flag;
1357 err_flags = prrs->err_flag;
1358 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1359 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1360 if (pkt_flags & RRS_IS_IPV4) {
1361 if (pkt_flags & RRS_IS_802_3)
1362 head_len += 8;
1363 iph = (struct iphdr *) (packet + head_len);
1364 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1365 goto hw_xsum;
1366 }
1367 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1368 skb->ip_summed = CHECKSUM_UNNECESSARY;
1369 return;
1370 }
1371 }
1372
1373hw_xsum :
1374 return;
1375}
1376
1377static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1378 u8 que)
1379{
1380 struct atl1e_rx_page_desc *rx_page_desc =
1381 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1382 u8 rx_using = rx_page_desc[que].rx_using;
1383
1384 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1385}
1386
1387static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1388 int *work_done, int work_to_do)
1389{
1390 struct net_device *netdev = adapter->netdev;
1391 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1392 &adapter->rx_ring;
1393 struct atl1e_rx_page_desc *rx_page_desc =
1394 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1395 struct sk_buff *skb = NULL;
1396 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1397 u32 packet_size, write_offset;
1398 struct atl1e_recv_ret_status *prrs;
1399
1400 write_offset = *(rx_page->write_offset_addr);
1401 if (likely(rx_page->read_offset < write_offset)) {
1402 do {
1403 if (*work_done >= work_to_do)
1404 break;
1405 (*work_done)++;
1406 /* get new packet's rrs */
1407 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1408 rx_page->read_offset);
1409 /* check sequence number */
1410 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1411 netdev_err(netdev,
1412 "rx sequence number error (rx=%d) (expect=%d)\n",
1413 prrs->seq_num,
1414 rx_page_desc[que].rx_nxseq);
1415 rx_page_desc[que].rx_nxseq++;
1416 /* just for debug use */
1417 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1418 (((u32)prrs->seq_num) << 16) |
1419 rx_page_desc[que].rx_nxseq);
1420 goto fatal_err;
1421 }
1422 rx_page_desc[que].rx_nxseq++;
1423
1424 /* error packet */
1425 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1426 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1427 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1428 RRS_ERR_TRUNC)) {
1429 /* hardware error, discard this packet*/
1430 netdev_err(netdev,
1431 "rx packet desc error %x\n",
1432 *((u32 *)prrs + 1));
1433 goto skip_pkt;
1434 }
1435 }
1436
1437 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1438 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1439 skb = netdev_alloc_skb_ip_align(netdev, packet_size);
1440 if (skb == NULL) {
1441 netdev_warn(netdev,
1442 "Memory squeeze, deferring packet\n");
1443 goto skip_pkt;
1444 }
1445 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1446 skb_put(skb, packet_size);
1447 skb->protocol = eth_type_trans(skb, netdev);
1448 atl1e_rx_checksum(adapter, skb, prrs);
1449
1450 if (prrs->pkt_flag & RRS_IS_VLAN_TAG) {
1451 u16 vlan_tag = (prrs->vtag >> 4) |
1452 ((prrs->vtag & 7) << 13) |
1453 ((prrs->vtag & 8) << 9);
1454 netdev_dbg(netdev,
1455 "RXD VLAN TAG<RRD>=0x%04x\n",
1456 prrs->vtag);
1457 __vlan_hwaccel_put_tag(skb, vlan_tag);
1458 }
1459 netif_receive_skb(skb);
1460
1461skip_pkt:
1462 /* skip current packet whether it's ok or not. */
1463 rx_page->read_offset +=
1464 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1465 RRS_PKT_SIZE_MASK) +
1466 sizeof(struct atl1e_recv_ret_status) + 31) &
1467 0xFFFFFFE0);
1468
1469 if (rx_page->read_offset >= rx_ring->page_size) {
1470 /* mark this page clean */
1471 u16 reg_addr;
1472 u8 rx_using;
1473
1474 rx_page->read_offset =
1475 *(rx_page->write_offset_addr) = 0;
1476 rx_using = rx_page_desc[que].rx_using;
1477 reg_addr =
1478 atl1e_rx_page_vld_regs[que][rx_using];
1479 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1480 rx_page_desc[que].rx_using ^= 1;
1481 rx_page = atl1e_get_rx_page(adapter, que);
1482 }
1483 write_offset = *(rx_page->write_offset_addr);
1484 } while (rx_page->read_offset < write_offset);
1485 }
1486
1487 return;
1488
1489fatal_err:
1490 if (!test_bit(__AT_DOWN, &adapter->flags))
1491 schedule_work(&adapter->reset_task);
1492}
1493
1494/*
1495 * atl1e_clean - NAPI Rx polling callback
1496 * @adapter: board private structure
1497 */
1498static int atl1e_clean(struct napi_struct *napi, int budget)
1499{
1500 struct atl1e_adapter *adapter =
1501 container_of(napi, struct atl1e_adapter, napi);
1502 u32 imr_data;
1503 int work_done = 0;
1504
1505 /* Keep link state information with original netdev */
1506 if (!netif_carrier_ok(adapter->netdev))
1507 goto quit_polling;
1508
1509 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1510
1511 /* If no Tx and not enough Rx work done, exit the polling mode */
1512 if (work_done < budget) {
1513quit_polling:
1514 napi_complete(napi);
1515 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1516 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1517 /* test debug */
1518 if (test_bit(__AT_DOWN, &adapter->flags)) {
1519 atomic_dec(&adapter->irq_sem);
1520 netdev_err(adapter->netdev,
1521 "atl1e_clean is called when AT_DOWN\n");
1522 }
1523 /* reenable RX intr */
1524 /*atl1e_irq_enable(adapter); */
1525
1526 }
1527 return work_done;
1528}
1529
1530#ifdef CONFIG_NET_POLL_CONTROLLER
1531
1532/*
1533 * Polling 'interrupt' - used by things like netconsole to send skbs
1534 * without having to re-enable interrupts. It's not called while
1535 * the interrupt routine is executing.
1536 */
1537static void atl1e_netpoll(struct net_device *netdev)
1538{
1539 struct atl1e_adapter *adapter = netdev_priv(netdev);
1540
1541 disable_irq(adapter->pdev->irq);
1542 atl1e_intr(adapter->pdev->irq, netdev);
1543 enable_irq(adapter->pdev->irq);
1544}
1545#endif
1546
1547static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1548{
1549 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1550 u16 next_to_use = 0;
1551 u16 next_to_clean = 0;
1552
1553 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1554 next_to_use = tx_ring->next_to_use;
1555
1556 return (u16)(next_to_clean > next_to_use) ?
1557 (next_to_clean - next_to_use - 1) :
1558 (tx_ring->count + next_to_clean - next_to_use - 1);
1559}
1560
1561/*
1562 * get next usable tpd
1563 * Note: should call atl1e_tdp_avail to make sure
1564 * there is enough tpd to use
1565 */
1566static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1567{
1568 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1569 u16 next_to_use = 0;
1570
1571 next_to_use = tx_ring->next_to_use;
1572 if (++tx_ring->next_to_use == tx_ring->count)
1573 tx_ring->next_to_use = 0;
1574
1575 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1576 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1577}
1578
1579static struct atl1e_tx_buffer *
1580atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1581{
1582 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1583
1584 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1585}
1586
1587/* Calculate the transmit packet descript needed*/
1588static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1589{
1590 int i = 0;
1591 u16 tpd_req = 1;
1592 u16 fg_size = 0;
1593 u16 proto_hdr_len = 0;
1594
1595 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1596 fg_size = skb_shinfo(skb)->frags[i].size;
1597 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1598 }
1599
1600 if (skb_is_gso(skb)) {
1601 if (skb->protocol == htons(ETH_P_IP) ||
1602 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1603 proto_hdr_len = skb_transport_offset(skb) +
1604 tcp_hdrlen(skb);
1605 if (proto_hdr_len < skb_headlen(skb)) {
1606 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1607 MAX_TX_BUF_LEN - 1) >>
1608 MAX_TX_BUF_SHIFT);
1609 }
1610 }
1611
1612 }
1613 return tpd_req;
1614}
1615
1616static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1617 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1618{
1619 u8 hdr_len;
1620 u32 real_len;
1621 unsigned short offload_type;
1622 int err;
1623
1624 if (skb_is_gso(skb)) {
1625 if (skb_header_cloned(skb)) {
1626 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1627 if (unlikely(err))
1628 return -1;
1629 }
1630 offload_type = skb_shinfo(skb)->gso_type;
1631
1632 if (offload_type & SKB_GSO_TCPV4) {
1633 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1634 + ntohs(ip_hdr(skb)->tot_len));
1635
1636 if (real_len < skb->len)
1637 pskb_trim(skb, real_len);
1638
1639 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1640 if (unlikely(skb->len == hdr_len)) {
1641 /* only xsum need */
1642 netdev_warn(adapter->netdev,
1643 "IPV4 tso with zero data??\n");
1644 goto check_sum;
1645 } else {
1646 ip_hdr(skb)->check = 0;
1647 ip_hdr(skb)->tot_len = 0;
1648 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1649 ip_hdr(skb)->saddr,
1650 ip_hdr(skb)->daddr,
1651 0, IPPROTO_TCP, 0);
1652 tpd->word3 |= (ip_hdr(skb)->ihl &
1653 TDP_V4_IPHL_MASK) <<
1654 TPD_V4_IPHL_SHIFT;
1655 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1656 TPD_TCPHDRLEN_MASK) <<
1657 TPD_TCPHDRLEN_SHIFT;
1658 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1659 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1660 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1661 }
1662 return 0;
1663 }
1664 }
1665
1666check_sum:
1667 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1668 u8 css, cso;
1669
1670 cso = skb_checksum_start_offset(skb);
1671 if (unlikely(cso & 0x1)) {
1672 netdev_err(adapter->netdev,
1673 "payload offset should not ant event number\n");
1674 return -1;
1675 } else {
1676 css = cso + skb->csum_offset;
1677 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1678 TPD_PLOADOFFSET_SHIFT;
1679 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1680 TPD_CCSUMOFFSET_SHIFT;
1681 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1682 }
1683 }
1684
1685 return 0;
1686}
1687
1688static void atl1e_tx_map(struct atl1e_adapter *adapter,
1689 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1690{
1691 struct atl1e_tpd_desc *use_tpd = NULL;
1692 struct atl1e_tx_buffer *tx_buffer = NULL;
1693 u16 buf_len = skb_headlen(skb);
1694 u16 map_len = 0;
1695 u16 mapped_len = 0;
1696 u16 hdr_len = 0;
1697 u16 nr_frags;
1698 u16 f;
1699 int segment;
1700
1701 nr_frags = skb_shinfo(skb)->nr_frags;
1702 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1703 if (segment) {
1704 /* TSO */
1705 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1706 use_tpd = tpd;
1707
1708 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1709 tx_buffer->length = map_len;
1710 tx_buffer->dma = pci_map_single(adapter->pdev,
1711 skb->data, hdr_len, PCI_DMA_TODEVICE);
1712 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1713 mapped_len += map_len;
1714 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1715 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1716 ((cpu_to_le32(tx_buffer->length) &
1717 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1718 }
1719
1720 while (mapped_len < buf_len) {
1721 /* mapped_len == 0, means we should use the first tpd,
1722 which is given by caller */
1723 if (mapped_len == 0) {
1724 use_tpd = tpd;
1725 } else {
1726 use_tpd = atl1e_get_tpd(adapter);
1727 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1728 }
1729 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1730 tx_buffer->skb = NULL;
1731
1732 tx_buffer->length = map_len =
1733 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1734 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1735 tx_buffer->dma =
1736 pci_map_single(adapter->pdev, skb->data + mapped_len,
1737 map_len, PCI_DMA_TODEVICE);
1738 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1739 mapped_len += map_len;
1740 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1741 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1742 ((cpu_to_le32(tx_buffer->length) &
1743 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1744 }
1745
1746 for (f = 0; f < nr_frags; f++) {
1747 struct skb_frag_struct *frag;
1748 u16 i;
1749 u16 seg_num;
1750
1751 frag = &skb_shinfo(skb)->frags[f];
1752 buf_len = frag->size;
1753
1754 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1755 for (i = 0; i < seg_num; i++) {
1756 use_tpd = atl1e_get_tpd(adapter);
1757 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1758
1759 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1760 BUG_ON(tx_buffer->skb);
1761
1762 tx_buffer->skb = NULL;
1763 tx_buffer->length =
1764 (buf_len > MAX_TX_BUF_LEN) ?
1765 MAX_TX_BUF_LEN : buf_len;
1766 buf_len -= tx_buffer->length;
1767
1768 tx_buffer->dma =
1769 pci_map_page(adapter->pdev, frag->page,
1770 frag->page_offset +
1771 (i * MAX_TX_BUF_LEN),
1772 tx_buffer->length,
1773 PCI_DMA_TODEVICE);
1774 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_PAGE);
1775 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1776 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1777 ((cpu_to_le32(tx_buffer->length) &
1778 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1779 }
1780 }
1781
1782 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1783 /* note this one is a tcp header */
1784 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1785 /* The last tpd */
1786
1787 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1788 /* The last buffer info contain the skb address,
1789 so it will be free after unmap */
1790 tx_buffer->skb = skb;
1791}
1792
1793static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1794 struct atl1e_tpd_desc *tpd)
1795{
1796 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1797 /* Force memory writes to complete before letting h/w
1798 * know there are new descriptors to fetch. (Only
1799 * applicable for weak-ordered memory model archs,
1800 * such as IA-64). */
1801 wmb();
1802 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1803}
1804
1805static netdev_tx_t atl1e_xmit_frame(struct sk_buff *skb,
1806 struct net_device *netdev)
1807{
1808 struct atl1e_adapter *adapter = netdev_priv(netdev);
1809 unsigned long flags;
1810 u16 tpd_req = 1;
1811 struct atl1e_tpd_desc *tpd;
1812
1813 if (test_bit(__AT_DOWN, &adapter->flags)) {
1814 dev_kfree_skb_any(skb);
1815 return NETDEV_TX_OK;
1816 }
1817
1818 if (unlikely(skb->len <= 0)) {
1819 dev_kfree_skb_any(skb);
1820 return NETDEV_TX_OK;
1821 }
1822 tpd_req = atl1e_cal_tdp_req(skb);
1823 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1824 return NETDEV_TX_LOCKED;
1825
1826 if (atl1e_tpd_avail(adapter) < tpd_req) {
1827 /* no enough descriptor, just stop queue */
1828 netif_stop_queue(netdev);
1829 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1830 return NETDEV_TX_BUSY;
1831 }
1832
1833 tpd = atl1e_get_tpd(adapter);
1834
1835 if (vlan_tx_tag_present(skb)) {
1836 u16 vlan_tag = vlan_tx_tag_get(skb);
1837 u16 atl1e_vlan_tag;
1838
1839 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1840 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1841 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1842 TPD_VLAN_SHIFT;
1843 }
1844
1845 if (skb->protocol == htons(ETH_P_8021Q))
1846 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1847
1848 if (skb_network_offset(skb) != ETH_HLEN)
1849 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1850
1851 /* do TSO and check sum */
1852 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1853 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1854 dev_kfree_skb_any(skb);
1855 return NETDEV_TX_OK;
1856 }
1857
1858 atl1e_tx_map(adapter, skb, tpd);
1859 atl1e_tx_queue(adapter, tpd_req, tpd);
1860
1861 netdev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1862 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1863 return NETDEV_TX_OK;
1864}
1865
1866static void atl1e_free_irq(struct atl1e_adapter *adapter)
1867{
1868 struct net_device *netdev = adapter->netdev;
1869
1870 free_irq(adapter->pdev->irq, netdev);
1871
1872 if (adapter->have_msi)
1873 pci_disable_msi(adapter->pdev);
1874}
1875
1876static int atl1e_request_irq(struct atl1e_adapter *adapter)
1877{
1878 struct pci_dev *pdev = adapter->pdev;
1879 struct net_device *netdev = adapter->netdev;
1880 int flags = 0;
1881 int err = 0;
1882
1883 adapter->have_msi = true;
1884 err = pci_enable_msi(adapter->pdev);
1885 if (err) {
1886 netdev_dbg(adapter->netdev,
1887 "Unable to allocate MSI interrupt Error: %d\n", err);
1888 adapter->have_msi = false;
1889 } else
1890 netdev->irq = pdev->irq;
1891
1892
1893 if (!adapter->have_msi)
1894 flags |= IRQF_SHARED;
1895 err = request_irq(adapter->pdev->irq, atl1e_intr, flags,
1896 netdev->name, netdev);
1897 if (err) {
1898 netdev_dbg(adapter->netdev,
1899 "Unable to allocate interrupt Error: %d\n", err);
1900 if (adapter->have_msi)
1901 pci_disable_msi(adapter->pdev);
1902 return err;
1903 }
1904 netdev_dbg(adapter->netdev, "atl1e_request_irq OK\n");
1905 return err;
1906}
1907
1908int atl1e_up(struct atl1e_adapter *adapter)
1909{
1910 struct net_device *netdev = adapter->netdev;
1911 int err = 0;
1912 u32 val;
1913
1914 /* hardware has been reset, we need to reload some things */
1915 err = atl1e_init_hw(&adapter->hw);
1916 if (err) {
1917 err = -EIO;
1918 return err;
1919 }
1920 atl1e_init_ring_ptrs(adapter);
1921 atl1e_set_multi(netdev);
1922 atl1e_restore_vlan(adapter);
1923
1924 if (atl1e_configure(adapter)) {
1925 err = -EIO;
1926 goto err_up;
1927 }
1928
1929 clear_bit(__AT_DOWN, &adapter->flags);
1930 napi_enable(&adapter->napi);
1931 atl1e_irq_enable(adapter);
1932 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1933 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1934 val | MASTER_CTRL_MANUAL_INT);
1935
1936err_up:
1937 return err;
1938}
1939
1940void atl1e_down(struct atl1e_adapter *adapter)
1941{
1942 struct net_device *netdev = adapter->netdev;
1943
1944 /* signal that we're down so the interrupt handler does not
1945 * reschedule our watchdog timer */
1946 set_bit(__AT_DOWN, &adapter->flags);
1947
1948 netif_stop_queue(netdev);
1949
1950 /* reset MAC to disable all RX/TX */
1951 atl1e_reset_hw(&adapter->hw);
1952 msleep(1);
1953
1954 napi_disable(&adapter->napi);
1955 atl1e_del_timer(adapter);
1956 atl1e_irq_disable(adapter);
1957
1958 netif_carrier_off(netdev);
1959 adapter->link_speed = SPEED_0;
1960 adapter->link_duplex = -1;
1961 atl1e_clean_tx_ring(adapter);
1962 atl1e_clean_rx_ring(adapter);
1963}
1964
1965/*
1966 * atl1e_open - Called when a network interface is made active
1967 * @netdev: network interface device structure
1968 *
1969 * Returns 0 on success, negative value on failure
1970 *
1971 * The open entry point is called when a network interface is made
1972 * active by the system (IFF_UP). At this point all resources needed
1973 * for transmit and receive operations are allocated, the interrupt
1974 * handler is registered with the OS, the watchdog timer is started,
1975 * and the stack is notified that the interface is ready.
1976 */
1977static int atl1e_open(struct net_device *netdev)
1978{
1979 struct atl1e_adapter *adapter = netdev_priv(netdev);
1980 int err;
1981
1982 /* disallow open during test */
1983 if (test_bit(__AT_TESTING, &adapter->flags))
1984 return -EBUSY;
1985
1986 /* allocate rx/tx dma buffer & descriptors */
1987 atl1e_init_ring_resources(adapter);
1988 err = atl1e_setup_ring_resources(adapter);
1989 if (unlikely(err))
1990 return err;
1991
1992 err = atl1e_request_irq(adapter);
1993 if (unlikely(err))
1994 goto err_req_irq;
1995
1996 err = atl1e_up(adapter);
1997 if (unlikely(err))
1998 goto err_up;
1999
2000 return 0;
2001
2002err_up:
2003 atl1e_free_irq(adapter);
2004err_req_irq:
2005 atl1e_free_ring_resources(adapter);
2006 atl1e_reset_hw(&adapter->hw);
2007
2008 return err;
2009}
2010
2011/*
2012 * atl1e_close - Disables a network interface
2013 * @netdev: network interface device structure
2014 *
2015 * Returns 0, this is not allowed to fail
2016 *
2017 * The close entry point is called when an interface is de-activated
2018 * by the OS. The hardware is still under the drivers control, but
2019 * needs to be disabled. A global MAC reset is issued to stop the
2020 * hardware, and all transmit and receive resources are freed.
2021 */
2022static int atl1e_close(struct net_device *netdev)
2023{
2024 struct atl1e_adapter *adapter = netdev_priv(netdev);
2025
2026 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2027 atl1e_down(adapter);
2028 atl1e_free_irq(adapter);
2029 atl1e_free_ring_resources(adapter);
2030
2031 return 0;
2032}
2033
2034static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2035{
2036 struct net_device *netdev = pci_get_drvdata(pdev);
2037 struct atl1e_adapter *adapter = netdev_priv(netdev);
2038 struct atl1e_hw *hw = &adapter->hw;
2039 u32 ctrl = 0;
2040 u32 mac_ctrl_data = 0;
2041 u32 wol_ctrl_data = 0;
2042 u16 mii_advertise_data = 0;
2043 u16 mii_bmsr_data = 0;
2044 u16 mii_intr_status_data = 0;
2045 u32 wufc = adapter->wol;
2046 u32 i;
2047#ifdef CONFIG_PM
2048 int retval = 0;
2049#endif
2050
2051 if (netif_running(netdev)) {
2052 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2053 atl1e_down(adapter);
2054 }
2055 netif_device_detach(netdev);
2056
2057#ifdef CONFIG_PM
2058 retval = pci_save_state(pdev);
2059 if (retval)
2060 return retval;
2061#endif
2062
2063 if (wufc) {
2064 /* get link status */
2065 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2066 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2067
2068 mii_advertise_data = ADVERTISE_10HALF;
2069
2070 if ((atl1e_write_phy_reg(hw, MII_CTRL1000, 0) != 0) ||
2071 (atl1e_write_phy_reg(hw,
2072 MII_ADVERTISE, mii_advertise_data) != 0) ||
2073 (atl1e_phy_commit(hw)) != 0) {
2074 netdev_dbg(adapter->netdev, "set phy register failed\n");
2075 goto wol_dis;
2076 }
2077
2078 hw->phy_configured = false; /* re-init PHY when resume */
2079
2080 /* turn on magic packet wol */
2081 if (wufc & AT_WUFC_MAG)
2082 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2083
2084 if (wufc & AT_WUFC_LNKC) {
2085 /* if orignal link status is link, just wait for retrive link */
2086 if (mii_bmsr_data & BMSR_LSTATUS) {
2087 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2088 msleep(100);
2089 atl1e_read_phy_reg(hw, MII_BMSR,
2090 (u16 *)&mii_bmsr_data);
2091 if (mii_bmsr_data & BMSR_LSTATUS)
2092 break;
2093 }
2094
2095 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2096 netdev_dbg(adapter->netdev,
2097 "Link may change when suspend\n");
2098 }
2099 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2100 /* only link up can wake up */
2101 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2102 netdev_dbg(adapter->netdev,
2103 "read write phy register failed\n");
2104 goto wol_dis;
2105 }
2106 }
2107 /* clear phy interrupt */
2108 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2109 /* Config MAC Ctrl register */
2110 mac_ctrl_data = MAC_CTRL_RX_EN;
2111 /* set to 10/100M halt duplex */
2112 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2113 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2114 MAC_CTRL_PRMLEN_MASK) <<
2115 MAC_CTRL_PRMLEN_SHIFT);
2116
2117 __atl1e_vlan_mode(netdev->features, &mac_ctrl_data);
2118
2119 /* magic packet maybe Broadcast&multicast&Unicast frame */
2120 if (wufc & AT_WUFC_MAG)
2121 mac_ctrl_data |= MAC_CTRL_BC_EN;
2122
2123 netdev_dbg(adapter->netdev, "suspend MAC=0x%x\n",
2124 mac_ctrl_data);
2125
2126 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2127 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2128 /* pcie patch */
2129 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2130 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2131 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2132 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2133 goto suspend_exit;
2134 }
2135wol_dis:
2136
2137 /* WOL disabled */
2138 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2139
2140 /* pcie patch */
2141 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2142 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2143 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2144
2145 atl1e_force_ps(hw);
2146 hw->phy_configured = false; /* re-init PHY when resume */
2147
2148 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2149
2150suspend_exit:
2151
2152 if (netif_running(netdev))
2153 atl1e_free_irq(adapter);
2154
2155 pci_disable_device(pdev);
2156
2157 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2158
2159 return 0;
2160}
2161
2162#ifdef CONFIG_PM
2163static int atl1e_resume(struct pci_dev *pdev)
2164{
2165 struct net_device *netdev = pci_get_drvdata(pdev);
2166 struct atl1e_adapter *adapter = netdev_priv(netdev);
2167 u32 err;
2168
2169 pci_set_power_state(pdev, PCI_D0);
2170 pci_restore_state(pdev);
2171
2172 err = pci_enable_device(pdev);
2173 if (err) {
2174 netdev_err(adapter->netdev,
2175 "Cannot enable PCI device from suspend\n");
2176 return err;
2177 }
2178
2179 pci_set_master(pdev);
2180
2181 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2182
2183 pci_enable_wake(pdev, PCI_D3hot, 0);
2184 pci_enable_wake(pdev, PCI_D3cold, 0);
2185
2186 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2187
2188 if (netif_running(netdev)) {
2189 err = atl1e_request_irq(adapter);
2190 if (err)
2191 return err;
2192 }
2193
2194 atl1e_reset_hw(&adapter->hw);
2195
2196 if (netif_running(netdev))
2197 atl1e_up(adapter);
2198
2199 netif_device_attach(netdev);
2200
2201 return 0;
2202}
2203#endif
2204
2205static void atl1e_shutdown(struct pci_dev *pdev)
2206{
2207 atl1e_suspend(pdev, PMSG_SUSPEND);
2208}
2209
2210static const struct net_device_ops atl1e_netdev_ops = {
2211 .ndo_open = atl1e_open,
2212 .ndo_stop = atl1e_close,
2213 .ndo_start_xmit = atl1e_xmit_frame,
2214 .ndo_get_stats = atl1e_get_stats,
2215 .ndo_set_multicast_list = atl1e_set_multi,
2216 .ndo_validate_addr = eth_validate_addr,
2217 .ndo_set_mac_address = atl1e_set_mac_addr,
2218 .ndo_fix_features = atl1e_fix_features,
2219 .ndo_set_features = atl1e_set_features,
2220 .ndo_change_mtu = atl1e_change_mtu,
2221 .ndo_do_ioctl = atl1e_ioctl,
2222 .ndo_tx_timeout = atl1e_tx_timeout,
2223#ifdef CONFIG_NET_POLL_CONTROLLER
2224 .ndo_poll_controller = atl1e_netpoll,
2225#endif
2226
2227};
2228
2229static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2230{
2231 SET_NETDEV_DEV(netdev, &pdev->dev);
2232 pci_set_drvdata(pdev, netdev);
2233
2234 netdev->irq = pdev->irq;
2235 netdev->netdev_ops = &atl1e_netdev_ops;
2236
2237 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2238 atl1e_set_ethtool_ops(netdev);
2239
2240 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO |
2241 NETIF_F_HW_VLAN_RX;
2242 netdev->features = netdev->hw_features | NETIF_F_LLTX |
2243 NETIF_F_HW_VLAN_TX;
2244
2245 return 0;
2246}
2247
2248/*
2249 * atl1e_probe - Device Initialization Routine
2250 * @pdev: PCI device information struct
2251 * @ent: entry in atl1e_pci_tbl
2252 *
2253 * Returns 0 on success, negative on failure
2254 *
2255 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2256 * The OS initialization, configuring of the adapter private structure,
2257 * and a hardware reset occur.
2258 */
2259static int __devinit atl1e_probe(struct pci_dev *pdev,
2260 const struct pci_device_id *ent)
2261{
2262 struct net_device *netdev;
2263 struct atl1e_adapter *adapter = NULL;
2264 static int cards_found;
2265
2266 int err = 0;
2267
2268 err = pci_enable_device(pdev);
2269 if (err) {
2270 dev_err(&pdev->dev, "cannot enable PCI device\n");
2271 return err;
2272 }
2273
2274 /*
2275 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2276 * shared register for the high 32 bits, so only a single, aligned,
2277 * 4 GB physical address range can be used at a time.
2278 *
2279 * Supporting 64-bit DMA on this hardware is more trouble than it's
2280 * worth. It is far easier to limit to 32-bit DMA than update
2281 * various kernel subsystems to support the mechanics required by a
2282 * fixed-high-32-bit system.
2283 */
2284 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2285 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2286 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2287 goto err_dma;
2288 }
2289
2290 err = pci_request_regions(pdev, atl1e_driver_name);
2291 if (err) {
2292 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2293 goto err_pci_reg;
2294 }
2295
2296 pci_set_master(pdev);
2297
2298 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2299 if (netdev == NULL) {
2300 err = -ENOMEM;
2301 dev_err(&pdev->dev, "etherdev alloc failed\n");
2302 goto err_alloc_etherdev;
2303 }
2304
2305 err = atl1e_init_netdev(netdev, pdev);
2306 if (err) {
2307 netdev_err(netdev, "init netdevice failed\n");
2308 goto err_init_netdev;
2309 }
2310 adapter = netdev_priv(netdev);
2311 adapter->bd_number = cards_found;
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 adapter->hw.adapter = adapter;
2315 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2316 if (!adapter->hw.hw_addr) {
2317 err = -EIO;
2318 netdev_err(netdev, "cannot map device registers\n");
2319 goto err_ioremap;
2320 }
2321 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2322
2323 /* init mii data */
2324 adapter->mii.dev = netdev;
2325 adapter->mii.mdio_read = atl1e_mdio_read;
2326 adapter->mii.mdio_write = atl1e_mdio_write;
2327 adapter->mii.phy_id_mask = 0x1f;
2328 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2329
2330 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2331
2332 init_timer(&adapter->phy_config_timer);
2333 adapter->phy_config_timer.function = atl1e_phy_config;
2334 adapter->phy_config_timer.data = (unsigned long) adapter;
2335
2336 /* get user settings */
2337 atl1e_check_options(adapter);
2338 /*
2339 * Mark all PCI regions associated with PCI device
2340 * pdev as being reserved by owner atl1e_driver_name
2341 * Enables bus-mastering on the device and calls
2342 * pcibios_set_master to do the needed arch specific settings
2343 */
2344 atl1e_setup_pcicmd(pdev);
2345 /* setup the private structure */
2346 err = atl1e_sw_init(adapter);
2347 if (err) {
2348 netdev_err(netdev, "net device private data init failed\n");
2349 goto err_sw_init;
2350 }
2351
2352 /* Init GPHY as early as possible due to power saving issue */
2353 atl1e_phy_init(&adapter->hw);
2354 /* reset the controller to
2355 * put the device in a known good starting state */
2356 err = atl1e_reset_hw(&adapter->hw);
2357 if (err) {
2358 err = -EIO;
2359 goto err_reset;
2360 }
2361
2362 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2363 err = -EIO;
2364 netdev_err(netdev, "get mac address failed\n");
2365 goto err_eeprom;
2366 }
2367
2368 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2369 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2370 netdev_dbg(netdev, "mac address : %pM\n", adapter->hw.mac_addr);
2371
2372 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2373 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2374 err = register_netdev(netdev);
2375 if (err) {
2376 netdev_err(netdev, "register netdevice failed\n");
2377 goto err_register;
2378 }
2379
2380 /* assume we have no link for now */
2381 netif_stop_queue(netdev);
2382 netif_carrier_off(netdev);
2383
2384 cards_found++;
2385
2386 return 0;
2387
2388err_reset:
2389err_register:
2390err_sw_init:
2391err_eeprom:
2392 iounmap(adapter->hw.hw_addr);
2393err_init_netdev:
2394err_ioremap:
2395 free_netdev(netdev);
2396err_alloc_etherdev:
2397 pci_release_regions(pdev);
2398err_pci_reg:
2399err_dma:
2400 pci_disable_device(pdev);
2401 return err;
2402}
2403
2404/*
2405 * atl1e_remove - Device Removal Routine
2406 * @pdev: PCI device information struct
2407 *
2408 * atl1e_remove is called by the PCI subsystem to alert the driver
2409 * that it should release a PCI device. The could be caused by a
2410 * Hot-Plug event, or because the driver is going to be removed from
2411 * memory.
2412 */
2413static void __devexit atl1e_remove(struct pci_dev *pdev)
2414{
2415 struct net_device *netdev = pci_get_drvdata(pdev);
2416 struct atl1e_adapter *adapter = netdev_priv(netdev);
2417
2418 /*
2419 * flush_scheduled work may reschedule our watchdog task, so
2420 * explicitly disable watchdog tasks from being rescheduled
2421 */
2422 set_bit(__AT_DOWN, &adapter->flags);
2423
2424 atl1e_del_timer(adapter);
2425 atl1e_cancel_work(adapter);
2426
2427 unregister_netdev(netdev);
2428 atl1e_free_ring_resources(adapter);
2429 atl1e_force_ps(&adapter->hw);
2430 iounmap(adapter->hw.hw_addr);
2431 pci_release_regions(pdev);
2432 free_netdev(netdev);
2433 pci_disable_device(pdev);
2434}
2435
2436/*
2437 * atl1e_io_error_detected - called when PCI error is detected
2438 * @pdev: Pointer to PCI device
2439 * @state: The current pci connection state
2440 *
2441 * This function is called after a PCI bus error affecting
2442 * this device has been detected.
2443 */
2444static pci_ers_result_t
2445atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2446{
2447 struct net_device *netdev = pci_get_drvdata(pdev);
2448 struct atl1e_adapter *adapter = netdev_priv(netdev);
2449
2450 netif_device_detach(netdev);
2451
2452 if (state == pci_channel_io_perm_failure)
2453 return PCI_ERS_RESULT_DISCONNECT;
2454
2455 if (netif_running(netdev))
2456 atl1e_down(adapter);
2457
2458 pci_disable_device(pdev);
2459
2460 /* Request a slot slot reset. */
2461 return PCI_ERS_RESULT_NEED_RESET;
2462}
2463
2464/*
2465 * atl1e_io_slot_reset - called after the pci bus has been reset.
2466 * @pdev: Pointer to PCI device
2467 *
2468 * Restart the card from scratch, as if from a cold-boot. Implementation
2469 * resembles the first-half of the e1000_resume routine.
2470 */
2471static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2472{
2473 struct net_device *netdev = pci_get_drvdata(pdev);
2474 struct atl1e_adapter *adapter = netdev_priv(netdev);
2475
2476 if (pci_enable_device(pdev)) {
2477 netdev_err(adapter->netdev,
2478 "Cannot re-enable PCI device after reset\n");
2479 return PCI_ERS_RESULT_DISCONNECT;
2480 }
2481 pci_set_master(pdev);
2482
2483 pci_enable_wake(pdev, PCI_D3hot, 0);
2484 pci_enable_wake(pdev, PCI_D3cold, 0);
2485
2486 atl1e_reset_hw(&adapter->hw);
2487
2488 return PCI_ERS_RESULT_RECOVERED;
2489}
2490
2491/*
2492 * atl1e_io_resume - called when traffic can start flowing again.
2493 * @pdev: Pointer to PCI device
2494 *
2495 * This callback is called when the error recovery driver tells us that
2496 * its OK to resume normal operation. Implementation resembles the
2497 * second-half of the atl1e_resume routine.
2498 */
2499static void atl1e_io_resume(struct pci_dev *pdev)
2500{
2501 struct net_device *netdev = pci_get_drvdata(pdev);
2502 struct atl1e_adapter *adapter = netdev_priv(netdev);
2503
2504 if (netif_running(netdev)) {
2505 if (atl1e_up(adapter)) {
2506 netdev_err(adapter->netdev,
2507 "can't bring device back up after reset\n");
2508 return;
2509 }
2510 }
2511
2512 netif_device_attach(netdev);
2513}
2514
2515static struct pci_error_handlers atl1e_err_handler = {
2516 .error_detected = atl1e_io_error_detected,
2517 .slot_reset = atl1e_io_slot_reset,
2518 .resume = atl1e_io_resume,
2519};
2520
2521static struct pci_driver atl1e_driver = {
2522 .name = atl1e_driver_name,
2523 .id_table = atl1e_pci_tbl,
2524 .probe = atl1e_probe,
2525 .remove = __devexit_p(atl1e_remove),
2526 /* Power Management Hooks */
2527#ifdef CONFIG_PM
2528 .suspend = atl1e_suspend,
2529 .resume = atl1e_resume,
2530#endif
2531 .shutdown = atl1e_shutdown,
2532 .err_handler = &atl1e_err_handler
2533};
2534
2535/*
2536 * atl1e_init_module - Driver Registration Routine
2537 *
2538 * atl1e_init_module is the first routine called when the driver is
2539 * loaded. All it does is register with the PCI subsystem.
2540 */
2541static int __init atl1e_init_module(void)
2542{
2543 return pci_register_driver(&atl1e_driver);
2544}
2545
2546/*
2547 * atl1e_exit_module - Driver Exit Cleanup Routine
2548 *
2549 * atl1e_exit_module is called just before the driver is removed
2550 * from memory.
2551 */
2552static void __exit atl1e_exit_module(void)
2553{
2554 pci_unregister_driver(&atl1e_driver);
2555}
2556
2557module_init(atl1e_init_module);
2558module_exit(atl1e_exit_module);
diff --git a/drivers/net/atl1e/atl1e_param.c b/drivers/net/atl1e/atl1e_param.c
deleted file mode 100644
index 0ce60b6e7ef0..000000000000
--- a/drivers/net/atl1e/atl1e_param.c
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include <linux/netdevice.h>
23
24#include "atl1e.h"
25
26/* This is the only thing that needs to be changed to adjust the
27 * maximum number of ports that the driver can manage.
28 */
29
30#define ATL1E_MAX_NIC 32
31
32#define OPTION_UNSET -1
33#define OPTION_DISABLED 0
34#define OPTION_ENABLED 1
35
36/* All parameters are treated the same, as an integer array of values.
37 * This macro just reduces the need to repeat the same declaration code
38 * over and over (plus this helps to avoid typo bugs).
39 */
40#define ATL1E_PARAM_INIT { [0 ... ATL1E_MAX_NIC] = OPTION_UNSET }
41
42#define ATL1E_PARAM(x, desc) \
43 static int __devinitdata x[ATL1E_MAX_NIC + 1] = ATL1E_PARAM_INIT; \
44 static unsigned int num_##x; \
45 module_param_array_named(x, x, int, &num_##x, 0); \
46 MODULE_PARM_DESC(x, desc);
47
48/* Transmit Memory count
49 *
50 * Valid Range: 64-2048
51 *
52 * Default Value: 128
53 */
54#define ATL1E_MIN_TX_DESC_CNT 32
55#define ATL1E_MAX_TX_DESC_CNT 1020
56#define ATL1E_DEFAULT_TX_DESC_CNT 128
57ATL1E_PARAM(tx_desc_cnt, "Transmit description count");
58
59/* Receive Memory Block Count
60 *
61 * Valid Range: 16-512
62 *
63 * Default Value: 128
64 */
65#define ATL1E_MIN_RX_MEM_SIZE 8 /* 8KB */
66#define ATL1E_MAX_RX_MEM_SIZE 1024 /* 1MB */
67#define ATL1E_DEFAULT_RX_MEM_SIZE 256 /* 128KB */
68ATL1E_PARAM(rx_mem_size, "memory size of rx buffer(KB)");
69
70/* User Specified MediaType Override
71 *
72 * Valid Range: 0-5
73 * - 0 - auto-negotiate at all supported speeds
74 * - 1 - only link at 100Mbps Full Duplex
75 * - 2 - only link at 100Mbps Half Duplex
76 * - 3 - only link at 10Mbps Full Duplex
77 * - 4 - only link at 10Mbps Half Duplex
78 * Default Value: 0
79 */
80
81ATL1E_PARAM(media_type, "MediaType Select");
82
83/* Interrupt Moderate Timer in units of 2 us
84 *
85 * Valid Range: 10-65535
86 *
87 * Default Value: 45000(90ms)
88 */
89#define INT_MOD_DEFAULT_CNT 100 /* 200us */
90#define INT_MOD_MAX_CNT 65000
91#define INT_MOD_MIN_CNT 50
92ATL1E_PARAM(int_mod_timer, "Interrupt Moderator Timer");
93
94#define AUTONEG_ADV_DEFAULT 0x2F
95#define AUTONEG_ADV_MASK 0x2F
96#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
97
98#define FLASH_VENDOR_DEFAULT 0
99#define FLASH_VENDOR_MIN 0
100#define FLASH_VENDOR_MAX 2
101
102struct atl1e_option {
103 enum { enable_option, range_option, list_option } type;
104 char *name;
105 char *err;
106 int def;
107 union {
108 struct { /* range_option info */
109 int min;
110 int max;
111 } r;
112 struct { /* list_option info */
113 int nr;
114 struct atl1e_opt_list { int i; char *str; } *p;
115 } l;
116 } arg;
117};
118
119static int __devinit atl1e_validate_option(int *value, struct atl1e_option *opt, struct atl1e_adapter *adapter)
120{
121 if (*value == OPTION_UNSET) {
122 *value = opt->def;
123 return 0;
124 }
125
126 switch (opt->type) {
127 case enable_option:
128 switch (*value) {
129 case OPTION_ENABLED:
130 netdev_info(adapter->netdev,
131 "%s Enabled\n", opt->name);
132 return 0;
133 case OPTION_DISABLED:
134 netdev_info(adapter->netdev,
135 "%s Disabled\n", opt->name);
136 return 0;
137 }
138 break;
139 case range_option:
140 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
141 netdev_info(adapter->netdev, "%s set to %i\n",
142 opt->name, *value);
143 return 0;
144 }
145 break;
146 case list_option:{
147 int i;
148 struct atl1e_opt_list *ent;
149
150 for (i = 0; i < opt->arg.l.nr; i++) {
151 ent = &opt->arg.l.p[i];
152 if (*value == ent->i) {
153 if (ent->str[0] != '\0')
154 netdev_info(adapter->netdev,
155 "%s\n", ent->str);
156 return 0;
157 }
158 }
159 break;
160 }
161 default:
162 BUG();
163 }
164
165 netdev_info(adapter->netdev, "Invalid %s specified (%i) %s\n",
166 opt->name, *value, opt->err);
167 *value = opt->def;
168 return -1;
169}
170
171/*
172 * atl1e_check_options - Range Checking for Command Line Parameters
173 * @adapter: board private structure
174 *
175 * This routine checks all command line parameters for valid user
176 * input. If an invalid value is given, or if no user specified
177 * value exists, a default value is used. The final value is stored
178 * in a variable in the adapter structure.
179 */
180void __devinit atl1e_check_options(struct atl1e_adapter *adapter)
181{
182 int bd = adapter->bd_number;
183
184 if (bd >= ATL1E_MAX_NIC) {
185 netdev_notice(adapter->netdev,
186 "no configuration for board #%i\n", bd);
187 netdev_notice(adapter->netdev,
188 "Using defaults for all values\n");
189 }
190
191 { /* Transmit Ring Size */
192 struct atl1e_option opt = {
193 .type = range_option,
194 .name = "Transmit Ddescription Count",
195 .err = "using default of "
196 __MODULE_STRING(ATL1E_DEFAULT_TX_DESC_CNT),
197 .def = ATL1E_DEFAULT_TX_DESC_CNT,
198 .arg = { .r = { .min = ATL1E_MIN_TX_DESC_CNT,
199 .max = ATL1E_MAX_TX_DESC_CNT} }
200 };
201 int val;
202 if (num_tx_desc_cnt > bd) {
203 val = tx_desc_cnt[bd];
204 atl1e_validate_option(&val, &opt, adapter);
205 adapter->tx_ring.count = (u16) val & 0xFFFC;
206 } else
207 adapter->tx_ring.count = (u16)opt.def;
208 }
209
210 { /* Receive Memory Block Count */
211 struct atl1e_option opt = {
212 .type = range_option,
213 .name = "Memory size of rx buffer(KB)",
214 .err = "using default of "
215 __MODULE_STRING(ATL1E_DEFAULT_RX_MEM_SIZE),
216 .def = ATL1E_DEFAULT_RX_MEM_SIZE,
217 .arg = { .r = { .min = ATL1E_MIN_RX_MEM_SIZE,
218 .max = ATL1E_MAX_RX_MEM_SIZE} }
219 };
220 int val;
221 if (num_rx_mem_size > bd) {
222 val = rx_mem_size[bd];
223 atl1e_validate_option(&val, &opt, adapter);
224 adapter->rx_ring.page_size = (u32)val * 1024;
225 } else {
226 adapter->rx_ring.page_size = (u32)opt.def * 1024;
227 }
228 }
229
230 { /* Interrupt Moderate Timer */
231 struct atl1e_option opt = {
232 .type = range_option,
233 .name = "Interrupt Moderate Timer",
234 .err = "using default of "
235 __MODULE_STRING(INT_MOD_DEFAULT_CNT),
236 .def = INT_MOD_DEFAULT_CNT,
237 .arg = { .r = { .min = INT_MOD_MIN_CNT,
238 .max = INT_MOD_MAX_CNT} }
239 } ;
240 int val;
241 if (num_int_mod_timer > bd) {
242 val = int_mod_timer[bd];
243 atl1e_validate_option(&val, &opt, adapter);
244 adapter->hw.imt = (u16) val;
245 } else
246 adapter->hw.imt = (u16)(opt.def);
247 }
248
249 { /* MediaType */
250 struct atl1e_option opt = {
251 .type = range_option,
252 .name = "Speed/Duplex Selection",
253 .err = "using default of "
254 __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR),
255 .def = MEDIA_TYPE_AUTO_SENSOR,
256 .arg = { .r = { .min = MEDIA_TYPE_AUTO_SENSOR,
257 .max = MEDIA_TYPE_10M_HALF} }
258 } ;
259 int val;
260 if (num_media_type > bd) {
261 val = media_type[bd];
262 atl1e_validate_option(&val, &opt, adapter);
263 adapter->hw.media_type = (u16) val;
264 } else
265 adapter->hw.media_type = (u16)(opt.def);
266
267 }
268}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 12:26:33 -0400