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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-20 09:55:16 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-11 19:29:59 -0400
commit2b133ad6e9e96798007e64eb912c42fa00adef0a (patch)
tree34d1760a9257b150289893cda05b4adfa1990306 /drivers/net/atl1c/atl1c.h
parent3401299a1b9e747cbf7de2cc0c8f6376c3cbe565 (diff)
atl*: Move the Atheros drivers
Move the Atheros drivers into drivers/net/ethernet/atheros/ and make the necessary Kconfig and Makefile changes. CC: Jay Cliburn <jcliburn@gmail.com> CC: Chris Snook <chris.snook@gmail.com> CC: Jie Yang <jie.yang@atheros.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/atl1c/atl1c.h')
-rw-r--r--drivers/net/atl1c/atl1c.h636
1 files changed, 0 insertions, 636 deletions
diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h
deleted file mode 100644
index ca70e16b6e2c..000000000000
--- a/drivers/net/atl1c/atl1c.h
+++ /dev/null
@@ -1,636 +0,0 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_H_
23#define _ATL1C_H_
24
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ioport.h>
35#include <linux/slab.h>
36#include <linux/list.h>
37#include <linux/delay.h>
38#include <linux/sched.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/ipv6.h>
42#include <linux/udp.h>
43#include <linux/mii.h>
44#include <linux/io.h>
45#include <linux/vmalloc.h>
46#include <linux/pagemap.h>
47#include <linux/tcp.h>
48#include <linux/ethtool.h>
49#include <linux/if_vlan.h>
50#include <linux/workqueue.h>
51#include <net/checksum.h>
52#include <net/ip6_checksum.h>
53
54#include "atl1c_hw.h"
55
56/* Wake Up Filter Control */
57#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
58#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
59#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
60#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
61#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
62
63#define AT_VLAN_TO_TAG(_vlan, _tag) \
64 _tag = ((((_vlan) >> 8) & 0xFF) |\
65 (((_vlan) & 0xFF) << 8))
66
67#define AT_TAG_TO_VLAN(_tag, _vlan) \
68 _vlan = ((((_tag) >> 8) & 0xFF) |\
69 (((_tag) & 0xFF) << 8))
70
71#define SPEED_0 0xffff
72#define HALF_DUPLEX 1
73#define FULL_DUPLEX 2
74
75#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
76#define MAX_JUMBO_FRAME_SIZE (6*1024)
77#define MAX_TSO_FRAME_SIZE (7*1024)
78#define MAX_TX_OFFLOAD_THRESH (9*1024)
79
80#define AT_MAX_RECEIVE_QUEUE 4
81#define AT_DEF_RECEIVE_QUEUE 1
82#define AT_MAX_TRANSMIT_QUEUE 2
83
84#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
85#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
86
87#define AT_TX_WATCHDOG (5 * HZ)
88#define AT_MAX_INT_WORK 5
89#define AT_TWSI_EEPROM_TIMEOUT 100
90#define AT_HW_MAX_IDLE_DELAY 10
91#define AT_SUSPEND_LINK_TIMEOUT 100
92
93#define AT_ASPM_L0S_TIMER 6
94#define AT_ASPM_L1_TIMER 12
95#define AT_LCKDET_TIMER 12
96
97#define ATL1C_PCIE_L0S_L1_DISABLE 0x01
98#define ATL1C_PCIE_PHY_RESET 0x02
99
100#define ATL1C_ASPM_L0s_ENABLE 0x0001
101#define ATL1C_ASPM_L1_ENABLE 0x0002
102
103#define AT_REGS_LEN (75 * sizeof(u32))
104#define AT_EEPROM_LEN 512
105
106#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
107#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
108#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
109#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
110
111/* tpd word 1 bit 0:7 General Checksum task offload */
112#define TPD_L4HDR_OFFSET_MASK 0x00FF
113#define TPD_L4HDR_OFFSET_SHIFT 0
114
115/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
116#define TPD_TCPHDR_OFFSET_MASK 0x00FF
117#define TPD_TCPHDR_OFFSET_SHIFT 0
118
119/* tpd word 1 bit 0:7 Custom Checksum task offload */
120#define TPD_PLOADOFFSET_MASK 0x00FF
121#define TPD_PLOADOFFSET_SHIFT 0
122
123/* tpd word 1 bit 8:17 */
124#define TPD_CCSUM_EN_MASK 0x0001
125#define TPD_CCSUM_EN_SHIFT 8
126#define TPD_IP_CSUM_MASK 0x0001
127#define TPD_IP_CSUM_SHIFT 9
128#define TPD_TCP_CSUM_MASK 0x0001
129#define TPD_TCP_CSUM_SHIFT 10
130#define TPD_UDP_CSUM_MASK 0x0001
131#define TPD_UDP_CSUM_SHIFT 11
132#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
133#define TPD_LSO_EN_SHIFT 12
134#define TPD_LSO_VER_MASK 0x0001
135#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
136#define TPD_CON_VTAG_MASK 0x0001
137#define TPD_CON_VTAG_SHIFT 14
138#define TPD_INS_VTAG_MASK 0x0001
139#define TPD_INS_VTAG_SHIFT 15
140#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
141#define TPD_IPV4_PACKET_SHIFT 16
142#define TPD_ETH_TYPE_MASK 0x0001
143#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
144
145/* tpd word 18:25 Custom Checksum task offload */
146#define TPD_CCSUM_OFFSET_MASK 0x00FF
147#define TPD_CCSUM_OFFSET_SHIFT 18
148#define TPD_CCSUM_EPAD_MASK 0x0001
149#define TPD_CCSUM_EPAD_SHIFT 30
150
151/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
152#define TPD_MSS_MASK 0x1FFF
153#define TPD_MSS_SHIFT 18
154
155#define TPD_EOP_MASK 0x0001
156#define TPD_EOP_SHIFT 31
157
158struct atl1c_tpd_desc {
159 __le16 buffer_len; /* include 4-byte CRC */
160 __le16 vlan_tag;
161 __le32 word1;
162 __le64 buffer_addr;
163};
164
165struct atl1c_tpd_ext_desc {
166 u32 reservd_0;
167 __le32 word1;
168 __le32 pkt_len;
169 u32 reservd_1;
170};
171/* rrs word 0 bit 0:31 */
172#define RRS_RX_CSUM_MASK 0xFFFF
173#define RRS_RX_CSUM_SHIFT 0
174#define RRS_RX_RFD_CNT_MASK 0x000F
175#define RRS_RX_RFD_CNT_SHIFT 16
176#define RRS_RX_RFD_INDEX_MASK 0x0FFF
177#define RRS_RX_RFD_INDEX_SHIFT 20
178
179/* rrs flag bit 0:16 */
180#define RRS_HEAD_LEN_MASK 0x00FF
181#define RRS_HEAD_LEN_SHIFT 0
182#define RRS_HDS_TYPE_MASK 0x0003
183#define RRS_HDS_TYPE_SHIFT 8
184#define RRS_CPU_NUM_MASK 0x0003
185#define RRS_CPU_NUM_SHIFT 10
186#define RRS_HASH_FLG_MASK 0x000F
187#define RRS_HASH_FLG_SHIFT 12
188
189#define RRS_HDS_TYPE_HEAD 1
190#define RRS_HDS_TYPE_DATA 2
191
192#define RRS_IS_NO_HDS_TYPE(flag) \
193 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0)
194
195#define RRS_IS_HDS_HEAD(flag) \
196 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
197 RRS_HDS_TYPE_HEAD)
198
199#define RRS_IS_HDS_DATA(flag) \
200 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
201 RRS_HDS_TYPE_DATA)
202
203/* rrs word 3 bit 0:31 */
204#define RRS_PKT_SIZE_MASK 0x3FFF
205#define RRS_PKT_SIZE_SHIFT 0
206#define RRS_ERR_L4_CSUM_MASK 0x0001
207#define RRS_ERR_L4_CSUM_SHIFT 14
208#define RRS_ERR_IP_CSUM_MASK 0x0001
209#define RRS_ERR_IP_CSUM_SHIFT 15
210#define RRS_VLAN_INS_MASK 0x0001
211#define RRS_VLAN_INS_SHIFT 16
212#define RRS_PROT_ID_MASK 0x0007
213#define RRS_PROT_ID_SHIFT 17
214#define RRS_RX_ERR_SUM_MASK 0x0001
215#define RRS_RX_ERR_SUM_SHIFT 20
216#define RRS_RX_ERR_CRC_MASK 0x0001
217#define RRS_RX_ERR_CRC_SHIFT 21
218#define RRS_RX_ERR_FAE_MASK 0x0001
219#define RRS_RX_ERR_FAE_SHIFT 22
220#define RRS_RX_ERR_TRUNC_MASK 0x0001
221#define RRS_RX_ERR_TRUNC_SHIFT 23
222#define RRS_RX_ERR_RUNC_MASK 0x0001
223#define RRS_RX_ERR_RUNC_SHIFT 24
224#define RRS_RX_ERR_ICMP_MASK 0x0001
225#define RRS_RX_ERR_ICMP_SHIFT 25
226#define RRS_PACKET_BCAST_MASK 0x0001
227#define RRS_PACKET_BCAST_SHIFT 26
228#define RRS_PACKET_MCAST_MASK 0x0001
229#define RRS_PACKET_MCAST_SHIFT 27
230#define RRS_PACKET_TYPE_MASK 0x0001
231#define RRS_PACKET_TYPE_SHIFT 28
232#define RRS_FIFO_FULL_MASK 0x0001
233#define RRS_FIFO_FULL_SHIFT 29
234#define RRS_802_3_LEN_ERR_MASK 0x0001
235#define RRS_802_3_LEN_ERR_SHIFT 30
236#define RRS_RXD_UPDATED_MASK 0x0001
237#define RRS_RXD_UPDATED_SHIFT 31
238
239#define RRS_ERR_L4_CSUM 0x00004000
240#define RRS_ERR_IP_CSUM 0x00008000
241#define RRS_VLAN_INS 0x00010000
242#define RRS_RX_ERR_SUM 0x00100000
243#define RRS_RX_ERR_CRC 0x00200000
244#define RRS_802_3_LEN_ERR 0x40000000
245#define RRS_RXD_UPDATED 0x80000000
246
247#define RRS_PACKET_TYPE_802_3 1
248#define RRS_PACKET_TYPE_ETH 0
249#define RRS_PACKET_IS_ETH(word) \
250 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \
251 RRS_PACKET_TYPE_ETH)
252#define RRS_RXD_IS_VALID(word) \
253 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
254
255#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
256 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
257#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
258 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
259
260struct atl1c_recv_ret_status {
261 __le32 word0;
262 __le32 rss_hash;
263 __le16 vlan_tag;
264 __le16 flag;
265 __le32 word3;
266};
267
268/* RFD descriptor */
269struct atl1c_rx_free_desc {
270 __le64 buffer_addr;
271};
272
273/* DMA Order Settings */
274enum atl1c_dma_order {
275 atl1c_dma_ord_in = 1,
276 atl1c_dma_ord_enh = 2,
277 atl1c_dma_ord_out = 4
278};
279
280enum atl1c_dma_rcb {
281 atl1c_rcb_64 = 0,
282 atl1c_rcb_128 = 1
283};
284
285enum atl1c_mac_speed {
286 atl1c_mac_speed_0 = 0,
287 atl1c_mac_speed_10_100 = 1,
288 atl1c_mac_speed_1000 = 2
289};
290
291enum atl1c_dma_req_block {
292 atl1c_dma_req_128 = 0,
293 atl1c_dma_req_256 = 1,
294 atl1c_dma_req_512 = 2,
295 atl1c_dma_req_1024 = 3,
296 atl1c_dma_req_2048 = 4,
297 atl1c_dma_req_4096 = 5
298};
299
300enum atl1c_rss_mode {
301 atl1c_rss_mode_disable = 0,
302 atl1c_rss_sig_que = 1,
303 atl1c_rss_mul_que_sig_int = 2,
304 atl1c_rss_mul_que_mul_int = 4,
305};
306
307enum atl1c_rss_type {
308 atl1c_rss_disable = 0,
309 atl1c_rss_ipv4 = 1,
310 atl1c_rss_ipv4_tcp = 2,
311 atl1c_rss_ipv6 = 4,
312 atl1c_rss_ipv6_tcp = 8
313};
314
315enum atl1c_nic_type {
316 athr_l1c = 0,
317 athr_l2c = 1,
318 athr_l2c_b,
319 athr_l2c_b2,
320 athr_l1d,
321 athr_l1d_2,
322};
323
324enum atl1c_trans_queue {
325 atl1c_trans_normal = 0,
326 atl1c_trans_high = 1
327};
328
329struct atl1c_hw_stats {
330 /* rx */
331 unsigned long rx_ok; /* The number of good packet received. */
332 unsigned long rx_bcast; /* The number of good broadcast packet received. */
333 unsigned long rx_mcast; /* The number of good multicast packet received. */
334 unsigned long rx_pause; /* The number of Pause packet received. */
335 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
336 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
337 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
338 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
339 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
340 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
341 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
342 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
343 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
344 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
345 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
346 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
347 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
348 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
349 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
350 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
351 unsigned long rx_align_err; /* Alignment Error */
352 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
353 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
354 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
355
356 /* tx */
357 unsigned long tx_ok; /* The number of good packet transmitted. */
358 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
359 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
360 unsigned long tx_pause; /* The number of Pause packet transmitted. */
361 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
362 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
363 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
364 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
365 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
366 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
367 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
368 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
369 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
370 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
371 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
372 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
373 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
374 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
375 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
376 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
377 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
378 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
379 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
380 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
381 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
382};
383
384struct atl1c_hw {
385 u8 __iomem *hw_addr; /* inner register address */
386 struct atl1c_adapter *adapter;
387 enum atl1c_nic_type nic_type;
388 enum atl1c_dma_order dma_order;
389 enum atl1c_dma_rcb rcb_value;
390 enum atl1c_dma_req_block dmar_block;
391 enum atl1c_dma_req_block dmaw_block;
392
393 u16 device_id;
394 u16 vendor_id;
395 u16 subsystem_id;
396 u16 subsystem_vendor_id;
397 u8 revision_id;
398 u16 phy_id1;
399 u16 phy_id2;
400
401 u32 intr_mask;
402 u8 dmaw_dly_cnt;
403 u8 dmar_dly_cnt;
404
405 u8 preamble_len;
406 u16 max_frame_size;
407 u16 min_frame_size;
408
409 enum atl1c_mac_speed mac_speed;
410 bool mac_duplex;
411 bool hibernate;
412 u16 media_type;
413#define MEDIA_TYPE_AUTO_SENSOR 0
414#define MEDIA_TYPE_100M_FULL 1
415#define MEDIA_TYPE_100M_HALF 2
416#define MEDIA_TYPE_10M_FULL 3
417#define MEDIA_TYPE_10M_HALF 4
418
419 u16 autoneg_advertised;
420 u16 mii_autoneg_adv_reg;
421 u16 mii_1000t_ctrl_reg;
422
423 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */
424 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */
425 u16 ict; /* Interrupt Clear timer (2us resolution) */
426 u16 ctrl_flags;
427#define ATL1C_INTR_CLEAR_ON_READ 0x0001
428#define ATL1C_INTR_MODRT_ENABLE 0x0002
429#define ATL1C_CMB_ENABLE 0x0004
430#define ATL1C_SMB_ENABLE 0x0010
431#define ATL1C_TXQ_MODE_ENHANCE 0x0020
432#define ATL1C_RX_IPV6_CHKSUM 0x0040
433#define ATL1C_ASPM_L0S_SUPPORT 0x0080
434#define ATL1C_ASPM_L1_SUPPORT 0x0100
435#define ATL1C_ASPM_CTRL_MON 0x0200
436#define ATL1C_HIB_DISABLE 0x0400
437#define ATL1C_APS_MODE_ENABLE 0x0800
438#define ATL1C_LINK_EXT_SYNC 0x1000
439#define ATL1C_CLK_GATING_EN 0x2000
440#define ATL1C_FPGA_VERSION 0x8000
441 u16 link_cap_flags;
442#define ATL1C_LINK_CAP_1000M 0x0001
443 u16 cmb_tpd;
444 u16 cmb_rrd;
445 u16 cmb_rx_timer; /* 2us resolution */
446 u16 cmb_tx_timer;
447 u32 smb_timer;
448
449 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
450 interrupt request */
451 u16 tpd_thresh;
452 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
453 u8 rfd_burst;
454 enum atl1c_rss_type rss_type;
455 enum atl1c_rss_mode rss_mode;
456 u8 rss_hash_bits;
457 u32 base_cpu;
458 u32 indirect_tab;
459 u8 mac_addr[ETH_ALEN];
460 u8 perm_mac_addr[ETH_ALEN];
461
462 bool phy_configured;
463 bool re_autoneg;
464 bool emi_ca;
465};
466
467/*
468 * atl1c_ring_header represents a single, contiguous block of DMA space
469 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
470 * message blocks (cmb, smb) described below
471 */
472struct atl1c_ring_header {
473 void *desc; /* virtual address */
474 dma_addr_t dma; /* physical address*/
475 unsigned int size; /* length in bytes */
476};
477
478/*
479 * atl1c_buffer is wrapper around a pointer to a socket buffer
480 * so a DMA handle can be stored along with the skb
481 */
482struct atl1c_buffer {
483 struct sk_buff *skb; /* socket buffer */
484 u16 length; /* rx buffer length */
485 u16 flags; /* information of buffer */
486#define ATL1C_BUFFER_FREE 0x0001
487#define ATL1C_BUFFER_BUSY 0x0002
488#define ATL1C_BUFFER_STATE_MASK 0x0003
489
490#define ATL1C_PCIMAP_SINGLE 0x0004
491#define ATL1C_PCIMAP_PAGE 0x0008
492#define ATL1C_PCIMAP_TYPE_MASK 0x000C
493
494#define ATL1C_PCIMAP_TODEVICE 0x0010
495#define ATL1C_PCIMAP_FROMDEVICE 0x0020
496#define ATL1C_PCIMAP_DIRECTION_MASK 0x0030
497 dma_addr_t dma;
498};
499
500#define ATL1C_SET_BUFFER_STATE(buff, state) do { \
501 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \
502 ((buff)->flags) |= (state); \
503 } while (0)
504
505#define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \
506 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \
507 ((buff)->flags) |= (type); \
508 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \
509 ((buff)->flags) |= (direction); \
510 } while (0)
511
512/* transimit packet descriptor (tpd) ring */
513struct atl1c_tpd_ring {
514 void *desc; /* descriptor ring virtual address */
515 dma_addr_t dma; /* descriptor ring physical address */
516 u16 size; /* descriptor ring length in bytes */
517 u16 count; /* number of descriptors in the ring */
518 u16 next_to_use; /* this is protectd by adapter->tx_lock */
519 atomic_t next_to_clean;
520 struct atl1c_buffer *buffer_info;
521};
522
523/* receive free descriptor (rfd) ring */
524struct atl1c_rfd_ring {
525 void *desc; /* descriptor ring virtual address */
526 dma_addr_t dma; /* descriptor ring physical address */
527 u16 size; /* descriptor ring length in bytes */
528 u16 count; /* number of descriptors in the ring */
529 u16 next_to_use;
530 u16 next_to_clean;
531 struct atl1c_buffer *buffer_info;
532};
533
534/* receive return descriptor (rrd) ring */
535struct atl1c_rrd_ring {
536 void *desc; /* descriptor ring virtual address */
537 dma_addr_t dma; /* descriptor ring physical address */
538 u16 size; /* descriptor ring length in bytes */
539 u16 count; /* number of descriptors in the ring */
540 u16 next_to_use;
541 u16 next_to_clean;
542};
543
544struct atl1c_cmb {
545 void *cmb;
546 dma_addr_t dma;
547};
548
549struct atl1c_smb {
550 void *smb;
551 dma_addr_t dma;
552};
553
554/* board specific private data structure */
555struct atl1c_adapter {
556 struct net_device *netdev;
557 struct pci_dev *pdev;
558 struct napi_struct napi;
559 struct atl1c_hw hw;
560 struct atl1c_hw_stats hw_stats;
561 struct mii_if_info mii; /* MII interface info */
562 u16 rx_buffer_len;
563
564 unsigned long flags;
565#define __AT_TESTING 0x0001
566#define __AT_RESETTING 0x0002
567#define __AT_DOWN 0x0003
568 unsigned long work_event;
569#define ATL1C_WORK_EVENT_RESET 0
570#define ATL1C_WORK_EVENT_LINK_CHANGE 1
571 u32 msg_enable;
572
573 bool have_msi;
574 u32 wol;
575 u16 link_speed;
576 u16 link_duplex;
577
578 spinlock_t mdio_lock;
579 spinlock_t tx_lock;
580 atomic_t irq_sem;
581
582 struct work_struct common_task;
583 struct timer_list watchdog_timer;
584 struct timer_list phy_config_timer;
585
586 /* All Descriptor memory */
587 struct atl1c_ring_header ring_header;
588 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
589 struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
590 struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
591 struct atl1c_cmb cmb;
592 struct atl1c_smb smb;
593 int num_rx_queues;
594 u32 bd_number; /* board number;*/
595};
596
597#define AT_WRITE_REG(a, reg, value) ( \
598 writel((value), ((a)->hw_addr + reg)))
599
600#define AT_WRITE_FLUSH(a) (\
601 readl((a)->hw_addr))
602
603#define AT_READ_REG(a, reg, pdata) do { \
604 if (unlikely((a)->hibernate)) { \
605 readl((a)->hw_addr + reg); \
606 *(u32 *)pdata = readl((a)->hw_addr + reg); \
607 } else { \
608 *(u32 *)pdata = readl((a)->hw_addr + reg); \
609 } \
610 } while (0)
611
612#define AT_WRITE_REGB(a, reg, value) (\
613 writeb((value), ((a)->hw_addr + reg)))
614
615#define AT_READ_REGB(a, reg) (\
616 readb((a)->hw_addr + reg))
617
618#define AT_WRITE_REGW(a, reg, value) (\
619 writew((value), ((a)->hw_addr + reg)))
620
621#define AT_READ_REGW(a, reg) (\
622 readw((a)->hw_addr + reg))
623
624#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
625 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
626
627#define AT_READ_REG_ARRAY(a, reg, offset) ( \
628 readl(((a)->hw_addr + reg) + ((offset) << 2)))
629
630extern char atl1c_driver_name[];
631extern char atl1c_driver_version[];
632
633extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
634extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
635extern void atl1c_set_ethtool_ops(struct net_device *netdev);
636#endif /* _ATL1C_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 14:43:25 -0500