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authorJay Cliburn <jacliburn@bellsouth.net>2008-02-02 20:50:03 -0500
committerJeff Garzik <jeff@garzik.org>2008-03-17 07:49:23 -0400
commit2e5071bce5ce4037ce852a916e8106811e68677b (patch)
treee6bba6946c6e8ebe51b28a6f5b3251a5fcddbb4e /drivers/net/atl1
parentfa6557aff47f25e5b6b92c930a9b60a12acd0b58 (diff)
atl1: relocate atl1 driver to /drivers/net/atlx
In preparation for a future Atheros L2 NIC driver (called atl2), relocate the atl1 driver into a new /drivers/net/atlx directory that will ultimately be shared with the future atl2 driver. Signed-off-by: Chris Snook <csnook@redhat.com> Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/atl1')
-rw-r--r--drivers/net/atl1/Makefile2
-rw-r--r--drivers/net/atl1/atl1.h286
-rw-r--r--drivers/net/atl1/atl1_ethtool.c505
-rw-r--r--drivers/net/atl1/atl1_hw.c720
-rw-r--r--drivers/net/atl1/atl1_hw.h946
-rw-r--r--drivers/net/atl1/atl1_main.c2453
-rw-r--r--drivers/net/atl1/atl1_param.c203
7 files changed, 0 insertions, 5115 deletions
diff --git a/drivers/net/atl1/Makefile b/drivers/net/atl1/Makefile
deleted file mode 100644
index a6b707e4e69e..000000000000
--- a/drivers/net/atl1/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ATL1) += atl1.o
2atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
diff --git a/drivers/net/atl1/atl1.h b/drivers/net/atl1/atl1.h
deleted file mode 100644
index ff4765f6c3de..000000000000
--- a/drivers/net/atl1/atl1.h
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef _ATL1_H_
25#define _ATL1_H_
26
27#include <linux/types.h>
28#include <linux/if_vlan.h>
29
30#include "atl1_hw.h"
31
32/* function prototypes needed by multiple files */
33s32 atl1_up(struct atl1_adapter *adapter);
34void atl1_down(struct atl1_adapter *adapter);
35int atl1_reset(struct atl1_adapter *adapter);
36s32 atl1_setup_ring_resources(struct atl1_adapter *adapter);
37void atl1_free_ring_resources(struct atl1_adapter *adapter);
38
39extern char atl1_driver_name[];
40extern char atl1_driver_version[];
41extern const struct ethtool_ops atl1_ethtool_ops;
42
43struct atl1_adapter;
44
45#define ATL1_MAX_INTR 3
46#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
47
48#define ATL1_DEFAULT_TPD 256
49#define ATL1_MAX_TPD 1024
50#define ATL1_MIN_TPD 64
51#define ATL1_DEFAULT_RFD 512
52#define ATL1_MIN_RFD 128
53#define ATL1_MAX_RFD 2048
54
55#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
56#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
57#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
58#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
59
60/*
61 * This detached comment is preserved for documentation purposes only.
62 * It was originally attached to some code that got deleted, but seems
63 * important enough to keep around...
64 *
65 * <begin detached comment>
66 * Some workarounds require millisecond delays and are run during interrupt
67 * context. Most notably, when establishing link, the phy may need tweaking
68 * but cannot process phy register reads/writes faster than millisecond
69 * intervals...and we establish link due to a "link status change" interrupt.
70 * <end detached comment>
71 */
72
73/*
74 * atl1_ring_header represents a single, contiguous block of DMA space
75 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
76 * message blocks (cmb, smb) described below
77 */
78struct atl1_ring_header {
79 void *desc; /* virtual address */
80 dma_addr_t dma; /* physical address*/
81 unsigned int size; /* length in bytes */
82};
83
84/*
85 * atl1_buffer is wrapper around a pointer to a socket buffer
86 * so a DMA handle can be stored along with the skb
87 */
88struct atl1_buffer {
89 struct sk_buff *skb; /* socket buffer */
90 u16 length; /* rx buffer length */
91 u16 alloced; /* 1 if skb allocated */
92 dma_addr_t dma;
93};
94
95/* transmit packet descriptor (tpd) ring */
96struct atl1_tpd_ring {
97 void *desc; /* descriptor ring virtual address */
98 dma_addr_t dma; /* descriptor ring physical address */
99 u16 size; /* descriptor ring length in bytes */
100 u16 count; /* number of descriptors in the ring */
101 u16 hw_idx; /* hardware index */
102 atomic_t next_to_clean;
103 atomic_t next_to_use;
104 struct atl1_buffer *buffer_info;
105};
106
107/* receive free descriptor (rfd) ring */
108struct atl1_rfd_ring {
109 void *desc; /* descriptor ring virtual address */
110 dma_addr_t dma; /* descriptor ring physical address */
111 u16 size; /* descriptor ring length in bytes */
112 u16 count; /* number of descriptors in the ring */
113 atomic_t next_to_use;
114 u16 next_to_clean;
115 struct atl1_buffer *buffer_info;
116};
117
118/* receive return descriptor (rrd) ring */
119struct atl1_rrd_ring {
120 void *desc; /* descriptor ring virtual address */
121 dma_addr_t dma; /* descriptor ring physical address */
122 unsigned int size; /* descriptor ring length in bytes */
123 u16 count; /* number of descriptors in the ring */
124 u16 next_to_use;
125 atomic_t next_to_clean;
126};
127
128/* coalescing message block (cmb) */
129struct atl1_cmb {
130 struct coals_msg_block *cmb;
131 dma_addr_t dma;
132};
133
134/* statistics message block (smb) */
135struct atl1_smb {
136 struct stats_msg_block *smb;
137 dma_addr_t dma;
138};
139
140/* Statistics counters */
141struct atl1_sft_stats {
142 u64 rx_packets;
143 u64 tx_packets;
144 u64 rx_bytes;
145 u64 tx_bytes;
146 u64 multicast;
147 u64 collisions;
148 u64 rx_errors;
149 u64 rx_length_errors;
150 u64 rx_crc_errors;
151 u64 rx_frame_errors;
152 u64 rx_fifo_errors;
153 u64 rx_missed_errors;
154 u64 tx_errors;
155 u64 tx_fifo_errors;
156 u64 tx_aborted_errors;
157 u64 tx_window_errors;
158 u64 tx_carrier_errors;
159 u64 tx_pause; /* num pause packets transmitted. */
160 u64 excecol; /* num tx packets w/ excessive collisions. */
161 u64 deffer; /* num tx packets deferred */
162 u64 scc; /* num packets subsequently transmitted
163 * successfully w/ single prior collision. */
164 u64 mcc; /* num packets subsequently transmitted
165 * successfully w/ multiple prior collisions. */
166 u64 latecol; /* num tx packets w/ late collisions. */
167 u64 tx_underun; /* num tx packets aborted due to transmit
168 * FIFO underrun, or TRD FIFO underrun */
169 u64 tx_trunc; /* num tx packets truncated due to size
170 * exceeding MTU, regardless whether truncated
171 * by the chip or not. (The name doesn't really
172 * reflect the meaning in this case.) */
173 u64 rx_pause; /* num Pause packets received. */
174 u64 rx_rrd_ov;
175 u64 rx_trunc;
176};
177
178/* hardware structure */
179struct atl1_hw {
180 u8 __iomem *hw_addr;
181 struct atl1_adapter *back;
182 enum atl1_dma_order dma_ord;
183 enum atl1_dma_rcb rcb_value;
184 enum atl1_dma_req_block dmar_block;
185 enum atl1_dma_req_block dmaw_block;
186 u8 preamble_len;
187 u8 max_retry; /* Retransmission maximum, after which the
188 * packet will be discarded */
189 u8 jam_ipg; /* IPG to start JAM for collision based flow
190 * control in half-duplex mode. In units of
191 * 8-bit time */
192 u8 ipgt; /* Desired back to back inter-packet gap.
193 * The default is 96-bit time */
194 u8 min_ifg; /* Minimum number of IFG to enforce in between
195 * receive frames. Frame gap below such IFP
196 * is dropped */
197 u8 ipgr1; /* 64bit Carrier-Sense window */
198 u8 ipgr2; /* 96-bit IPG window */
199 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
200 * burst. Each TPD is 16 bytes long */
201 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
202 * burst. Each RFD is 12 bytes long */
203 u8 rfd_fetch_gap;
204 u8 rrd_burst; /* Threshold number of RRDs that can be retired
205 * in a burst. Each RRD is 16 bytes long */
206 u8 tpd_fetch_th;
207 u8 tpd_fetch_gap;
208 u16 tx_jumbo_task_th;
209 u16 txf_burst; /* Number of data bytes to read in a cache-
210 * aligned burst. Each SRAM entry is 8 bytes */
211 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
212 * packets should add 4 bytes */
213 u16 rx_jumbo_lkah;
214 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
215 * every 512ns passes. */
216 u16 lcol; /* Collision Window */
217
218 u16 cmb_tpd;
219 u16 cmb_rrd;
220 u16 cmb_rx_timer;
221 u16 cmb_tx_timer;
222 u32 smb_timer;
223 u16 media_type;
224 u16 autoneg_advertised;
225
226 u16 mii_autoneg_adv_reg;
227 u16 mii_1000t_ctrl_reg;
228
229 u32 max_frame_size;
230 u32 min_frame_size;
231
232 u16 dev_rev;
233
234 /* spi flash */
235 u8 flash_vendor;
236
237 u8 mac_addr[ETH_ALEN];
238 u8 perm_mac_addr[ETH_ALEN];
239
240 bool phy_configured;
241};
242
243struct atl1_adapter {
244 struct net_device *netdev;
245 struct pci_dev *pdev;
246 struct net_device_stats net_stats;
247 struct atl1_sft_stats soft_stats;
248 struct vlan_group *vlgrp;
249 u32 rx_buffer_len;
250 u32 wol;
251 u16 link_speed;
252 u16 link_duplex;
253 spinlock_t lock;
254 struct work_struct tx_timeout_task;
255 struct work_struct link_chg_task;
256 struct work_struct pcie_dma_to_rst_task;
257 struct timer_list watchdog_timer;
258 struct timer_list phy_config_timer;
259 bool phy_timer_pending;
260
261 /* all descriptor rings' memory */
262 struct atl1_ring_header ring_header;
263
264 /* TX */
265 struct atl1_tpd_ring tpd_ring;
266 spinlock_t mb_lock;
267
268 /* RX */
269 struct atl1_rfd_ring rfd_ring;
270 struct atl1_rrd_ring rrd_ring;
271 u64 hw_csum_err;
272 u64 hw_csum_good;
273
274 u16 imt; /* interrupt moderator timer (2us resolution */
275 u16 ict; /* interrupt clear timer (2us resolution */
276 struct mii_if_info mii; /* MII interface info */
277
278 /* structs defined in atl1_hw.h */
279 u32 bd_number; /* board number */
280 bool pci_using_64;
281 struct atl1_hw hw;
282 struct atl1_smb smb;
283 struct atl1_cmb cmb;
284};
285
286#endif /* _ATL1_H_ */
diff --git a/drivers/net/atl1/atl1_ethtool.c b/drivers/net/atl1/atl1_ethtool.c
deleted file mode 100644
index 68a83be843ab..000000000000
--- a/drivers/net/atl1/atl1_ethtool.c
+++ /dev/null
@@ -1,505 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/ethtool.h>
27#include <linux/netdevice.h>
28#include <linux/mii.h>
29#include <asm/uaccess.h>
30
31#include "atl1.h"
32
33struct atl1_stats {
34 char stat_string[ETH_GSTRING_LEN];
35 int sizeof_stat;
36 int stat_offset;
37};
38
39#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
40 offsetof(struct atl1_adapter, m)
41
42static struct atl1_stats atl1_gstrings_stats[] = {
43 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
44 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
45 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
46 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
47 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
48 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
49 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
50 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
51 {"multicast", ATL1_STAT(soft_stats.multicast)},
52 {"collisions", ATL1_STAT(soft_stats.collisions)},
53 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
54 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
55 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
56 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
57 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
58 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
59 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
60 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
61 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
62 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
63 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
64 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
65 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
66 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
67 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
68 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
69 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
70 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
71 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
72 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
73 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
74};
75
76static void atl1_get_ethtool_stats(struct net_device *netdev,
77 struct ethtool_stats *stats, u64 *data)
78{
79 struct atl1_adapter *adapter = netdev_priv(netdev);
80 int i;
81 char *p;
82
83 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
84 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
85 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
86 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
87 }
88
89}
90
91static int atl1_get_sset_count(struct net_device *netdev, int sset)
92{
93 switch (sset) {
94 case ETH_SS_STATS:
95 return ARRAY_SIZE(atl1_gstrings_stats);
96 default:
97 return -EOPNOTSUPP;
98 }
99}
100
101static int atl1_get_settings(struct net_device *netdev,
102 struct ethtool_cmd *ecmd)
103{
104 struct atl1_adapter *adapter = netdev_priv(netdev);
105 struct atl1_hw *hw = &adapter->hw;
106
107 ecmd->supported = (SUPPORTED_10baseT_Half |
108 SUPPORTED_10baseT_Full |
109 SUPPORTED_100baseT_Half |
110 SUPPORTED_100baseT_Full |
111 SUPPORTED_1000baseT_Full |
112 SUPPORTED_Autoneg | SUPPORTED_TP);
113 ecmd->advertising = ADVERTISED_TP;
114 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
115 hw->media_type == MEDIA_TYPE_1000M_FULL) {
116 ecmd->advertising |= ADVERTISED_Autoneg;
117 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
118 ecmd->advertising |= ADVERTISED_Autoneg;
119 ecmd->advertising |=
120 (ADVERTISED_10baseT_Half |
121 ADVERTISED_10baseT_Full |
122 ADVERTISED_100baseT_Half |
123 ADVERTISED_100baseT_Full |
124 ADVERTISED_1000baseT_Full);
125 }
126 else
127 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
128 }
129 ecmd->port = PORT_TP;
130 ecmd->phy_address = 0;
131 ecmd->transceiver = XCVR_INTERNAL;
132
133 if (netif_carrier_ok(adapter->netdev)) {
134 u16 link_speed, link_duplex;
135 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
136 ecmd->speed = link_speed;
137 if (link_duplex == FULL_DUPLEX)
138 ecmd->duplex = DUPLEX_FULL;
139 else
140 ecmd->duplex = DUPLEX_HALF;
141 } else {
142 ecmd->speed = -1;
143 ecmd->duplex = -1;
144 }
145 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
146 hw->media_type == MEDIA_TYPE_1000M_FULL)
147 ecmd->autoneg = AUTONEG_ENABLE;
148 else
149 ecmd->autoneg = AUTONEG_DISABLE;
150
151 return 0;
152}
153
154static int atl1_set_settings(struct net_device *netdev,
155 struct ethtool_cmd *ecmd)
156{
157 struct atl1_adapter *adapter = netdev_priv(netdev);
158 struct atl1_hw *hw = &adapter->hw;
159 u16 phy_data;
160 int ret_val = 0;
161 u16 old_media_type = hw->media_type;
162
163 if (netif_running(adapter->netdev)) {
164 dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
165 atl1_down(adapter);
166 }
167
168 if (ecmd->autoneg == AUTONEG_ENABLE)
169 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
170 else {
171 if (ecmd->speed == SPEED_1000) {
172 if (ecmd->duplex != DUPLEX_FULL) {
173 dev_warn(&adapter->pdev->dev,
174 "can't force to 1000M half duplex\n");
175 ret_val = -EINVAL;
176 goto exit_sset;
177 }
178 hw->media_type = MEDIA_TYPE_1000M_FULL;
179 } else if (ecmd->speed == SPEED_100) {
180 if (ecmd->duplex == DUPLEX_FULL) {
181 hw->media_type = MEDIA_TYPE_100M_FULL;
182 } else
183 hw->media_type = MEDIA_TYPE_100M_HALF;
184 } else {
185 if (ecmd->duplex == DUPLEX_FULL)
186 hw->media_type = MEDIA_TYPE_10M_FULL;
187 else
188 hw->media_type = MEDIA_TYPE_10M_HALF;
189 }
190 }
191 switch (hw->media_type) {
192 case MEDIA_TYPE_AUTO_SENSOR:
193 ecmd->advertising =
194 ADVERTISED_10baseT_Half |
195 ADVERTISED_10baseT_Full |
196 ADVERTISED_100baseT_Half |
197 ADVERTISED_100baseT_Full |
198 ADVERTISED_1000baseT_Full |
199 ADVERTISED_Autoneg | ADVERTISED_TP;
200 break;
201 case MEDIA_TYPE_1000M_FULL:
202 ecmd->advertising =
203 ADVERTISED_1000baseT_Full |
204 ADVERTISED_Autoneg | ADVERTISED_TP;
205 break;
206 default:
207 ecmd->advertising = 0;
208 break;
209 }
210 if (atl1_phy_setup_autoneg_adv(hw)) {
211 ret_val = -EINVAL;
212 dev_warn(&adapter->pdev->dev,
213 "invalid ethtool speed/duplex setting\n");
214 goto exit_sset;
215 }
216 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
217 hw->media_type == MEDIA_TYPE_1000M_FULL)
218 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
219 else {
220 switch (hw->media_type) {
221 case MEDIA_TYPE_100M_FULL:
222 phy_data =
223 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
224 MII_CR_RESET;
225 break;
226 case MEDIA_TYPE_100M_HALF:
227 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
228 break;
229 case MEDIA_TYPE_10M_FULL:
230 phy_data =
231 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
232 break;
233 default: /* MEDIA_TYPE_10M_HALF: */
234 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
235 break;
236 }
237 }
238 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
239exit_sset:
240 if (ret_val)
241 hw->media_type = old_media_type;
242
243 if (netif_running(adapter->netdev)) {
244 dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
245 atl1_up(adapter);
246 } else if (!ret_val) {
247 dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
248 atl1_reset(adapter);
249 }
250 return ret_val;
251}
252
253static void atl1_get_drvinfo(struct net_device *netdev,
254 struct ethtool_drvinfo *drvinfo)
255{
256 struct atl1_adapter *adapter = netdev_priv(netdev);
257
258 strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
259 strncpy(drvinfo->version, atl1_driver_version,
260 sizeof(drvinfo->version));
261 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
262 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
263 sizeof(drvinfo->bus_info));
264 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
265}
266
267static void atl1_get_wol(struct net_device *netdev,
268 struct ethtool_wolinfo *wol)
269{
270 struct atl1_adapter *adapter = netdev_priv(netdev);
271
272 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
273 wol->wolopts = 0;
274 if (adapter->wol & ATL1_WUFC_EX)
275 wol->wolopts |= WAKE_UCAST;
276 if (adapter->wol & ATL1_WUFC_MC)
277 wol->wolopts |= WAKE_MCAST;
278 if (adapter->wol & ATL1_WUFC_BC)
279 wol->wolopts |= WAKE_BCAST;
280 if (adapter->wol & ATL1_WUFC_MAG)
281 wol->wolopts |= WAKE_MAGIC;
282 return;
283}
284
285static int atl1_set_wol(struct net_device *netdev,
286 struct ethtool_wolinfo *wol)
287{
288 struct atl1_adapter *adapter = netdev_priv(netdev);
289
290 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
291 return -EOPNOTSUPP;
292 adapter->wol = 0;
293 if (wol->wolopts & WAKE_UCAST)
294 adapter->wol |= ATL1_WUFC_EX;
295 if (wol->wolopts & WAKE_MCAST)
296 adapter->wol |= ATL1_WUFC_MC;
297 if (wol->wolopts & WAKE_BCAST)
298 adapter->wol |= ATL1_WUFC_BC;
299 if (wol->wolopts & WAKE_MAGIC)
300 adapter->wol |= ATL1_WUFC_MAG;
301 return 0;
302}
303
304static void atl1_get_ringparam(struct net_device *netdev,
305 struct ethtool_ringparam *ring)
306{
307 struct atl1_adapter *adapter = netdev_priv(netdev);
308 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
309 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
310
311 ring->rx_max_pending = ATL1_MAX_RFD;
312 ring->tx_max_pending = ATL1_MAX_TPD;
313 ring->rx_mini_max_pending = 0;
314 ring->rx_jumbo_max_pending = 0;
315 ring->rx_pending = rxdr->count;
316 ring->tx_pending = txdr->count;
317 ring->rx_mini_pending = 0;
318 ring->rx_jumbo_pending = 0;
319}
320
321static int atl1_set_ringparam(struct net_device *netdev,
322 struct ethtool_ringparam *ring)
323{
324 struct atl1_adapter *adapter = netdev_priv(netdev);
325 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
326 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
327 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
328
329 struct atl1_tpd_ring tpd_old, tpd_new;
330 struct atl1_rfd_ring rfd_old, rfd_new;
331 struct atl1_rrd_ring rrd_old, rrd_new;
332 struct atl1_ring_header rhdr_old, rhdr_new;
333 int err;
334
335 tpd_old = adapter->tpd_ring;
336 rfd_old = adapter->rfd_ring;
337 rrd_old = adapter->rrd_ring;
338 rhdr_old = adapter->ring_header;
339
340 if (netif_running(adapter->netdev))
341 atl1_down(adapter);
342
343 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
344 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
345 rfdr->count;
346 rfdr->count = (rfdr->count + 3) & ~3;
347 rrdr->count = rfdr->count;
348
349 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
350 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
351 tpdr->count;
352 tpdr->count = (tpdr->count + 3) & ~3;
353
354 if (netif_running(adapter->netdev)) {
355 /* try to get new resources before deleting old */
356 err = atl1_setup_ring_resources(adapter);
357 if (err)
358 goto err_setup_ring;
359
360 /*
361 * save the new, restore the old in order to free it,
362 * then restore the new back again
363 */
364
365 rfd_new = adapter->rfd_ring;
366 rrd_new = adapter->rrd_ring;
367 tpd_new = adapter->tpd_ring;
368 rhdr_new = adapter->ring_header;
369 adapter->rfd_ring = rfd_old;
370 adapter->rrd_ring = rrd_old;
371 adapter->tpd_ring = tpd_old;
372 adapter->ring_header = rhdr_old;
373 atl1_free_ring_resources(adapter);
374 adapter->rfd_ring = rfd_new;
375 adapter->rrd_ring = rrd_new;
376 adapter->tpd_ring = tpd_new;
377 adapter->ring_header = rhdr_new;
378
379 err = atl1_up(adapter);
380 if (err)
381 return err;
382 }
383 return 0;
384
385err_setup_ring:
386 adapter->rfd_ring = rfd_old;
387 adapter->rrd_ring = rrd_old;
388 adapter->tpd_ring = tpd_old;
389 adapter->ring_header = rhdr_old;
390 atl1_up(adapter);
391 return err;
392}
393
394static void atl1_get_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *epause)
396{
397 struct atl1_adapter *adapter = netdev_priv(netdev);
398 struct atl1_hw *hw = &adapter->hw;
399
400 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
401 hw->media_type == MEDIA_TYPE_1000M_FULL) {
402 epause->autoneg = AUTONEG_ENABLE;
403 } else {
404 epause->autoneg = AUTONEG_DISABLE;
405 }
406 epause->rx_pause = 1;
407 epause->tx_pause = 1;
408}
409
410static int atl1_set_pauseparam(struct net_device *netdev,
411 struct ethtool_pauseparam *epause)
412{
413 struct atl1_adapter *adapter = netdev_priv(netdev);
414 struct atl1_hw *hw = &adapter->hw;
415
416 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
417 hw->media_type == MEDIA_TYPE_1000M_FULL) {
418 epause->autoneg = AUTONEG_ENABLE;
419 } else {
420 epause->autoneg = AUTONEG_DISABLE;
421 }
422
423 epause->rx_pause = 1;
424 epause->tx_pause = 1;
425
426 return 0;
427}
428
429static u32 atl1_get_rx_csum(struct net_device *netdev)
430{
431 return 1;
432}
433
434static void atl1_get_strings(struct net_device *netdev, u32 stringset,
435 u8 *data)
436{
437 u8 *p = data;
438 int i;
439
440 switch (stringset) {
441 case ETH_SS_STATS:
442 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
443 memcpy(p, atl1_gstrings_stats[i].stat_string,
444 ETH_GSTRING_LEN);
445 p += ETH_GSTRING_LEN;
446 }
447 break;
448 }
449}
450
451static int atl1_nway_reset(struct net_device *netdev)
452{
453 struct atl1_adapter *adapter = netdev_priv(netdev);
454 struct atl1_hw *hw = &adapter->hw;
455
456 if (netif_running(netdev)) {
457 u16 phy_data;
458 atl1_down(adapter);
459
460 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
461 hw->media_type == MEDIA_TYPE_1000M_FULL) {
462 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
463 } else {
464 switch (hw->media_type) {
465 case MEDIA_TYPE_100M_FULL:
466 phy_data = MII_CR_FULL_DUPLEX |
467 MII_CR_SPEED_100 | MII_CR_RESET;
468 break;
469 case MEDIA_TYPE_100M_HALF:
470 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
471 break;
472 case MEDIA_TYPE_10M_FULL:
473 phy_data = MII_CR_FULL_DUPLEX |
474 MII_CR_SPEED_10 | MII_CR_RESET;
475 break;
476 default: /* MEDIA_TYPE_10M_HALF */
477 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
478 }
479 }
480 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
481 atl1_up(adapter);
482 }
483 return 0;
484}
485
486const struct ethtool_ops atl1_ethtool_ops = {
487 .get_settings = atl1_get_settings,
488 .set_settings = atl1_set_settings,
489 .get_drvinfo = atl1_get_drvinfo,
490 .get_wol = atl1_get_wol,
491 .set_wol = atl1_set_wol,
492 .get_ringparam = atl1_get_ringparam,
493 .set_ringparam = atl1_set_ringparam,
494 .get_pauseparam = atl1_get_pauseparam,
495 .set_pauseparam = atl1_set_pauseparam,
496 .get_rx_csum = atl1_get_rx_csum,
497 .set_tx_csum = ethtool_op_set_tx_hw_csum,
498 .get_link = ethtool_op_get_link,
499 .set_sg = ethtool_op_set_sg,
500 .get_strings = atl1_get_strings,
501 .nway_reset = atl1_nway_reset,
502 .get_ethtool_stats = atl1_get_ethtool_stats,
503 .get_sset_count = atl1_get_sset_count,
504 .set_tso = ethtool_op_set_tso,
505};
diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atl1/atl1_hw.c
deleted file mode 100644
index 9d3bd22e3a82..000000000000
--- a/drivers/net/atl1/atl1_hw.c
+++ /dev/null
@@ -1,720 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 struct pci_dev *pdev = hw->back->pdev;
42 u32 icr;
43 int i;
44
45 /*
46 * Clear Interrupt mask to stop board from generating
47 * interrupts & Clear any pending interrupt events
48 */
49 /*
50 * iowrite32(0, hw->hw_addr + REG_IMR);
51 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
52 */
53
54 /*
55 * Issue Soft Reset to the MAC. This will reset the chip's
56 * transmit, receive, DMA. It will not effect
57 * the current PCI configuration. The global reset bit is self-
58 * clearing, and should clear within a microsecond.
59 */
60 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
61 ioread32(hw->hw_addr + REG_MASTER_CTRL);
62
63 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
64 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
65
66 msleep(1); /* delay about 1ms */
67
68 /* Wait at least 10ms for All module to be Idle */
69 for (i = 0; i < 10; i++) {
70 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
71 if (!icr)
72 break;
73 msleep(1); /* delay 1 ms */
74 cpu_relax(); /* FIXME: is this still the right way to do this? */
75 }
76
77 if (icr) {
78 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
79 return icr;
80 }
81
82 return ATL1_SUCCESS;
83}
84
85/* function about EEPROM
86 *
87 * check_eeprom_exist
88 * return 0 if eeprom exist
89 */
90static int atl1_check_eeprom_exist(struct atl1_hw *hw)
91{
92 u32 value;
93 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
94 if (value & SPI_FLASH_CTRL_EN_VPD) {
95 value &= ~SPI_FLASH_CTRL_EN_VPD;
96 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
97 }
98
99 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
100 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
101}
102
103static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
104{
105 int i;
106 u32 control;
107
108 if (offset & 3)
109 return false; /* address do not align */
110
111 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
112 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
113 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
114 ioread32(hw->hw_addr + REG_VPD_CAP);
115
116 for (i = 0; i < 10; i++) {
117 msleep(2);
118 control = ioread32(hw->hw_addr + REG_VPD_CAP);
119 if (control & VPD_CAP_VPD_FLAG)
120 break;
121 }
122 if (control & VPD_CAP_VPD_FLAG) {
123 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
124 return true;
125 }
126 return false; /* timeout */
127}
128
129/*
130 * Reads the value from a PHY register
131 * hw - Struct containing variables accessed by shared code
132 * reg_addr - address of the PHY register to read
133 */
134s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
135{
136 u32 val;
137 int i;
138
139 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
140 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
141 MDIO_CLK_SEL_SHIFT;
142 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
143 ioread32(hw->hw_addr + REG_MDIO_CTRL);
144
145 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
146 udelay(2);
147 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
148 if (!(val & (MDIO_START | MDIO_BUSY)))
149 break;
150 }
151 if (!(val & (MDIO_START | MDIO_BUSY))) {
152 *phy_data = (u16) val;
153 return ATL1_SUCCESS;
154 }
155 return ATL1_ERR_PHY;
156}
157
158#define CUSTOM_SPI_CS_SETUP 2
159#define CUSTOM_SPI_CLK_HI 2
160#define CUSTOM_SPI_CLK_LO 2
161#define CUSTOM_SPI_CS_HOLD 2
162#define CUSTOM_SPI_CS_HI 3
163
164static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
165{
166 int i;
167 u32 value;
168
169 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
170 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
171
172 value = SPI_FLASH_CTRL_WAIT_READY |
173 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
174 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
175 SPI_FLASH_CTRL_CLK_HI_MASK) <<
176 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
177 SPI_FLASH_CTRL_CLK_LO_MASK) <<
178 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
179 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
180 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
181 SPI_FLASH_CTRL_CS_HI_MASK) <<
182 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
183 SPI_FLASH_CTRL_INS_SHIFT;
184
185 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
186
187 value |= SPI_FLASH_CTRL_START;
188 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
189 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
190
191 for (i = 0; i < 10; i++) {
192 msleep(1); /* 1ms */
193 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
194 if (!(value & SPI_FLASH_CTRL_START))
195 break;
196 }
197
198 if (value & SPI_FLASH_CTRL_START)
199 return false;
200
201 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
202
203 return true;
204}
205
206/*
207 * get_permanent_address
208 * return 0 if get valid mac address,
209 */
210static int atl1_get_permanent_address(struct atl1_hw *hw)
211{
212 u32 addr[2];
213 u32 i, control;
214 u16 reg;
215 u8 eth_addr[ETH_ALEN];
216 bool key_valid;
217
218 if (is_valid_ether_addr(hw->perm_mac_addr))
219 return 0;
220
221 /* init */
222 addr[0] = addr[1] = 0;
223
224 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
225 reg = 0;
226 key_valid = false;
227 /* Read out all EEPROM content */
228 i = 0;
229 while (1) {
230 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
231 if (key_valid) {
232 if (reg == REG_MAC_STA_ADDR)
233 addr[0] = control;
234 else if (reg == (REG_MAC_STA_ADDR + 4))
235 addr[1] = control;
236 key_valid = false;
237 } else if ((control & 0xff) == 0x5A) {
238 key_valid = true;
239 reg = (u16) (control >> 16);
240 } else
241 break; /* assume data end while encount an invalid KEYWORD */
242 } else
243 break; /* read error */
244 i += 4;
245 }
246
247 *(u32 *) &eth_addr[2] = swab32(addr[0]);
248 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
249 if (is_valid_ether_addr(eth_addr)) {
250 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
251 return 0;
252 }
253 return 1;
254 }
255
256 /* see if SPI FLAGS exist ? */
257 addr[0] = addr[1] = 0;
258 reg = 0;
259 key_valid = false;
260 i = 0;
261 while (1) {
262 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
263 if (key_valid) {
264 if (reg == REG_MAC_STA_ADDR)
265 addr[0] = control;
266 else if (reg == (REG_MAC_STA_ADDR + 4))
267 addr[1] = control;
268 key_valid = false;
269 } else if ((control & 0xff) == 0x5A) {
270 key_valid = true;
271 reg = (u16) (control >> 16);
272 } else
273 break; /* data end */
274 } else
275 break; /* read error */
276 i += 4;
277 }
278
279 *(u32 *) &eth_addr[2] = swab32(addr[0]);
280 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
281 if (is_valid_ether_addr(eth_addr)) {
282 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
283 return 0;
284 }
285
286 /*
287 * On some motherboards, the MAC address is written by the
288 * BIOS directly to the MAC register during POST, and is
289 * not stored in eeprom. If all else thus far has failed
290 * to fetch the permanent MAC address, try reading it directly.
291 */
292 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
293 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
294 *(u32 *) &eth_addr[2] = swab32(addr[0]);
295 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
296 if (is_valid_ether_addr(eth_addr)) {
297 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
298 return 0;
299 }
300
301 return 1;
302}
303
304/*
305 * Reads the adapter's MAC address from the EEPROM
306 * hw - Struct containing variables accessed by shared code
307 */
308s32 atl1_read_mac_addr(struct atl1_hw *hw)
309{
310 u16 i;
311
312 if (atl1_get_permanent_address(hw))
313 random_ether_addr(hw->perm_mac_addr);
314
315 for (i = 0; i < ETH_ALEN; i++)
316 hw->mac_addr[i] = hw->perm_mac_addr[i];
317 return ATL1_SUCCESS;
318}
319
320/*
321 * Hashes an address to determine its location in the multicast table
322 * hw - Struct containing variables accessed by shared code
323 * mc_addr - the multicast address to hash
324 *
325 * atl1_hash_mc_addr
326 * purpose
327 * set hash value for a multicast address
328 * hash calcu processing :
329 * 1. calcu 32bit CRC for multicast address
330 * 2. reverse crc with MSB to LSB
331 */
332u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
333{
334 u32 crc32, value = 0;
335 int i;
336
337 crc32 = ether_crc_le(6, mc_addr);
338 for (i = 0; i < 32; i++)
339 value |= (((crc32 >> i) & 1) << (31 - i));
340
341 return value;
342}
343
344/*
345 * Sets the bit in the multicast table corresponding to the hash value.
346 * hw - Struct containing variables accessed by shared code
347 * hash_value - Multicast address hash value
348 */
349void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
350{
351 u32 hash_bit, hash_reg;
352 u32 mta;
353
354 /*
355 * The HASH Table is a register array of 2 32-bit registers.
356 * It is treated like an array of 64 bits. We want to set
357 * bit BitArray[hash_value]. So we figure out what register
358 * the bit is in, read it, OR in the new bit, then write
359 * back the new value. The register is determined by the
360 * upper 7 bits of the hash value and the bit within that
361 * register are determined by the lower 5 bits of the value.
362 */
363 hash_reg = (hash_value >> 31) & 0x1;
364 hash_bit = (hash_value >> 26) & 0x1F;
365 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
366 mta |= (1 << hash_bit);
367 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
368}
369
370/*
371 * Writes a value to a PHY register
372 * hw - Struct containing variables accessed by shared code
373 * reg_addr - address of the PHY register to write
374 * data - data to write to the PHY
375 */
376s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
377{
378 int i;
379 u32 val;
380
381 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
382 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
383 MDIO_SUP_PREAMBLE |
384 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
385 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
386 ioread32(hw->hw_addr + REG_MDIO_CTRL);
387
388 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
389 udelay(2);
390 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
391 if (!(val & (MDIO_START | MDIO_BUSY)))
392 break;
393 }
394
395 if (!(val & (MDIO_START | MDIO_BUSY)))
396 return ATL1_SUCCESS;
397
398 return ATL1_ERR_PHY;
399}
400
401/*
402 * Make L001's PHY out of Power Saving State (bug)
403 * hw - Struct containing variables accessed by shared code
404 * when power on, L001's PHY always on Power saving State
405 * (Gigabit Link forbidden)
406 */
407static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
408{
409 s32 ret;
410 ret = atl1_write_phy_reg(hw, 29, 0x0029);
411 if (ret)
412 return ret;
413 return atl1_write_phy_reg(hw, 30, 0);
414}
415
416/*
417 *TODO: do something or get rid of this
418 */
419s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
420{
421/* s32 ret_val;
422 * u16 phy_data;
423 */
424
425/*
426 ret_val = atl1_write_phy_reg(hw, ...);
427 ret_val = atl1_write_phy_reg(hw, ...);
428 ....
429*/
430 return ATL1_SUCCESS;
431}
432
433/*
434 * Resets the PHY and make all config validate
435 * hw - Struct containing variables accessed by shared code
436 *
437 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
438 */
439static s32 atl1_phy_reset(struct atl1_hw *hw)
440{
441 struct pci_dev *pdev = hw->back->pdev;
442 s32 ret_val;
443 u16 phy_data;
444
445 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
446 hw->media_type == MEDIA_TYPE_1000M_FULL)
447 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
448 else {
449 switch (hw->media_type) {
450 case MEDIA_TYPE_100M_FULL:
451 phy_data =
452 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
453 MII_CR_RESET;
454 break;
455 case MEDIA_TYPE_100M_HALF:
456 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
457 break;
458 case MEDIA_TYPE_10M_FULL:
459 phy_data =
460 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
461 break;
462 default: /* MEDIA_TYPE_10M_HALF: */
463 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
464 break;
465 }
466 }
467
468 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
469 if (ret_val) {
470 u32 val;
471 int i;
472 /* pcie serdes link may be down! */
473 dev_dbg(&pdev->dev, "pcie phy link down\n");
474
475 for (i = 0; i < 25; i++) {
476 msleep(1);
477 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
478 if (!(val & (MDIO_START | MDIO_BUSY)))
479 break;
480 }
481
482 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
483 dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
484 return ret_val;
485 }
486 }
487 return ATL1_SUCCESS;
488}
489
490/*
491 * Configures PHY autoneg and flow control advertisement settings
492 * hw - Struct containing variables accessed by shared code
493 */
494s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
495{
496 s32 ret_val;
497 s16 mii_autoneg_adv_reg;
498 s16 mii_1000t_ctrl_reg;
499
500 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
501 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
502
503 /* Read the MII 1000Base-T Control Register (Address 9). */
504 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
505
506 /*
507 * First we clear all the 10/100 mb speed bits in the Auto-Neg
508 * Advertisement Register (Address 4) and the 1000 mb speed bits in
509 * the 1000Base-T Control Register (Address 9).
510 */
511 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
512 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
513
514 /*
515 * Need to parse media_type and set up
516 * the appropriate PHY registers.
517 */
518 switch (hw->media_type) {
519 case MEDIA_TYPE_AUTO_SENSOR:
520 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
521 MII_AR_10T_FD_CAPS |
522 MII_AR_100TX_HD_CAPS |
523 MII_AR_100TX_FD_CAPS);
524 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
525 break;
526
527 case MEDIA_TYPE_1000M_FULL:
528 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
529 break;
530
531 case MEDIA_TYPE_100M_FULL:
532 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
533 break;
534
535 case MEDIA_TYPE_100M_HALF:
536 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
537 break;
538
539 case MEDIA_TYPE_10M_FULL:
540 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
541 break;
542
543 default:
544 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
545 break;
546 }
547
548 /* flow control fixed to enable all */
549 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
550
551 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
552 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
553
554 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
555 if (ret_val)
556 return ret_val;
557
558 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
559 if (ret_val)
560 return ret_val;
561
562 return ATL1_SUCCESS;
563}
564
565/*
566 * Configures link settings.
567 * hw - Struct containing variables accessed by shared code
568 * Assumes the hardware has previously been reset and the
569 * transmitter and receiver are not enabled.
570 */
571static s32 atl1_setup_link(struct atl1_hw *hw)
572{
573 struct pci_dev *pdev = hw->back->pdev;
574 s32 ret_val;
575
576 /*
577 * Options:
578 * PHY will advertise value(s) parsed from
579 * autoneg_advertised and fc
580 * no matter what autoneg is , We will not wait link result.
581 */
582 ret_val = atl1_phy_setup_autoneg_adv(hw);
583 if (ret_val) {
584 dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
585 return ret_val;
586 }
587 /* SW.Reset , En-Auto-Neg if needed */
588 ret_val = atl1_phy_reset(hw);
589 if (ret_val) {
590 dev_dbg(&pdev->dev, "error resetting phy\n");
591 return ret_val;
592 }
593 hw->phy_configured = true;
594 return ret_val;
595}
596
597static struct atl1_spi_flash_dev flash_table[] = {
598/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
599 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
600 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
601 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
602};
603
604static void atl1_init_flash_opcode(struct atl1_hw *hw)
605{
606 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
607 hw->flash_vendor = 0; /* ATMEL */
608
609 /* Init OP table */
610 iowrite8(flash_table[hw->flash_vendor].cmd_program,
611 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
612 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
615 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
616 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
617 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
618 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
619 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
620 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
623 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
624 iowrite8(flash_table[hw->flash_vendor].cmd_read,
625 hw->hw_addr + REG_SPI_FLASH_OP_READ);
626}
627
628/*
629 * Performs basic configuration of the adapter.
630 * hw - Struct containing variables accessed by shared code
631 * Assumes that the controller has previously been reset and is in a
632 * post-reset uninitialized state. Initializes multicast table,
633 * and Calls routines to setup link
634 * Leaves the transmit and receive units disabled and uninitialized.
635 */
636s32 atl1_init_hw(struct atl1_hw *hw)
637{
638 u32 ret_val = 0;
639
640 /* Zero out the Multicast HASH table */
641 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
642 /* clear the old settings from the multicast hash table */
643 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
644
645 atl1_init_flash_opcode(hw);
646
647 if (!hw->phy_configured) {
648 /* enable GPHY LinkChange Interrrupt */
649 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
650 if (ret_val)
651 return ret_val;
652 /* make PHY out of power-saving state */
653 ret_val = atl1_phy_leave_power_saving(hw);
654 if (ret_val)
655 return ret_val;
656 /* Call a subroutine to configure the link */
657 ret_val = atl1_setup_link(hw);
658 }
659 return ret_val;
660}
661
662/*
663 * Detects the current speed and duplex settings of the hardware.
664 * hw - Struct containing variables accessed by shared code
665 * speed - Speed of the connection
666 * duplex - Duplex setting of the connection
667 */
668s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
669{
670 struct pci_dev *pdev = hw->back->pdev;
671 s32 ret_val;
672 u16 phy_data;
673
674 /* ; --- Read PHY Specific Status Register (17) */
675 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
676 if (ret_val)
677 return ret_val;
678
679 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
680 return ATL1_ERR_PHY_RES;
681
682 switch (phy_data & MII_AT001_PSSR_SPEED) {
683 case MII_AT001_PSSR_1000MBS:
684 *speed = SPEED_1000;
685 break;
686 case MII_AT001_PSSR_100MBS:
687 *speed = SPEED_100;
688 break;
689 case MII_AT001_PSSR_10MBS:
690 *speed = SPEED_10;
691 break;
692 default:
693 dev_dbg(&pdev->dev, "error getting speed\n");
694 return ATL1_ERR_PHY_SPEED;
695 break;
696 }
697 if (phy_data & MII_AT001_PSSR_DPLX)
698 *duplex = FULL_DUPLEX;
699 else
700 *duplex = HALF_DUPLEX;
701
702 return ATL1_SUCCESS;
703}
704
705void atl1_set_mac_addr(struct atl1_hw *hw)
706{
707 u32 value;
708 /*
709 * 00-0B-6A-F6-00-DC
710 * 0: 6AF600DC 1: 000B
711 * low dword
712 */
713 value = (((u32) hw->mac_addr[2]) << 24) |
714 (((u32) hw->mac_addr[3]) << 16) |
715 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
716 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
717 /* high dword */
718 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
719 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
720}
diff --git a/drivers/net/atl1/atl1_hw.h b/drivers/net/atl1/atl1_hw.h
deleted file mode 100644
index 939aa0f53f6e..000000000000
--- a/drivers/net/atl1/atl1_hw.h
+++ /dev/null
@@ -1,946 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * There are a lot of defines in here that are unused and/or have cryptic
24 * names. Please leave them alone, as they're the closest thing we have
25 * to a spec from Attansic at present. *ahem* -- CHS
26 */
27
28#ifndef _ATL1_HW_H_
29#define _ATL1_HW_H_
30
31#include <linux/types.h>
32#include <linux/mii.h>
33
34struct atl1_adapter;
35struct atl1_hw;
36
37/* function prototypes needed by multiple files */
38s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
39s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
40s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
41s32 atl1_read_mac_addr(struct atl1_hw *hw);
42s32 atl1_init_hw(struct atl1_hw *hw);
43s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
44s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
45u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
46void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
47s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
48void atl1_set_mac_addr(struct atl1_hw *hw);
49s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
50s32 atl1_reset_hw(struct atl1_hw *hw);
51void atl1_check_options(struct atl1_adapter *adapter);
52
53/* register definitions */
54#define REG_PCIE_CAP_LIST 0x58
55
56#define REG_VPD_CAP 0x6C
57#define VPD_CAP_ID_MASK 0xff
58#define VPD_CAP_ID_SHIFT 0
59#define VPD_CAP_NEXT_PTR_MASK 0xFF
60#define VPD_CAP_NEXT_PTR_SHIFT 8
61#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
62#define VPD_CAP_VPD_ADDR_SHIFT 16
63#define VPD_CAP_VPD_FLAG 0x80000000
64
65#define REG_VPD_DATA 0x70
66
67#define REG_SPI_FLASH_CTRL 0x200
68#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
69#define SPI_FLASH_CTRL_STS_WEN 0x2
70#define SPI_FLASH_CTRL_STS_WPEN 0x80
71#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
72#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
73#define SPI_FLASH_CTRL_INS_MASK 0x7
74#define SPI_FLASH_CTRL_INS_SHIFT 8
75#define SPI_FLASH_CTRL_START 0x800
76#define SPI_FLASH_CTRL_EN_VPD 0x2000
77#define SPI_FLASH_CTRL_LDSTART 0x8000
78#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
79#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
80#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
81#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
82#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
83#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
84#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
85#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
86#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
87#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
88#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
89#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
90#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
91
92#define REG_SPI_ADDR 0x204
93
94#define REG_SPI_DATA 0x208
95
96#define REG_SPI_FLASH_CONFIG 0x20C
97#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
98#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
99#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
100#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
101#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
102
103#define REG_SPI_FLASH_OP_PROGRAM 0x210
104#define REG_SPI_FLASH_OP_SC_ERASE 0x211
105#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
106#define REG_SPI_FLASH_OP_RDID 0x213
107#define REG_SPI_FLASH_OP_WREN 0x214
108#define REG_SPI_FLASH_OP_RDSR 0x215
109#define REG_SPI_FLASH_OP_WRSR 0x216
110#define REG_SPI_FLASH_OP_READ 0x217
111
112#define REG_TWSI_CTRL 0x218
113#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
114#define TWSI_CTRL_LD_OFFSET_SHIFT 0
115#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
116#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
117#define TWSI_CTRL_SW_LDSTART 0x800
118#define TWSI_CTRL_HW_LDSTART 0x1000
119#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
120#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
121#define TWSI_CTRL_LD_EXIST 0x400000
122#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
123#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
124#define TWSI_CTRL_FREQ_SEL_100K 0
125#define TWSI_CTRL_FREQ_SEL_200K 1
126#define TWSI_CTRL_FREQ_SEL_300K 2
127#define TWSI_CTRL_FREQ_SEL_400K 3
128#define TWSI_CTRL_SMB_SLV_ADDR
129#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
130#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
131
132#define REG_PCIE_DEV_MISC_CTRL 0x21C
133#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
134#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
135#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
136#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
137#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
138
139/* Selene Master Control Register */
140#define REG_MASTER_CTRL 0x1400
141#define MASTER_CTRL_SOFT_RST 0x1
142#define MASTER_CTRL_MTIMER_EN 0x2
143#define MASTER_CTRL_ITIMER_EN 0x4
144#define MASTER_CTRL_MANUAL_INT 0x8
145#define MASTER_CTRL_REV_NUM_SHIFT 16
146#define MASTER_CTRL_REV_NUM_MASK 0xff
147#define MASTER_CTRL_DEV_ID_SHIFT 24
148#define MASTER_CTRL_DEV_ID_MASK 0xff
149
150/* Timer Initial Value Register */
151#define REG_MANUAL_TIMER_INIT 0x1404
152
153/* IRQ ModeratorTimer Initial Value Register */
154#define REG_IRQ_MODU_TIMER_INIT 0x1408
155
156#define REG_GPHY_ENABLE 0x140C
157
158/* IRQ Anti-Lost Timer Initial Value Register */
159#define REG_CMBDISDMA_TIMER 0x140E
160
161/* Block IDLE Status Register */
162#define REG_IDLE_STATUS 0x1410
163#define IDLE_STATUS_RXMAC 1
164#define IDLE_STATUS_TXMAC 2
165#define IDLE_STATUS_RXQ 4
166#define IDLE_STATUS_TXQ 8
167#define IDLE_STATUS_DMAR 0x10
168#define IDLE_STATUS_DMAW 0x20
169#define IDLE_STATUS_SMB 0x40
170#define IDLE_STATUS_CMB 0x80
171
172/* MDIO Control Register */
173#define REG_MDIO_CTRL 0x1414
174#define MDIO_DATA_MASK 0xffff
175#define MDIO_DATA_SHIFT 0
176#define MDIO_REG_ADDR_MASK 0x1f
177#define MDIO_REG_ADDR_SHIFT 16
178#define MDIO_RW 0x200000
179#define MDIO_SUP_PREAMBLE 0x400000
180#define MDIO_START 0x800000
181#define MDIO_CLK_SEL_SHIFT 24
182#define MDIO_CLK_25_4 0
183#define MDIO_CLK_25_6 2
184#define MDIO_CLK_25_8 3
185#define MDIO_CLK_25_10 4
186#define MDIO_CLK_25_14 5
187#define MDIO_CLK_25_20 6
188#define MDIO_CLK_25_28 7
189#define MDIO_BUSY 0x8000000
190#define MDIO_WAIT_TIMES 30
191
192/* MII PHY Status Register */
193#define REG_PHY_STATUS 0x1418
194
195/* BIST Control and Status Register0 (for the Packet Memory) */
196#define REG_BIST0_CTRL 0x141c
197#define BIST0_NOW 0x1
198#define BIST0_SRAM_FAIL 0x2
199#define BIST0_FUSE_FLAG 0x4
200#define REG_BIST1_CTRL 0x1420
201#define BIST1_NOW 0x1
202#define BIST1_SRAM_FAIL 0x2
203#define BIST1_FUSE_FLAG 0x4
204
205/* MAC Control Register */
206#define REG_MAC_CTRL 0x1480
207#define MAC_CTRL_TX_EN 1
208#define MAC_CTRL_RX_EN 2
209#define MAC_CTRL_TX_FLOW 4
210#define MAC_CTRL_RX_FLOW 8
211#define MAC_CTRL_LOOPBACK 0x10
212#define MAC_CTRL_DUPLX 0x20
213#define MAC_CTRL_ADD_CRC 0x40
214#define MAC_CTRL_PAD 0x80
215#define MAC_CTRL_LENCHK 0x100
216#define MAC_CTRL_HUGE_EN 0x200
217#define MAC_CTRL_PRMLEN_SHIFT 10
218#define MAC_CTRL_PRMLEN_MASK 0xf
219#define MAC_CTRL_RMV_VLAN 0x4000
220#define MAC_CTRL_PROMIS_EN 0x8000
221#define MAC_CTRL_TX_PAUSE 0x10000
222#define MAC_CTRL_SCNT 0x20000
223#define MAC_CTRL_SRST_TX 0x40000
224#define MAC_CTRL_TX_SIMURST 0x80000
225#define MAC_CTRL_SPEED_SHIFT 20
226#define MAC_CTRL_SPEED_MASK 0x300000
227#define MAC_CTRL_SPEED_1000 2
228#define MAC_CTRL_SPEED_10_100 1
229#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
230#define MAC_CTRL_TX_HUGE 0x800000
231#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
232#define MAC_CTRL_MC_ALL_EN 0x2000000
233#define MAC_CTRL_BC_EN 0x4000000
234#define MAC_CTRL_DBG 0x8000000
235
236/* MAC IPG/IFG Control Register */
237#define REG_MAC_IPG_IFG 0x1484
238#define MAC_IPG_IFG_IPGT_SHIFT 0
239#define MAC_IPG_IFG_IPGT_MASK 0x7f
240#define MAC_IPG_IFG_MIFG_SHIFT 8
241#define MAC_IPG_IFG_MIFG_MASK 0xff
242#define MAC_IPG_IFG_IPGR1_SHIFT 16
243#define MAC_IPG_IFG_IPGR1_MASK 0x7f
244#define MAC_IPG_IFG_IPGR2_SHIFT 24
245#define MAC_IPG_IFG_IPGR2_MASK 0x7f
246
247/* MAC STATION ADDRESS */
248#define REG_MAC_STA_ADDR 0x1488
249
250/* Hash table for multicast address */
251#define REG_RX_HASH_TABLE 0x1490
252
253/* MAC Half-Duplex Control Register */
254#define REG_MAC_HALF_DUPLX_CTRL 0x1498
255#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
256#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
257#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
258#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
259#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
260#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
261#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
262#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
263#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
264#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
265#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
266#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
267
268/* Maximum Frame Length Control Register */
269#define REG_MTU 0x149c
270
271/* Wake-On-Lan control register */
272#define REG_WOL_CTRL 0x14a0
273#define WOL_PATTERN_EN 0x00000001
274#define WOL_PATTERN_PME_EN 0x00000002
275#define WOL_MAGIC_EN 0x00000004
276#define WOL_MAGIC_PME_EN 0x00000008
277#define WOL_LINK_CHG_EN 0x00000010
278#define WOL_LINK_CHG_PME_EN 0x00000020
279#define WOL_PATTERN_ST 0x00000100
280#define WOL_MAGIC_ST 0x00000200
281#define WOL_LINKCHG_ST 0x00000400
282#define WOL_CLK_SWITCH_EN 0x00008000
283#define WOL_PT0_EN 0x00010000
284#define WOL_PT1_EN 0x00020000
285#define WOL_PT2_EN 0x00040000
286#define WOL_PT3_EN 0x00080000
287#define WOL_PT4_EN 0x00100000
288#define WOL_PT5_EN 0x00200000
289#define WOL_PT6_EN 0x00400000
290
291/* WOL Length ( 2 DWORD ) */
292#define REG_WOL_PATTERN_LEN 0x14a4
293#define WOL_PT_LEN_MASK 0x7f
294#define WOL_PT0_LEN_SHIFT 0
295#define WOL_PT1_LEN_SHIFT 8
296#define WOL_PT2_LEN_SHIFT 16
297#define WOL_PT3_LEN_SHIFT 24
298#define WOL_PT4_LEN_SHIFT 0
299#define WOL_PT5_LEN_SHIFT 8
300#define WOL_PT6_LEN_SHIFT 16
301
302/* Internal SRAM Partition Register */
303#define REG_SRAM_RFD_ADDR 0x1500
304#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
305#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
306#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
307#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
308#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
309#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
310#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
311#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
312#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
313#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
314#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
315#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
316#define SRAM_TCPH_ADDR_MASK 0x0fff
317#define SRAM_TCPH_ADDR_SHIFT 0
318#define SRAM_PATH_ADDR_MASK 0x0fff
319#define SRAM_PATH_ADDR_SHIFT 16
320
321/* Load Ptr Register */
322#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
323
324/* Descriptor Control register */
325#define REG_DESC_BASE_ADDR_HI 0x1540
326#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
327#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
328#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
329#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
330#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
331#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
332#define DESC_RFD_RING_SIZE_MASK 0x7ff
333#define DESC_RFD_RING_SIZE_SHIFT 0
334#define DESC_RRD_RING_SIZE_MASK 0x7ff
335#define DESC_RRD_RING_SIZE_SHIFT 16
336#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
337#define DESC_TPD_RING_SIZE_MASK 0x3ff
338#define DESC_TPD_RING_SIZE_SHIFT 0
339
340/* TXQ Control Register */
341#define REG_TXQ_CTRL 0x1580
342#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
343#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
344#define TXQ_CTRL_EN 0x20
345#define TXQ_CTRL_ENH_MODE 0x40
346#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
347#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
348#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
349#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
350
351/* Jumbo packet Threshold for task offload */
352#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
353#define TX_JUMBO_TASK_TH_MASK 0x7ff
354#define TX_JUMBO_TASK_TH_SHIFT 0
355#define TX_TPD_MIN_IPG_MASK 0x1f
356#define TX_TPD_MIN_IPG_SHIFT 16
357
358/* RXQ Control Register */
359#define REG_RXQ_CTRL 0x15a0
360#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
361#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
362#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
363#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
364#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
365#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
366#define RXQ_CTRL_CUT_THRU_EN 0x40000000
367#define RXQ_CTRL_EN 0x80000000
368
369/* Rx jumbo packet threshold and rrd retirement timer */
370#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
371#define RXQ_JMBOSZ_TH_MASK 0x7ff
372#define RXQ_JMBOSZ_TH_SHIFT 0
373#define RXQ_JMBO_LKAH_MASK 0xf
374#define RXQ_JMBO_LKAH_SHIFT 11
375#define RXQ_RRD_TIMER_MASK 0xffff
376#define RXQ_RRD_TIMER_SHIFT 16
377
378/* RFD flow control register */
379#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
380#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
381#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
382#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
383#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
384
385/* RRD flow control register */
386#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
387#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
388#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
389#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
390#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
391
392/* DMA Engine Control Register */
393#define REG_DMA_CTRL 0x15c0
394#define DMA_CTRL_DMAR_IN_ORDER 0x1
395#define DMA_CTRL_DMAR_ENH_ORDER 0x2
396#define DMA_CTRL_DMAR_OUT_ORDER 0x4
397#define DMA_CTRL_RCB_VALUE 0x8
398#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
399#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
400#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
401#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
402#define DMA_CTRL_DMAR_EN 0x400
403#define DMA_CTRL_DMAW_EN 0x800
404
405/* CMB/SMB Control Register */
406#define REG_CSMB_CTRL 0x15d0
407#define CSMB_CTRL_CMB_NOW 1
408#define CSMB_CTRL_SMB_NOW 2
409#define CSMB_CTRL_CMB_EN 4
410#define CSMB_CTRL_SMB_EN 8
411
412/* CMB DMA Write Threshold Register */
413#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
414#define CMB_RRD_TH_SHIFT 0
415#define CMB_RRD_TH_MASK 0x7ff
416#define CMB_TPD_TH_SHIFT 16
417#define CMB_TPD_TH_MASK 0x7ff
418
419/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
420#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
421#define CMB_RX_TM_SHIFT 0
422#define CMB_RX_TM_MASK 0xffff
423#define CMB_TX_TM_SHIFT 16
424#define CMB_TX_TM_MASK 0xffff
425
426/* Number of packet received since last CMB write */
427#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
428
429/* Number of packet transmitted since last CMB write */
430#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
431
432/* SMB auto DMA timer register */
433#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
434
435/* Mailbox Register */
436#define REG_MAILBOX 0x15f0
437#define MB_RFD_PROD_INDX_SHIFT 0
438#define MB_RFD_PROD_INDX_MASK 0x7ff
439#define MB_RRD_CONS_INDX_SHIFT 11
440#define MB_RRD_CONS_INDX_MASK 0x7ff
441#define MB_TPD_PROD_INDX_SHIFT 22
442#define MB_TPD_PROD_INDX_MASK 0x3ff
443
444/* Interrupt Status Register */
445#define REG_ISR 0x1600
446#define ISR_SMB 1
447#define ISR_TIMER 2
448#define ISR_MANUAL 4
449#define ISR_RXF_OV 8
450#define ISR_RFD_UNRUN 0x10
451#define ISR_RRD_OV 0x20
452#define ISR_TXF_UNRUN 0x40
453#define ISR_LINK 0x80
454#define ISR_HOST_RFD_UNRUN 0x100
455#define ISR_HOST_RRD_OV 0x200
456#define ISR_DMAR_TO_RST 0x400
457#define ISR_DMAW_TO_RST 0x800
458#define ISR_GPHY 0x1000
459#define ISR_RX_PKT 0x10000
460#define ISR_TX_PKT 0x20000
461#define ISR_TX_DMA 0x40000
462#define ISR_RX_DMA 0x80000
463#define ISR_CMB_RX 0x100000
464#define ISR_CMB_TX 0x200000
465#define ISR_MAC_RX 0x400000
466#define ISR_MAC_TX 0x800000
467#define ISR_UR_DETECTED 0x1000000
468#define ISR_FERR_DETECTED 0x2000000
469#define ISR_NFERR_DETECTED 0x4000000
470#define ISR_CERR_DETECTED 0x8000000
471#define ISR_PHY_LINKDOWN 0x10000000
472#define ISR_DIS_SMB 0x20000000
473#define ISR_DIS_DMA 0x40000000
474#define ISR_DIS_INT 0x80000000
475
476/* Interrupt Mask Register */
477#define REG_IMR 0x1604
478
479/* Normal Interrupt mask */
480#define IMR_NORMAL_MASK (\
481 ISR_SMB |\
482 ISR_GPHY |\
483 ISR_PHY_LINKDOWN|\
484 ISR_DMAR_TO_RST |\
485 ISR_DMAW_TO_RST |\
486 ISR_CMB_TX |\
487 ISR_CMB_RX )
488
489/* Debug Interrupt Mask (enable all interrupt) */
490#define IMR_DEBUG_MASK (\
491 ISR_SMB |\
492 ISR_TIMER |\
493 ISR_MANUAL |\
494 ISR_RXF_OV |\
495 ISR_RFD_UNRUN |\
496 ISR_RRD_OV |\
497 ISR_TXF_UNRUN |\
498 ISR_LINK |\
499 ISR_CMB_TX |\
500 ISR_CMB_RX |\
501 ISR_RX_PKT |\
502 ISR_TX_PKT |\
503 ISR_MAC_RX |\
504 ISR_MAC_TX )
505
506/* Interrupt Status Register */
507#define REG_RFD_RRD_IDX 0x1800
508#define REG_TPD_IDX 0x1804
509
510/* MII definition */
511/* PHY Common Register */
512#define MII_AT001_CR 0x09
513#define MII_AT001_SR 0x0A
514#define MII_AT001_ESR 0x0F
515#define MII_AT001_PSCR 0x10
516#define MII_AT001_PSSR 0x11
517
518/* PHY Control Register */
519#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
520#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
521#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
522#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
523#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
524#define MII_CR_POWER_DOWN 0x0800 /* Power down */
525#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
526#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
527#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
528#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
529#define MII_CR_SPEED_MASK 0x2040
530#define MII_CR_SPEED_1000 0x0040
531#define MII_CR_SPEED_100 0x2000
532#define MII_CR_SPEED_10 0x0000
533
534/* PHY Status Register */
535#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
536#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
537#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
538#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
539#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
540#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
541#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
542#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
543#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
544#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
545#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
546#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
547#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
548#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
549#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
550
551/* Link partner ability register. */
552#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
553#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
554#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
555#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
556#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
557#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
558#define MII_LPA_PAUSE 0x0400 /* PAUSE */
559#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
560#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
561#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
562#define MII_LPA_NPAGE 0x8000 /* Next page bit */
563
564/* Autoneg Advertisement Register */
565#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
566#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
567#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
568#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
569#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
570#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
571#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
572#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
573#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
574#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
575#define MII_AR_SPEED_MASK 0x01E0
576#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
577
578/* 1000BASE-T Control Register */
579#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
580#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
581#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
582#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
583#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
584#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
585#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
586#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
587#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
588#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
589#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
590#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
591
592/* 1000BASE-T Status Register */
593#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
594#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
595#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
596#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
597#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
598#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
599#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
600#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
601
602/* Extended Status Register */
603#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
604#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
605#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
606#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
607
608/* AT001 PHY Specific Control Register */
609#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
610#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
611#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
612#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
613#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
614#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
615#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
616#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
617#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
618#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
619#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
620#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
621#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
622#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
623#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
624#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
625#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
626
627/* AT001 PHY Specific Status Register */
628#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
629#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
630#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
631#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
632#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
633#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
634
635/* PCI Command Register Bit Definitions */
636#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
637#define CMD_IO_SPACE 0x0001
638#define CMD_MEMORY_SPACE 0x0002
639#define CMD_BUS_MASTER 0x0004
640
641/* Wake Up Filter Control */
642#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
643#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
644#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
645#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
646#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
647
648/* Error Codes */
649#define ATL1_SUCCESS 0
650#define ATL1_ERR_EEPROM 1
651#define ATL1_ERR_PHY 2
652#define ATL1_ERR_CONFIG 3
653#define ATL1_ERR_PARAM 4
654#define ATL1_ERR_MAC_TYPE 5
655#define ATL1_ERR_PHY_TYPE 6
656#define ATL1_ERR_PHY_SPEED 7
657#define ATL1_ERR_PHY_RES 8
658
659#define SPEED_0 0xffff
660#define SPEED_10 10
661#define SPEED_100 100
662#define SPEED_1000 1000
663#define HALF_DUPLEX 1
664#define FULL_DUPLEX 2
665
666#define MEDIA_TYPE_AUTO_SENSOR 0
667#define MEDIA_TYPE_1000M_FULL 1
668#define MEDIA_TYPE_100M_FULL 2
669#define MEDIA_TYPE_100M_HALF 3
670#define MEDIA_TYPE_10M_FULL 4
671#define MEDIA_TYPE_10M_HALF 5
672
673#define ADVERTISE_10_HALF 0x0001
674#define ADVERTISE_10_FULL 0x0002
675#define ADVERTISE_100_HALF 0x0004
676#define ADVERTISE_100_FULL 0x0008
677#define ADVERTISE_1000_HALF 0x0010
678#define ADVERTISE_1000_FULL 0x0020
679#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
680#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
681#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
682
683#define MAX_JUMBO_FRAME_SIZE 0x2800
684
685#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
686#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
687
688/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
689#define EEPROM_SUM 0xBABA
690
691#define ATL1_EEDUMP_LEN 48
692
693/* Statistics counters collected by the MAC */
694struct stats_msg_block {
695 /* rx */
696 u32 rx_ok; /* The number of good packet received. */
697 u32 rx_bcast; /* The number of good broadcast packet received. */
698 u32 rx_mcast; /* The number of good multicast packet received. */
699 u32 rx_pause; /* The number of Pause packet received. */
700 u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
701 u32 rx_fcs_err; /* The number of packets with bad FCS. */
702 u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
703 u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
704 u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
705 u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
706 u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
707 u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
708 u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
709 u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
710 u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
711 u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
712 u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
713 u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
714 u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
715 u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
716 u32 rx_align_err; /* Alignment Error */
717 u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
718 u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
719 u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
720
721 /* tx */
722 u32 tx_ok; /* The number of good packet transmitted. */
723 u32 tx_bcast; /* The number of good broadcast packet transmitted. */
724 u32 tx_mcast; /* The number of good multicast packet transmitted. */
725 u32 tx_pause; /* The number of Pause packet transmitted. */
726 u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
727 u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
728 u32 tx_defer; /* The number of packets transmitted that is deferred. */
729 u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
730 u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
731 u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
732 u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
733 u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
734 u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
735 u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
736 u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
737 u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
738 u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
739 u32 tx_late_col; /* The number of packets transmitted with late collisions. */
740 u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
741 u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
742 u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
743 u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
744 u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
745 u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
746 u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
747 u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
748 * Software should clear this bit as soon as retrieving the statistics information. */
749};
750
751/* Coalescing Message Block */
752struct coals_msg_block {
753 u32 int_stats; /* interrupt status */
754 u16 rrd_prod_idx; /* TRD Producer Index. */
755 u16 rfd_cons_idx; /* RFD Consumer Index. */
756 u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
757 * Software supposes to clear this bit when CMB information is processed. */
758 u16 tpd_cons_idx; /* TPD Consumer Index. */
759};
760
761/* RRD descriptor */
762struct rx_return_desc {
763 u8 num_buf; /* Number of RFD buffers used by the received packet */
764 u8 resved;
765 u16 buf_indx; /* RFD Index of the first buffer */
766 union {
767 u32 valid;
768 struct {
769 u16 rx_chksum;
770 u16 pkt_size;
771 } xsum_sz;
772 } xsz;
773
774 u16 pkt_flg; /* Packet flags */
775 u16 err_flg; /* Error flags */
776 u16 resved2;
777 u16 vlan_tag; /* VLAN TAG */
778};
779
780#define PACKET_FLAG_ETH_TYPE 0x0080
781#define PACKET_FLAG_VLAN_INS 0x0100
782#define PACKET_FLAG_ERR 0x0200
783#define PACKET_FLAG_IPV4 0x0400
784#define PACKET_FLAG_UDP 0x0800
785#define PACKET_FLAG_TCP 0x1000
786#define PACKET_FLAG_BCAST 0x2000
787#define PACKET_FLAG_MCAST 0x4000
788#define PACKET_FLAG_PAUSE 0x8000
789
790#define ERR_FLAG_CRC 0x0001
791#define ERR_FLAG_CODE 0x0002
792#define ERR_FLAG_DRIBBLE 0x0004
793#define ERR_FLAG_RUNT 0x0008
794#define ERR_FLAG_OV 0x0010
795#define ERR_FLAG_TRUNC 0x0020
796#define ERR_FLAG_IP_CHKSUM 0x0040
797#define ERR_FLAG_L4_CHKSUM 0x0080
798#define ERR_FLAG_LEN 0x0100
799#define ERR_FLAG_DES_ADDR 0x0200
800
801/* RFD descriptor */
802struct rx_free_desc {
803 __le64 buffer_addr; /* Address of the descriptor's data buffer */
804 __le16 buf_len; /* Size of the receive buffer in host memory, in byte */
805 u16 coalese; /* Update consumer index to host after the reception of this frame */
806 /* __attribute__ ((packed)) is required */
807} __attribute__ ((packed));
808
809/* tsopu defines */
810#define TSO_PARAM_BUFLEN_MASK 0x3FFF
811#define TSO_PARAM_BUFLEN_SHIFT 0
812#define TSO_PARAM_DMAINT_MASK 0x0001
813#define TSO_PARAM_DMAINT_SHIFT 14
814#define TSO_PARAM_PKTNT_MASK 0x0001
815#define TSO_PARAM_PKTINT_SHIFT 15
816#define TSO_PARAM_VLANTAG_MASK 0xFFFF
817#define TSO_PARAM_VLAN_SHIFT 16
818
819/* tsopl defines */
820#define TSO_PARAM_EOP_MASK 0x0001
821#define TSO_PARAM_EOP_SHIFT 0
822#define TSO_PARAM_COALESCE_MASK 0x0001
823#define TSO_PARAM_COALESCE_SHIFT 1
824#define TSO_PARAM_INSVLAG_MASK 0x0001
825#define TSO_PARAM_INSVLAG_SHIFT 2
826#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
827#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
828#define TSO_PARAM_SEGMENT_MASK 0x0001
829#define TSO_PARAM_SEGMENT_SHIFT 4
830#define TSO_PARAM_IPCKSUM_MASK 0x0001
831#define TSO_PARAM_IPCKSUM_SHIFT 5
832#define TSO_PARAM_TCPCKSUM_MASK 0x0001
833#define TSO_PARAM_TCPCKSUM_SHIFT 6
834#define TSO_PARAM_UDPCKSUM_MASK 0x0001
835#define TSO_PARAM_UDPCKSUM_SHIFT 7
836#define TSO_PARAM_VLANTAGGED_MASK 0x0001
837#define TSO_PARAM_VLANTAGGED_SHIFT 8
838#define TSO_PARAM_ETHTYPE_MASK 0x0001
839#define TSO_PARAM_ETHTYPE_SHIFT 9
840#define TSO_PARAM_IPHL_MASK 0x000F
841#define TSO_PARAM_IPHL_SHIFT 10
842#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
843#define TSO_PARAM_TCPHDRLEN_SHIFT 14
844#define TSO_PARAM_HDRFLAG_MASK 0x0001
845#define TSO_PARAM_HDRFLAG_SHIFT 18
846#define TSO_PARAM_MSS_MASK 0x1FFF
847#define TSO_PARAM_MSS_SHIFT 19
848
849/* csumpu defines */
850#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
851#define CSUM_PARAM_BUFLEN_SHIFT 0
852#define CSUM_PARAM_DMAINT_MASK 0x0001
853#define CSUM_PARAM_DMAINT_SHIFT 14
854#define CSUM_PARAM_PKTINT_MASK 0x0001
855#define CSUM_PARAM_PKTINT_SHIFT 15
856#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
857#define CSUM_PARAM_VALAN_SHIFT 16
858
859/* csumpl defines*/
860#define CSUM_PARAM_EOP_MASK 0x0001
861#define CSUM_PARAM_EOP_SHIFT 0
862#define CSUM_PARAM_COALESCE_MASK 0x0001
863#define CSUM_PARAM_COALESCE_SHIFT 1
864#define CSUM_PARAM_INSVLAG_MASK 0x0001
865#define CSUM_PARAM_INSVLAG_SHIFT 2
866#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
867#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
868#define CSUM_PARAM_SEGMENT_MASK 0x0001
869#define CSUM_PARAM_SEGMENT_SHIFT 4
870#define CSUM_PARAM_IPCKSUM_MASK 0x0001
871#define CSUM_PARAM_IPCKSUM_SHIFT 5
872#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
873#define CSUM_PARAM_TCPCKSUM_SHIFT 6
874#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
875#define CSUM_PARAM_UDPCKSUM_SHIFT 7
876#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
877#define CSUM_PARAM_VLANTAGGED_SHIFT 8
878#define CSUM_PARAM_ETHTYPE_MASK 0x0001
879#define CSUM_PARAM_ETHTYPE_SHIFT 9
880#define CSUM_PARAM_IPHL_MASK 0x000F
881#define CSUM_PARAM_IPHL_SHIFT 10
882#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
883#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
884#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
885#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
886
887/* TPD descriptor */
888struct tso_param {
889 /* The order of these declarations is important -- don't change it */
890 u32 tsopu; /* tso_param upper word */
891 u32 tsopl; /* tso_param lower word */
892};
893
894struct csum_param {
895 /* The order of these declarations is important -- don't change it */
896 u32 csumpu; /* csum_param upper word */
897 u32 csumpl; /* csum_param lower word */
898};
899
900union tpd_descr {
901 u64 data;
902 struct csum_param csum;
903 struct tso_param tso;
904};
905
906struct tx_packet_desc {
907 __le64 buffer_addr;
908 union tpd_descr desc;
909};
910
911/* DMA Order Settings */
912enum atl1_dma_order {
913 atl1_dma_ord_in = 1,
914 atl1_dma_ord_enh = 2,
915 atl1_dma_ord_out = 4
916};
917
918enum atl1_dma_rcb {
919 atl1_rcb_64 = 0,
920 atl1_rcb_128 = 1
921};
922
923enum atl1_dma_req_block {
924 atl1_dma_req_128 = 0,
925 atl1_dma_req_256 = 1,
926 atl1_dma_req_512 = 2,
927 atl1_dma_req_1024 = 3,
928 atl1_dma_req_2048 = 4,
929 atl1_dma_req_4096 = 5
930};
931
932struct atl1_spi_flash_dev {
933 const char *manu_name; /* manufacturer id */
934 /* op-code */
935 u8 cmd_wrsr;
936 u8 cmd_read;
937 u8 cmd_program;
938 u8 cmd_wren;
939 u8 cmd_wrdi;
940 u8 cmd_rdsr;
941 u8 cmd_rdid;
942 u8 cmd_sector_erase;
943 u8 cmd_chip_erase;
944};
945
946#endif /* _ATL1_HW_H_ */
diff --git a/drivers/net/atl1/atl1_main.c b/drivers/net/atl1/atl1_main.c
deleted file mode 100644
index 9200ee59d854..000000000000
--- a/drivers/net/atl1/atl1_main.c
+++ /dev/null
@@ -1,2453 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong_huang@attansic.com>
28 * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
29 * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
30 *
31 * Chris Snook <csnook@redhat.com>
32 * Jay Cliburn <jcliburn@gmail.com>
33 *
34 * This version is adapted from the Attansic reference driver for
35 * inclusion in the Linux kernel. It is currently under heavy development.
36 * A very incomplete list of things that need to be dealt with:
37 *
38 * TODO:
39 * Fix TSO; tx performance is horrible with TSO enabled.
40 * Wake on LAN.
41 * Add more ethtool functions.
42 * Fix abstruse irq enable/disable condition described here:
43 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
44 *
45 * NEEDS TESTING:
46 * VLAN
47 * multicast
48 * promiscuous mode
49 * interrupt coalescing
50 * SMP torture testing
51 */
52
53#include <linux/types.h>
54#include <linux/netdevice.h>
55#include <linux/pci.h>
56#include <linux/spinlock.h>
57#include <linux/slab.h>
58#include <linux/string.h>
59#include <linux/skbuff.h>
60#include <linux/etherdevice.h>
61#include <linux/if_vlan.h>
62#include <linux/if_ether.h>
63#include <linux/irqreturn.h>
64#include <linux/workqueue.h>
65#include <linux/timer.h>
66#include <linux/jiffies.h>
67#include <linux/hardirq.h>
68#include <linux/interrupt.h>
69#include <linux/irqflags.h>
70#include <linux/dma-mapping.h>
71#include <linux/net.h>
72#include <linux/pm.h>
73#include <linux/in.h>
74#include <linux/ip.h>
75#include <linux/tcp.h>
76#include <linux/compiler.h>
77#include <linux/delay.h>
78#include <linux/mii.h>
79#include <net/checksum.h>
80
81#include <asm/atomic.h>
82#include <asm/byteorder.h>
83
84#include "atl1.h"
85
86#define DRIVER_VERSION "2.0.7"
87
88char atl1_driver_name[] = "atl1";
89static const char atl1_driver_string[] = "Attansic L1 Ethernet Network Driver";
90static const char atl1_copyright[] = "Copyright(c) 2005-2006 Attansic Corporation.";
91char atl1_driver_version[] = DRIVER_VERSION;
92
93MODULE_AUTHOR
94 ("Attansic Corporation <xiong_huang@attansic.com>, Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
95MODULE_DESCRIPTION("Attansic 1000M Ethernet Network Driver");
96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRIVER_VERSION);
98
99/*
100 * atl1_pci_tbl - PCI Device ID Table
101 */
102static const struct pci_device_id atl1_pci_tbl[] = {
103 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
104 /* required last entry */
105 {0,}
106};
107
108MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
109
110/*
111 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
112 * @adapter: board private structure to initialize
113 *
114 * atl1_sw_init initializes the Adapter private data structure.
115 * Fields are initialized based on PCI device information and
116 * OS network device settings (MTU size).
117 */
118static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
119{
120 struct atl1_hw *hw = &adapter->hw;
121 struct net_device *netdev = adapter->netdev;
122
123 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
124 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
125
126 adapter->wol = 0;
127 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
128 adapter->ict = 50000; /* 100ms */
129 adapter->link_speed = SPEED_0; /* hardware init */
130 adapter->link_duplex = FULL_DUPLEX;
131
132 hw->phy_configured = false;
133 hw->preamble_len = 7;
134 hw->ipgt = 0x60;
135 hw->min_ifg = 0x50;
136 hw->ipgr1 = 0x40;
137 hw->ipgr2 = 0x60;
138 hw->max_retry = 0xf;
139 hw->lcol = 0x37;
140 hw->jam_ipg = 7;
141 hw->rfd_burst = 8;
142 hw->rrd_burst = 8;
143 hw->rfd_fetch_gap = 1;
144 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
145 hw->rx_jumbo_lkah = 1;
146 hw->rrd_ret_timer = 16;
147 hw->tpd_burst = 4;
148 hw->tpd_fetch_th = 16;
149 hw->txf_burst = 0x100;
150 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
151 hw->tpd_fetch_gap = 1;
152 hw->rcb_value = atl1_rcb_64;
153 hw->dma_ord = atl1_dma_ord_enh;
154 hw->dmar_block = atl1_dma_req_256;
155 hw->dmaw_block = atl1_dma_req_256;
156 hw->cmb_rrd = 4;
157 hw->cmb_tpd = 4;
158 hw->cmb_rx_timer = 1; /* about 2us */
159 hw->cmb_tx_timer = 1; /* about 2us */
160 hw->smb_timer = 100000; /* about 200ms */
161
162 spin_lock_init(&adapter->lock);
163 spin_lock_init(&adapter->mb_lock);
164
165 return 0;
166}
167
168static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
169{
170 struct atl1_adapter *adapter = netdev_priv(netdev);
171 u16 result;
172
173 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
174
175 return result;
176}
177
178static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
179 int val)
180{
181 struct atl1_adapter *adapter = netdev_priv(netdev);
182
183 atl1_write_phy_reg(&adapter->hw, reg_num, val);
184}
185
186/*
187 * atl1_mii_ioctl -
188 * @netdev:
189 * @ifreq:
190 * @cmd:
191 */
192static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
193{
194 struct atl1_adapter *adapter = netdev_priv(netdev);
195 unsigned long flags;
196 int retval;
197
198 if (!netif_running(netdev))
199 return -EINVAL;
200
201 spin_lock_irqsave(&adapter->lock, flags);
202 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
203 spin_unlock_irqrestore(&adapter->lock, flags);
204
205 return retval;
206}
207
208/*
209 * atl1_ioctl -
210 * @netdev:
211 * @ifreq:
212 * @cmd:
213 */
214static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
215{
216 switch (cmd) {
217 case SIOCGMIIPHY:
218 case SIOCGMIIREG:
219 case SIOCSMIIREG:
220 return atl1_mii_ioctl(netdev, ifr, cmd);
221 default:
222 return -EOPNOTSUPP;
223 }
224}
225
226/*
227 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
228 * @adapter: board private structure
229 *
230 * Return 0 on success, negative on failure
231 */
232s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
233{
234 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
235 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
236 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
237 struct atl1_ring_header *ring_header = &adapter->ring_header;
238 struct pci_dev *pdev = adapter->pdev;
239 int size;
240 u8 offset = 0;
241
242 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
243 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
244 if (unlikely(!tpd_ring->buffer_info)) {
245 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", size);
246 goto err_nomem;
247 }
248 rfd_ring->buffer_info =
249 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
250
251 /* real ring DMA buffer
252 * each ring/block may need up to 8 bytes for alignment, hence the
253 * additional 40 bytes tacked onto the end.
254 */
255 ring_header->size = size =
256 sizeof(struct tx_packet_desc) * tpd_ring->count
257 + sizeof(struct rx_free_desc) * rfd_ring->count
258 + sizeof(struct rx_return_desc) * rrd_ring->count
259 + sizeof(struct coals_msg_block)
260 + sizeof(struct stats_msg_block)
261 + 40;
262
263 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
264 &ring_header->dma);
265 if (unlikely(!ring_header->desc)) {
266 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
267 goto err_nomem;
268 }
269
270 memset(ring_header->desc, 0, ring_header->size);
271
272 /* init TPD ring */
273 tpd_ring->dma = ring_header->dma;
274 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
275 tpd_ring->dma += offset;
276 tpd_ring->desc = (u8 *) ring_header->desc + offset;
277 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
278
279 /* init RFD ring */
280 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
281 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
282 rfd_ring->dma += offset;
283 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
284 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
285
286
287 /* init RRD ring */
288 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
289 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
290 rrd_ring->dma += offset;
291 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
292 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
293
294
295 /* init CMB */
296 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
297 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
298 adapter->cmb.dma += offset;
299 adapter->cmb.cmb = (struct coals_msg_block *)
300 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
301
302 /* init SMB */
303 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
304 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
305 adapter->smb.dma += offset;
306 adapter->smb.smb = (struct stats_msg_block *)
307 ((u8 *) adapter->cmb.cmb +
308 (sizeof(struct coals_msg_block) + offset));
309
310 return ATL1_SUCCESS;
311
312err_nomem:
313 kfree(tpd_ring->buffer_info);
314 return -ENOMEM;
315}
316
317static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
318{
319 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
320 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
321 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
322
323 atomic_set(&tpd_ring->next_to_use, 0);
324 atomic_set(&tpd_ring->next_to_clean, 0);
325
326 rfd_ring->next_to_clean = 0;
327 atomic_set(&rfd_ring->next_to_use, 0);
328
329 rrd_ring->next_to_use = 0;
330 atomic_set(&rrd_ring->next_to_clean, 0);
331}
332
333/*
334 * atl1_clean_rx_ring - Free RFD Buffers
335 * @adapter: board private structure
336 */
337static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
338{
339 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
340 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
341 struct atl1_buffer *buffer_info;
342 struct pci_dev *pdev = adapter->pdev;
343 unsigned long size;
344 unsigned int i;
345
346 /* Free all the Rx ring sk_buffs */
347 for (i = 0; i < rfd_ring->count; i++) {
348 buffer_info = &rfd_ring->buffer_info[i];
349 if (buffer_info->dma) {
350 pci_unmap_page(pdev, buffer_info->dma,
351 buffer_info->length, PCI_DMA_FROMDEVICE);
352 buffer_info->dma = 0;
353 }
354 if (buffer_info->skb) {
355 dev_kfree_skb(buffer_info->skb);
356 buffer_info->skb = NULL;
357 }
358 }
359
360 size = sizeof(struct atl1_buffer) * rfd_ring->count;
361 memset(rfd_ring->buffer_info, 0, size);
362
363 /* Zero out the descriptor ring */
364 memset(rfd_ring->desc, 0, rfd_ring->size);
365
366 rfd_ring->next_to_clean = 0;
367 atomic_set(&rfd_ring->next_to_use, 0);
368
369 rrd_ring->next_to_use = 0;
370 atomic_set(&rrd_ring->next_to_clean, 0);
371}
372
373/*
374 * atl1_clean_tx_ring - Free Tx Buffers
375 * @adapter: board private structure
376 */
377static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
378{
379 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
380 struct atl1_buffer *buffer_info;
381 struct pci_dev *pdev = adapter->pdev;
382 unsigned long size;
383 unsigned int i;
384
385 /* Free all the Tx ring sk_buffs */
386 for (i = 0; i < tpd_ring->count; i++) {
387 buffer_info = &tpd_ring->buffer_info[i];
388 if (buffer_info->dma) {
389 pci_unmap_page(pdev, buffer_info->dma,
390 buffer_info->length, PCI_DMA_TODEVICE);
391 buffer_info->dma = 0;
392 }
393 }
394
395 for (i = 0; i < tpd_ring->count; i++) {
396 buffer_info = &tpd_ring->buffer_info[i];
397 if (buffer_info->skb) {
398 dev_kfree_skb_any(buffer_info->skb);
399 buffer_info->skb = NULL;
400 }
401 }
402
403 size = sizeof(struct atl1_buffer) * tpd_ring->count;
404 memset(tpd_ring->buffer_info, 0, size);
405
406 /* Zero out the descriptor ring */
407 memset(tpd_ring->desc, 0, tpd_ring->size);
408
409 atomic_set(&tpd_ring->next_to_use, 0);
410 atomic_set(&tpd_ring->next_to_clean, 0);
411}
412
413/*
414 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
415 * @adapter: board private structure
416 *
417 * Free all transmit software resources
418 */
419void atl1_free_ring_resources(struct atl1_adapter *adapter)
420{
421 struct pci_dev *pdev = adapter->pdev;
422 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
423 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
424 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
425 struct atl1_ring_header *ring_header = &adapter->ring_header;
426
427 atl1_clean_tx_ring(adapter);
428 atl1_clean_rx_ring(adapter);
429
430 kfree(tpd_ring->buffer_info);
431 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
432 ring_header->dma);
433
434 tpd_ring->buffer_info = NULL;
435 tpd_ring->desc = NULL;
436 tpd_ring->dma = 0;
437
438 rfd_ring->buffer_info = NULL;
439 rfd_ring->desc = NULL;
440 rfd_ring->dma = 0;
441
442 rrd_ring->desc = NULL;
443 rrd_ring->dma = 0;
444}
445
446static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
447{
448 u32 value;
449 struct atl1_hw *hw = &adapter->hw;
450 struct net_device *netdev = adapter->netdev;
451 /* Config MAC CTRL Register */
452 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
453 /* duplex */
454 if (FULL_DUPLEX == adapter->link_duplex)
455 value |= MAC_CTRL_DUPLX;
456 /* speed */
457 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
458 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
459 MAC_CTRL_SPEED_SHIFT);
460 /* flow control */
461 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
462 /* PAD & CRC */
463 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
464 /* preamble length */
465 value |= (((u32) adapter->hw.preamble_len
466 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
467 /* vlan */
468 if (adapter->vlgrp)
469 value |= MAC_CTRL_RMV_VLAN;
470 /* rx checksum
471 if (adapter->rx_csum)
472 value |= MAC_CTRL_RX_CHKSUM_EN;
473 */
474 /* filter mode */
475 value |= MAC_CTRL_BC_EN;
476 if (netdev->flags & IFF_PROMISC)
477 value |= MAC_CTRL_PROMIS_EN;
478 else if (netdev->flags & IFF_ALLMULTI)
479 value |= MAC_CTRL_MC_ALL_EN;
480 /* value |= MAC_CTRL_LOOPBACK; */
481 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
482}
483
484/*
485 * atl1_set_mac - Change the Ethernet Address of the NIC
486 * @netdev: network interface device structure
487 * @p: pointer to an address structure
488 *
489 * Returns 0 on success, negative on failure
490 */
491static int atl1_set_mac(struct net_device *netdev, void *p)
492{
493 struct atl1_adapter *adapter = netdev_priv(netdev);
494 struct sockaddr *addr = p;
495
496 if (netif_running(netdev))
497 return -EBUSY;
498
499 if (!is_valid_ether_addr(addr->sa_data))
500 return -EADDRNOTAVAIL;
501
502 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
503 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
504
505 atl1_set_mac_addr(&adapter->hw);
506 return 0;
507}
508
509static u32 atl1_check_link(struct atl1_adapter *adapter)
510{
511 struct atl1_hw *hw = &adapter->hw;
512 struct net_device *netdev = adapter->netdev;
513 u32 ret_val;
514 u16 speed, duplex, phy_data;
515 int reconfig = 0;
516
517 /* MII_BMSR must read twice */
518 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
519 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
520 if (!(phy_data & BMSR_LSTATUS)) { /* link down */
521 if (netif_carrier_ok(netdev)) { /* old link state: Up */
522 dev_info(&adapter->pdev->dev, "link is down\n");
523 adapter->link_speed = SPEED_0;
524 netif_carrier_off(netdev);
525 netif_stop_queue(netdev);
526 }
527 return ATL1_SUCCESS;
528 }
529
530 /* Link Up */
531 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
532 if (ret_val)
533 return ret_val;
534
535 switch (hw->media_type) {
536 case MEDIA_TYPE_1000M_FULL:
537 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
538 reconfig = 1;
539 break;
540 case MEDIA_TYPE_100M_FULL:
541 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
542 reconfig = 1;
543 break;
544 case MEDIA_TYPE_100M_HALF:
545 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
546 reconfig = 1;
547 break;
548 case MEDIA_TYPE_10M_FULL:
549 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
550 reconfig = 1;
551 break;
552 case MEDIA_TYPE_10M_HALF:
553 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
554 reconfig = 1;
555 break;
556 }
557
558 /* link result is our setting */
559 if (!reconfig) {
560 if (adapter->link_speed != speed
561 || adapter->link_duplex != duplex) {
562 adapter->link_speed = speed;
563 adapter->link_duplex = duplex;
564 atl1_setup_mac_ctrl(adapter);
565 dev_info(&adapter->pdev->dev,
566 "%s link is up %d Mbps %s\n",
567 netdev->name, adapter->link_speed,
568 adapter->link_duplex == FULL_DUPLEX ?
569 "full duplex" : "half duplex");
570 }
571 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
572 netif_carrier_on(netdev);
573 netif_wake_queue(netdev);
574 }
575 return ATL1_SUCCESS;
576 }
577
578 /* change orignal link status */
579 if (netif_carrier_ok(netdev)) {
580 adapter->link_speed = SPEED_0;
581 netif_carrier_off(netdev);
582 netif_stop_queue(netdev);
583 }
584
585 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
586 hw->media_type != MEDIA_TYPE_1000M_FULL) {
587 switch (hw->media_type) {
588 case MEDIA_TYPE_100M_FULL:
589 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
590 MII_CR_RESET;
591 break;
592 case MEDIA_TYPE_100M_HALF:
593 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
594 break;
595 case MEDIA_TYPE_10M_FULL:
596 phy_data =
597 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
598 break;
599 default: /* MEDIA_TYPE_10M_HALF: */
600 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
601 break;
602 }
603 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
604 return ATL1_SUCCESS;
605 }
606
607 /* auto-neg, insert timer to re-config phy */
608 if (!adapter->phy_timer_pending) {
609 adapter->phy_timer_pending = true;
610 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
611 }
612
613 return ATL1_SUCCESS;
614}
615
616static void atl1_check_for_link(struct atl1_adapter *adapter)
617{
618 struct net_device *netdev = adapter->netdev;
619 u16 phy_data = 0;
620
621 spin_lock(&adapter->lock);
622 adapter->phy_timer_pending = false;
623 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
624 atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
625 spin_unlock(&adapter->lock);
626
627 /* notify upper layer link down ASAP */
628 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
629 if (netif_carrier_ok(netdev)) { /* old link state: Up */
630 dev_info(&adapter->pdev->dev, "%s link is down\n",
631 netdev->name);
632 adapter->link_speed = SPEED_0;
633 netif_carrier_off(netdev);
634 netif_stop_queue(netdev);
635 }
636 }
637 schedule_work(&adapter->link_chg_task);
638}
639
640/*
641 * atl1_set_multi - Multicast and Promiscuous mode set
642 * @netdev: network interface device structure
643 *
644 * The set_multi entry point is called whenever the multicast address
645 * list or the network interface flags are updated. This routine is
646 * responsible for configuring the hardware for proper multicast,
647 * promiscuous mode, and all-multi behavior.
648 */
649static void atl1_set_multi(struct net_device *netdev)
650{
651 struct atl1_adapter *adapter = netdev_priv(netdev);
652 struct atl1_hw *hw = &adapter->hw;
653 struct dev_mc_list *mc_ptr;
654 u32 rctl;
655 u32 hash_value;
656
657 /* Check for Promiscuous and All Multicast modes */
658 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
659 if (netdev->flags & IFF_PROMISC)
660 rctl |= MAC_CTRL_PROMIS_EN;
661 else if (netdev->flags & IFF_ALLMULTI) {
662 rctl |= MAC_CTRL_MC_ALL_EN;
663 rctl &= ~MAC_CTRL_PROMIS_EN;
664 } else
665 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
666
667 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
668
669 /* clear the old settings from the multicast hash table */
670 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
671 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
672
673 /* compute mc addresses' hash value ,and put it into hash table */
674 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
675 hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr);
676 atl1_hash_set(hw, hash_value);
677 }
678}
679
680/*
681 * atl1_change_mtu - Change the Maximum Transfer Unit
682 * @netdev: network interface device structure
683 * @new_mtu: new value for maximum frame size
684 *
685 * Returns 0 on success, negative on failure
686 */
687static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
688{
689 struct atl1_adapter *adapter = netdev_priv(netdev);
690 int old_mtu = netdev->mtu;
691 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
692
693 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
694 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
695 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
696 return -EINVAL;
697 }
698
699 adapter->hw.max_frame_size = max_frame;
700 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
701 adapter->rx_buffer_len = (max_frame + 7) & ~7;
702 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
703
704 netdev->mtu = new_mtu;
705 if ((old_mtu != new_mtu) && netif_running(netdev)) {
706 atl1_down(adapter);
707 atl1_up(adapter);
708 }
709
710 return 0;
711}
712
713static void set_flow_ctrl_old(struct atl1_adapter *adapter)
714{
715 u32 hi, lo, value;
716
717 /* RFD Flow Control */
718 value = adapter->rfd_ring.count;
719 hi = value / 16;
720 if (hi < 2)
721 hi = 2;
722 lo = value * 7 / 8;
723
724 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
725 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
726 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
727
728 /* RRD Flow Control */
729 value = adapter->rrd_ring.count;
730 lo = value / 16;
731 hi = value * 7 / 8;
732 if (lo < 2)
733 lo = 2;
734 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
735 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
736 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
737}
738
739static void set_flow_ctrl_new(struct atl1_hw *hw)
740{
741 u32 hi, lo, value;
742
743 /* RXF Flow Control */
744 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
745 lo = value / 16;
746 if (lo < 192)
747 lo = 192;
748 hi = value * 7 / 8;
749 if (hi < lo)
750 hi = lo + 16;
751 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
752 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
753 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
754
755 /* RRD Flow Control */
756 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
757 lo = value / 8;
758 hi = value * 7 / 8;
759 if (lo < 2)
760 lo = 2;
761 if (hi < lo)
762 hi = lo + 3;
763 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
764 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
765 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
766}
767
768/*
769 * atl1_configure - Configure Transmit&Receive Unit after Reset
770 * @adapter: board private structure
771 *
772 * Configure the Tx /Rx unit of the MAC after a reset.
773 */
774static u32 atl1_configure(struct atl1_adapter *adapter)
775{
776 struct atl1_hw *hw = &adapter->hw;
777 u32 value;
778
779 /* clear interrupt status */
780 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
781
782 /* set MAC Address */
783 value = (((u32) hw->mac_addr[2]) << 24) |
784 (((u32) hw->mac_addr[3]) << 16) |
785 (((u32) hw->mac_addr[4]) << 8) |
786 (((u32) hw->mac_addr[5]));
787 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
788 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
789 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
790
791 /* tx / rx ring */
792
793 /* HI base address */
794 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
795 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
796 /* LO base address */
797 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
798 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
799 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
800 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
801 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
802 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
803 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
804 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
805 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
806 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
807
808 /* element count */
809 value = adapter->rrd_ring.count;
810 value <<= 16;
811 value += adapter->rfd_ring.count;
812 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
813 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
814 REG_DESC_TPD_RING_SIZE);
815
816 /* Load Ptr */
817 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
818
819 /* config Mailbox */
820 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
821 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
822 ((atomic_read(&adapter->rrd_ring.next_to_clean)
823 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
824 ((atomic_read(&adapter->rfd_ring.next_to_use)
825 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
826 iowrite32(value, hw->hw_addr + REG_MAILBOX);
827
828 /* config IPG/IFG */
829 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
830 << MAC_IPG_IFG_IPGT_SHIFT) |
831 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
832 << MAC_IPG_IFG_MIFG_SHIFT) |
833 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
834 << MAC_IPG_IFG_IPGR1_SHIFT) |
835 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
836 << MAC_IPG_IFG_IPGR2_SHIFT);
837 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
838
839 /* config Half-Duplex Control */
840 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
841 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
842 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
843 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
844 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
845 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
846 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
847 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
848
849 /* set Interrupt Moderator Timer */
850 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
851 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
852
853 /* set Interrupt Clear Timer */
854 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
855
856 /* set max frame size hw will accept */
857 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
858
859 /* jumbo size & rrd retirement timer */
860 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
861 << RXQ_JMBOSZ_TH_SHIFT) |
862 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
863 << RXQ_JMBO_LKAH_SHIFT) |
864 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
865 << RXQ_RRD_TIMER_SHIFT);
866 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
867
868 /* Flow Control */
869 switch (hw->dev_rev) {
870 case 0x8001:
871 case 0x9001:
872 case 0x9002:
873 case 0x9003:
874 set_flow_ctrl_old(adapter);
875 break;
876 default:
877 set_flow_ctrl_new(hw);
878 break;
879 }
880
881 /* config TXQ */
882 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
883 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
884 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
885 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
886 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
887 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
888 TXQ_CTRL_EN;
889 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
890
891 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
892 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
893 << TX_JUMBO_TASK_TH_SHIFT) |
894 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
895 << TX_TPD_MIN_IPG_SHIFT);
896 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
897
898 /* config RXQ */
899 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
900 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
901 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
902 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
903 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
904 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
905 RXQ_CTRL_EN;
906 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
907
908 /* config DMA Engine */
909 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
910 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
911 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
912 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
913 DMA_CTRL_DMAW_EN;
914 value |= (u32) hw->dma_ord;
915 if (atl1_rcb_128 == hw->rcb_value)
916 value |= DMA_CTRL_RCB_VALUE;
917 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
918
919 /* config CMB / SMB */
920 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
921 hw->cmb_tpd : adapter->tpd_ring.count;
922 value <<= 16;
923 value |= hw->cmb_rrd;
924 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
925 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
926 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
927 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
928
929 /* --- enable CMB / SMB */
930 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
931 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
932
933 value = ioread32(adapter->hw.hw_addr + REG_ISR);
934 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
935 value = 1; /* config failed */
936 else
937 value = 0;
938
939 /* clear all interrupt status */
940 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
941 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
942 return value;
943}
944
945/*
946 * atl1_pcie_patch - Patch for PCIE module
947 */
948static void atl1_pcie_patch(struct atl1_adapter *adapter)
949{
950 u32 value;
951
952 /* much vendor magic here */
953 value = 0x6500;
954 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
955 /* pcie flow control mode change */
956 value = ioread32(adapter->hw.hw_addr + 0x1008);
957 value |= 0x8000;
958 iowrite32(value, adapter->hw.hw_addr + 0x1008);
959}
960
961/*
962 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
963 * on PCI Command register is disable.
964 * The function enable this bit.
965 * Brackett, 2006/03/15
966 */
967static void atl1_via_workaround(struct atl1_adapter *adapter)
968{
969 unsigned long value;
970
971 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
972 if (value & PCI_COMMAND_INTX_DISABLE)
973 value &= ~PCI_COMMAND_INTX_DISABLE;
974 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
975}
976
977/*
978 * atl1_irq_enable - Enable default interrupt generation settings
979 * @adapter: board private structure
980 */
981static void atl1_irq_enable(struct atl1_adapter *adapter)
982{
983 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
984 ioread32(adapter->hw.hw_addr + REG_IMR);
985}
986
987/*
988 * atl1_irq_disable - Mask off interrupt generation on the NIC
989 * @adapter: board private structure
990 */
991static void atl1_irq_disable(struct atl1_adapter *adapter)
992{
993 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
994 ioread32(adapter->hw.hw_addr + REG_IMR);
995 synchronize_irq(adapter->pdev->irq);
996}
997
998static void atl1_clear_phy_int(struct atl1_adapter *adapter)
999{
1000 u16 phy_data;
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&adapter->lock, flags);
1004 atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
1005 spin_unlock_irqrestore(&adapter->lock, flags);
1006}
1007
1008static void atl1_inc_smb(struct atl1_adapter *adapter)
1009{
1010 struct stats_msg_block *smb = adapter->smb.smb;
1011
1012 /* Fill out the OS statistics structure */
1013 adapter->soft_stats.rx_packets += smb->rx_ok;
1014 adapter->soft_stats.tx_packets += smb->tx_ok;
1015 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1016 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1017 adapter->soft_stats.multicast += smb->rx_mcast;
1018 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1019 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1020
1021 /* Rx Errors */
1022 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1023 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1024 smb->rx_rrd_ov + smb->rx_align_err);
1025 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1026 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1027 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1028 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1029 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1030 smb->rx_rxf_ov);
1031
1032 adapter->soft_stats.rx_pause += smb->rx_pause;
1033 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1034 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1035
1036 /* Tx Errors */
1037 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1038 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1039 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1040 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1041 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1042
1043 adapter->soft_stats.excecol += smb->tx_abort_col;
1044 adapter->soft_stats.deffer += smb->tx_defer;
1045 adapter->soft_stats.scc += smb->tx_1_col;
1046 adapter->soft_stats.mcc += smb->tx_2_col;
1047 adapter->soft_stats.latecol += smb->tx_late_col;
1048 adapter->soft_stats.tx_underun += smb->tx_underrun;
1049 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1050 adapter->soft_stats.tx_pause += smb->tx_pause;
1051
1052 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
1053 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
1054 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
1055 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
1056 adapter->net_stats.multicast = adapter->soft_stats.multicast;
1057 adapter->net_stats.collisions = adapter->soft_stats.collisions;
1058 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
1059 adapter->net_stats.rx_over_errors =
1060 adapter->soft_stats.rx_missed_errors;
1061 adapter->net_stats.rx_length_errors =
1062 adapter->soft_stats.rx_length_errors;
1063 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1064 adapter->net_stats.rx_frame_errors =
1065 adapter->soft_stats.rx_frame_errors;
1066 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1067 adapter->net_stats.rx_missed_errors =
1068 adapter->soft_stats.rx_missed_errors;
1069 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
1070 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1071 adapter->net_stats.tx_aborted_errors =
1072 adapter->soft_stats.tx_aborted_errors;
1073 adapter->net_stats.tx_window_errors =
1074 adapter->soft_stats.tx_window_errors;
1075 adapter->net_stats.tx_carrier_errors =
1076 adapter->soft_stats.tx_carrier_errors;
1077}
1078
1079/*
1080 * atl1_get_stats - Get System Network Statistics
1081 * @netdev: network interface device structure
1082 *
1083 * Returns the address of the device statistics structure.
1084 * The statistics are actually updated from the timer callback.
1085 */
1086static struct net_device_stats *atl1_get_stats(struct net_device *netdev)
1087{
1088 struct atl1_adapter *adapter = netdev_priv(netdev);
1089 return &adapter->net_stats;
1090}
1091
1092static void atl1_update_mailbox(struct atl1_adapter *adapter)
1093{
1094 unsigned long flags;
1095 u32 tpd_next_to_use;
1096 u32 rfd_next_to_use;
1097 u32 rrd_next_to_clean;
1098 u32 value;
1099
1100 spin_lock_irqsave(&adapter->mb_lock, flags);
1101
1102 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1103 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1104 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1105
1106 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1107 MB_RFD_PROD_INDX_SHIFT) |
1108 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1109 MB_RRD_CONS_INDX_SHIFT) |
1110 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1111 MB_TPD_PROD_INDX_SHIFT);
1112 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1113
1114 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1115}
1116
1117static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1118 struct rx_return_desc *rrd, u16 offset)
1119{
1120 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1121
1122 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1123 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1124 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1125 rfd_ring->next_to_clean = 0;
1126 }
1127 }
1128}
1129
1130static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1131 struct rx_return_desc *rrd)
1132{
1133 u16 num_buf;
1134
1135 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1136 adapter->rx_buffer_len;
1137 if (rrd->num_buf == num_buf)
1138 /* clean alloc flag for bad rrd */
1139 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1140}
1141
1142static void atl1_rx_checksum(struct atl1_adapter *adapter,
1143 struct rx_return_desc *rrd, struct sk_buff *skb)
1144{
1145 struct pci_dev *pdev = adapter->pdev;
1146
1147 skb->ip_summed = CHECKSUM_NONE;
1148
1149 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1150 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1151 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1152 adapter->hw_csum_err++;
1153 dev_printk(KERN_DEBUG, &pdev->dev,
1154 "rx checksum error\n");
1155 return;
1156 }
1157 }
1158
1159 /* not IPv4 */
1160 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1161 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1162 return;
1163
1164 /* IPv4 packet */
1165 if (likely(!(rrd->err_flg &
1166 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1167 skb->ip_summed = CHECKSUM_UNNECESSARY;
1168 adapter->hw_csum_good++;
1169 return;
1170 }
1171
1172 /* IPv4, but hardware thinks its checksum is wrong */
1173 dev_printk(KERN_DEBUG, &pdev->dev,
1174 "hw csum wrong, pkt_flag:%x, err_flag:%x\n",
1175 rrd->pkt_flg, rrd->err_flg);
1176 skb->ip_summed = CHECKSUM_COMPLETE;
1177 skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
1178 adapter->hw_csum_err++;
1179 return;
1180}
1181
1182/*
1183 * atl1_alloc_rx_buffers - Replace used receive buffers
1184 * @adapter: address of board private structure
1185 */
1186static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1187{
1188 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1189 struct pci_dev *pdev = adapter->pdev;
1190 struct page *page;
1191 unsigned long offset;
1192 struct atl1_buffer *buffer_info, *next_info;
1193 struct sk_buff *skb;
1194 u16 num_alloc = 0;
1195 u16 rfd_next_to_use, next_next;
1196 struct rx_free_desc *rfd_desc;
1197
1198 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1199 if (++next_next == rfd_ring->count)
1200 next_next = 0;
1201 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1202 next_info = &rfd_ring->buffer_info[next_next];
1203
1204 while (!buffer_info->alloced && !next_info->alloced) {
1205 if (buffer_info->skb) {
1206 buffer_info->alloced = 1;
1207 goto next;
1208 }
1209
1210 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1211
1212 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
1213 if (unlikely(!skb)) { /* Better luck next round */
1214 adapter->net_stats.rx_dropped++;
1215 break;
1216 }
1217
1218 /*
1219 * Make buffer alignment 2 beyond a 16 byte boundary
1220 * this will result in a 16 byte aligned IP header after
1221 * the 14 byte MAC header is removed
1222 */
1223 skb_reserve(skb, NET_IP_ALIGN);
1224
1225 buffer_info->alloced = 1;
1226 buffer_info->skb = skb;
1227 buffer_info->length = (u16) adapter->rx_buffer_len;
1228 page = virt_to_page(skb->data);
1229 offset = (unsigned long)skb->data & ~PAGE_MASK;
1230 buffer_info->dma = pci_map_page(pdev, page, offset,
1231 adapter->rx_buffer_len,
1232 PCI_DMA_FROMDEVICE);
1233 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1234 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1235 rfd_desc->coalese = 0;
1236
1237next:
1238 rfd_next_to_use = next_next;
1239 if (unlikely(++next_next == rfd_ring->count))
1240 next_next = 0;
1241
1242 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1243 next_info = &rfd_ring->buffer_info[next_next];
1244 num_alloc++;
1245 }
1246
1247 if (num_alloc) {
1248 /*
1249 * Force memory writes to complete before letting h/w
1250 * know there are new descriptors to fetch. (Only
1251 * applicable for weak-ordered memory model archs,
1252 * such as IA-64).
1253 */
1254 wmb();
1255 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1256 }
1257 return num_alloc;
1258}
1259
1260static void atl1_intr_rx(struct atl1_adapter *adapter)
1261{
1262 int i, count;
1263 u16 length;
1264 u16 rrd_next_to_clean;
1265 u32 value;
1266 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1267 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1268 struct atl1_buffer *buffer_info;
1269 struct rx_return_desc *rrd;
1270 struct sk_buff *skb;
1271
1272 count = 0;
1273
1274 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1275
1276 while (1) {
1277 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1278 i = 1;
1279 if (likely(rrd->xsz.valid)) { /* packet valid */
1280chk_rrd:
1281 /* check rrd status */
1282 if (likely(rrd->num_buf == 1))
1283 goto rrd_ok;
1284
1285 /* rrd seems to be bad */
1286 if (unlikely(i-- > 0)) {
1287 /* rrd may not be DMAed completely */
1288 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1289 "incomplete RRD DMA transfer\n");
1290 udelay(1);
1291 goto chk_rrd;
1292 }
1293 /* bad rrd */
1294 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1295 "bad RRD\n");
1296 /* see if update RFD index */
1297 if (rrd->num_buf > 1)
1298 atl1_update_rfd_index(adapter, rrd);
1299
1300 /* update rrd */
1301 rrd->xsz.valid = 0;
1302 if (++rrd_next_to_clean == rrd_ring->count)
1303 rrd_next_to_clean = 0;
1304 count++;
1305 continue;
1306 } else { /* current rrd still not be updated */
1307
1308 break;
1309 }
1310rrd_ok:
1311 /* clean alloc flag for bad rrd */
1312 atl1_clean_alloc_flag(adapter, rrd, 0);
1313
1314 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1315 if (++rfd_ring->next_to_clean == rfd_ring->count)
1316 rfd_ring->next_to_clean = 0;
1317
1318 /* update rrd next to clean */
1319 if (++rrd_next_to_clean == rrd_ring->count)
1320 rrd_next_to_clean = 0;
1321 count++;
1322
1323 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1324 if (!(rrd->err_flg &
1325 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
1326 | ERR_FLAG_LEN))) {
1327 /* packet error, don't need upstream */
1328 buffer_info->alloced = 0;
1329 rrd->xsz.valid = 0;
1330 continue;
1331 }
1332 }
1333
1334 /* Good Receive */
1335 pci_unmap_page(adapter->pdev, buffer_info->dma,
1336 buffer_info->length, PCI_DMA_FROMDEVICE);
1337 skb = buffer_info->skb;
1338 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
1339
1340 skb_put(skb, length - ETH_FCS_LEN);
1341
1342 /* Receive Checksum Offload */
1343 atl1_rx_checksum(adapter, rrd, skb);
1344 skb->protocol = eth_type_trans(skb, adapter->netdev);
1345
1346 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
1347 u16 vlan_tag = (rrd->vlan_tag >> 4) |
1348 ((rrd->vlan_tag & 7) << 13) |
1349 ((rrd->vlan_tag & 8) << 9);
1350 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
1351 } else
1352 netif_rx(skb);
1353
1354 /* let protocol layer free skb */
1355 buffer_info->skb = NULL;
1356 buffer_info->alloced = 0;
1357 rrd->xsz.valid = 0;
1358
1359 adapter->netdev->last_rx = jiffies;
1360 }
1361
1362 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
1363
1364 atl1_alloc_rx_buffers(adapter);
1365
1366 /* update mailbox ? */
1367 if (count) {
1368 u32 tpd_next_to_use;
1369 u32 rfd_next_to_use;
1370
1371 spin_lock(&adapter->mb_lock);
1372
1373 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1374 rfd_next_to_use =
1375 atomic_read(&adapter->rfd_ring.next_to_use);
1376 rrd_next_to_clean =
1377 atomic_read(&adapter->rrd_ring.next_to_clean);
1378 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1379 MB_RFD_PROD_INDX_SHIFT) |
1380 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1381 MB_RRD_CONS_INDX_SHIFT) |
1382 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1383 MB_TPD_PROD_INDX_SHIFT);
1384 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1385 spin_unlock(&adapter->mb_lock);
1386 }
1387}
1388
1389static void atl1_intr_tx(struct atl1_adapter *adapter)
1390{
1391 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1392 struct atl1_buffer *buffer_info;
1393 u16 sw_tpd_next_to_clean;
1394 u16 cmb_tpd_next_to_clean;
1395
1396 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1397 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
1398
1399 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
1400 struct tx_packet_desc *tpd;
1401
1402 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
1403 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
1404 if (buffer_info->dma) {
1405 pci_unmap_page(adapter->pdev, buffer_info->dma,
1406 buffer_info->length, PCI_DMA_TODEVICE);
1407 buffer_info->dma = 0;
1408 }
1409
1410 if (buffer_info->skb) {
1411 dev_kfree_skb_irq(buffer_info->skb);
1412 buffer_info->skb = NULL;
1413 }
1414 tpd->buffer_addr = 0;
1415 tpd->desc.data = 0;
1416
1417 if (++sw_tpd_next_to_clean == tpd_ring->count)
1418 sw_tpd_next_to_clean = 0;
1419 }
1420 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
1421
1422 if (netif_queue_stopped(adapter->netdev)
1423 && netif_carrier_ok(adapter->netdev))
1424 netif_wake_queue(adapter->netdev);
1425}
1426
1427static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
1428{
1429 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1430 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
1431 return ((next_to_clean > next_to_use) ?
1432 next_to_clean - next_to_use - 1 :
1433 tpd_ring->count + next_to_clean - next_to_use - 1);
1434}
1435
1436static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
1437 struct tso_param *tso)
1438{
1439 /* We enter this function holding a spinlock. */
1440 u8 ipofst;
1441 int err;
1442
1443 if (skb_shinfo(skb)->gso_size) {
1444 if (skb_header_cloned(skb)) {
1445 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1446 if (unlikely(err))
1447 return err;
1448 }
1449
1450 if (skb->protocol == ntohs(ETH_P_IP)) {
1451 struct iphdr *iph = ip_hdr(skb);
1452
1453 iph->tot_len = 0;
1454 iph->check = 0;
1455 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1456 iph->daddr, 0, IPPROTO_TCP, 0);
1457 ipofst = skb_network_offset(skb);
1458 if (ipofst != ETH_HLEN) /* 802.3 frame */
1459 tso->tsopl |= 1 << TSO_PARAM_ETHTYPE_SHIFT;
1460
1461 tso->tsopl |= (iph->ihl &
1462 CSUM_PARAM_IPHL_MASK) << CSUM_PARAM_IPHL_SHIFT;
1463 tso->tsopl |= (tcp_hdrlen(skb) &
1464 TSO_PARAM_TCPHDRLEN_MASK) <<
1465 TSO_PARAM_TCPHDRLEN_SHIFT;
1466 tso->tsopl |= (skb_shinfo(skb)->gso_size &
1467 TSO_PARAM_MSS_MASK) << TSO_PARAM_MSS_SHIFT;
1468 tso->tsopl |= 1 << TSO_PARAM_IPCKSUM_SHIFT;
1469 tso->tsopl |= 1 << TSO_PARAM_TCPCKSUM_SHIFT;
1470 tso->tsopl |= 1 << TSO_PARAM_SEGMENT_SHIFT;
1471 return true;
1472 }
1473 }
1474 return false;
1475}
1476
1477static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
1478 struct csum_param *csum)
1479{
1480 u8 css, cso;
1481
1482 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1483 cso = skb_transport_offset(skb);
1484 css = cso + skb->csum_offset;
1485 if (unlikely(cso & 0x1)) {
1486 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1487 "payload offset not an even number\n");
1488 return -1;
1489 }
1490 csum->csumpl |= (cso & CSUM_PARAM_PLOADOFFSET_MASK) <<
1491 CSUM_PARAM_PLOADOFFSET_SHIFT;
1492 csum->csumpl |= (css & CSUM_PARAM_XSUMOFFSET_MASK) <<
1493 CSUM_PARAM_XSUMOFFSET_SHIFT;
1494 csum->csumpl |= 1 << CSUM_PARAM_CUSTOMCKSUM_SHIFT;
1495 return true;
1496 }
1497
1498 return true;
1499}
1500
1501static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
1502 bool tcp_seg)
1503{
1504 /* We enter this function holding a spinlock. */
1505 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1506 struct atl1_buffer *buffer_info;
1507 struct page *page;
1508 int first_buf_len = skb->len;
1509 unsigned long offset;
1510 unsigned int nr_frags;
1511 unsigned int f;
1512 u16 tpd_next_to_use;
1513 u16 proto_hdr_len;
1514 u16 len12;
1515
1516 first_buf_len -= skb->data_len;
1517 nr_frags = skb_shinfo(skb)->nr_frags;
1518 tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
1519 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1520 if (unlikely(buffer_info->skb))
1521 BUG();
1522 buffer_info->skb = NULL; /* put skb in last TPD */
1523
1524 if (tcp_seg) {
1525 /* TSO/GSO */
1526 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1527 buffer_info->length = proto_hdr_len;
1528 page = virt_to_page(skb->data);
1529 offset = (unsigned long)skb->data & ~PAGE_MASK;
1530 buffer_info->dma = pci_map_page(adapter->pdev, page,
1531 offset, proto_hdr_len,
1532 PCI_DMA_TODEVICE);
1533
1534 if (++tpd_next_to_use == tpd_ring->count)
1535 tpd_next_to_use = 0;
1536
1537 if (first_buf_len > proto_hdr_len) {
1538 int i, m;
1539
1540 len12 = first_buf_len - proto_hdr_len;
1541 m = (len12 + ATL1_MAX_TX_BUF_LEN - 1) /
1542 ATL1_MAX_TX_BUF_LEN;
1543 for (i = 0; i < m; i++) {
1544 buffer_info =
1545 &tpd_ring->buffer_info[tpd_next_to_use];
1546 buffer_info->skb = NULL;
1547 buffer_info->length =
1548 (ATL1_MAX_TX_BUF_LEN >=
1549 len12) ? ATL1_MAX_TX_BUF_LEN : len12;
1550 len12 -= buffer_info->length;
1551 page = virt_to_page(skb->data +
1552 (proto_hdr_len +
1553 i * ATL1_MAX_TX_BUF_LEN));
1554 offset = (unsigned long)(skb->data +
1555 (proto_hdr_len +
1556 i * ATL1_MAX_TX_BUF_LEN)) & ~PAGE_MASK;
1557 buffer_info->dma = pci_map_page(adapter->pdev,
1558 page, offset, buffer_info->length,
1559 PCI_DMA_TODEVICE);
1560 if (++tpd_next_to_use == tpd_ring->count)
1561 tpd_next_to_use = 0;
1562 }
1563 }
1564 } else {
1565 /* not TSO/GSO */
1566 buffer_info->length = first_buf_len;
1567 page = virt_to_page(skb->data);
1568 offset = (unsigned long)skb->data & ~PAGE_MASK;
1569 buffer_info->dma = pci_map_page(adapter->pdev, page,
1570 offset, first_buf_len, PCI_DMA_TODEVICE);
1571 if (++tpd_next_to_use == tpd_ring->count)
1572 tpd_next_to_use = 0;
1573 }
1574
1575 for (f = 0; f < nr_frags; f++) {
1576 struct skb_frag_struct *frag;
1577 u16 lenf, i, m;
1578
1579 frag = &skb_shinfo(skb)->frags[f];
1580 lenf = frag->size;
1581
1582 m = (lenf + ATL1_MAX_TX_BUF_LEN - 1) / ATL1_MAX_TX_BUF_LEN;
1583 for (i = 0; i < m; i++) {
1584 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1585 if (unlikely(buffer_info->skb))
1586 BUG();
1587 buffer_info->skb = NULL;
1588 buffer_info->length = (lenf > ATL1_MAX_TX_BUF_LEN) ?
1589 ATL1_MAX_TX_BUF_LEN : lenf;
1590 lenf -= buffer_info->length;
1591 buffer_info->dma = pci_map_page(adapter->pdev,
1592 frag->page,
1593 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
1594 buffer_info->length, PCI_DMA_TODEVICE);
1595
1596 if (++tpd_next_to_use == tpd_ring->count)
1597 tpd_next_to_use = 0;
1598 }
1599 }
1600
1601 /* last tpd's buffer-info */
1602 buffer_info->skb = skb;
1603}
1604
1605static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
1606 union tpd_descr *descr)
1607{
1608 /* We enter this function holding a spinlock. */
1609 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1610 int j;
1611 u32 val;
1612 struct atl1_buffer *buffer_info;
1613 struct tx_packet_desc *tpd;
1614 u16 tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
1615
1616 for (j = 0; j < count; j++) {
1617 buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
1618 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, tpd_next_to_use);
1619 tpd->desc.csum.csumpu = descr->csum.csumpu;
1620 tpd->desc.csum.csumpl = descr->csum.csumpl;
1621 tpd->desc.tso.tsopu = descr->tso.tsopu;
1622 tpd->desc.tso.tsopl = descr->tso.tsopl;
1623 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
1624 tpd->desc.data = descr->data;
1625 tpd->desc.csum.csumpu |= (cpu_to_le16(buffer_info->length) &
1626 CSUM_PARAM_BUFLEN_MASK) << CSUM_PARAM_BUFLEN_SHIFT;
1627
1628 val = (descr->tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
1629 TSO_PARAM_SEGMENT_MASK;
1630 if (val && !j)
1631 tpd->desc.tso.tsopl |= 1 << TSO_PARAM_HDRFLAG_SHIFT;
1632
1633 if (j == (count - 1))
1634 tpd->desc.csum.csumpl |= 1 << CSUM_PARAM_EOP_SHIFT;
1635
1636 if (++tpd_next_to_use == tpd_ring->count)
1637 tpd_next_to_use = 0;
1638 }
1639 /*
1640 * Force memory writes to complete before letting h/w
1641 * know there are new descriptors to fetch. (Only
1642 * applicable for weak-ordered memory model archs,
1643 * such as IA-64).
1644 */
1645 wmb();
1646
1647 atomic_set(&tpd_ring->next_to_use, (int)tpd_next_to_use);
1648}
1649
1650static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1651{
1652 struct atl1_adapter *adapter = netdev_priv(netdev);
1653 int len = skb->len;
1654 int tso;
1655 int count = 1;
1656 int ret_val;
1657 u32 val;
1658 union tpd_descr param;
1659 u16 frag_size;
1660 u16 vlan_tag;
1661 unsigned long flags;
1662 unsigned int nr_frags = 0;
1663 unsigned int mss = 0;
1664 unsigned int f;
1665 unsigned int proto_hdr_len;
1666
1667 len -= skb->data_len;
1668
1669 if (unlikely(skb->len == 0)) {
1670 dev_kfree_skb_any(skb);
1671 return NETDEV_TX_OK;
1672 }
1673
1674 param.data = 0;
1675 param.tso.tsopu = 0;
1676 param.tso.tsopl = 0;
1677 param.csum.csumpu = 0;
1678 param.csum.csumpl = 0;
1679
1680 /* nr_frags will be nonzero if we're doing scatter/gather (SG) */
1681 nr_frags = skb_shinfo(skb)->nr_frags;
1682 for (f = 0; f < nr_frags; f++) {
1683 frag_size = skb_shinfo(skb)->frags[f].size;
1684 if (frag_size)
1685 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
1686 ATL1_MAX_TX_BUF_LEN;
1687 }
1688
1689 /* mss will be nonzero if we're doing segment offload (TSO/GSO) */
1690 mss = skb_shinfo(skb)->gso_size;
1691 if (mss) {
1692 if (skb->protocol == htons(ETH_P_IP)) {
1693 proto_hdr_len = (skb_transport_offset(skb) +
1694 tcp_hdrlen(skb));
1695 if (unlikely(proto_hdr_len > len)) {
1696 dev_kfree_skb_any(skb);
1697 return NETDEV_TX_OK;
1698 }
1699 /* need additional TPD ? */
1700 if (proto_hdr_len != len)
1701 count += (len - proto_hdr_len +
1702 ATL1_MAX_TX_BUF_LEN - 1) /
1703 ATL1_MAX_TX_BUF_LEN;
1704 }
1705 }
1706
1707 if (!spin_trylock_irqsave(&adapter->lock, flags)) {
1708 /* Can't get lock - tell upper layer to requeue */
1709 dev_printk(KERN_DEBUG, &adapter->pdev->dev, "tx locked\n");
1710 return NETDEV_TX_LOCKED;
1711 }
1712
1713 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
1714 /* not enough descriptors */
1715 netif_stop_queue(netdev);
1716 spin_unlock_irqrestore(&adapter->lock, flags);
1717 dev_printk(KERN_DEBUG, &adapter->pdev->dev, "tx busy\n");
1718 return NETDEV_TX_BUSY;
1719 }
1720
1721 param.data = 0;
1722
1723 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
1724 vlan_tag = vlan_tx_tag_get(skb);
1725 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
1726 ((vlan_tag >> 9) & 0x8);
1727 param.csum.csumpl |= 1 << CSUM_PARAM_INSVLAG_SHIFT;
1728 param.csum.csumpu |= (vlan_tag & CSUM_PARAM_VALANTAG_MASK) <<
1729 CSUM_PARAM_VALAN_SHIFT;
1730 }
1731
1732 tso = atl1_tso(adapter, skb, &param.tso);
1733 if (tso < 0) {
1734 spin_unlock_irqrestore(&adapter->lock, flags);
1735 dev_kfree_skb_any(skb);
1736 return NETDEV_TX_OK;
1737 }
1738
1739 if (!tso) {
1740 ret_val = atl1_tx_csum(adapter, skb, &param.csum);
1741 if (ret_val < 0) {
1742 spin_unlock_irqrestore(&adapter->lock, flags);
1743 dev_kfree_skb_any(skb);
1744 return NETDEV_TX_OK;
1745 }
1746 }
1747
1748 val = (param.csum.csumpl >> CSUM_PARAM_SEGMENT_SHIFT) &
1749 CSUM_PARAM_SEGMENT_MASK;
1750 atl1_tx_map(adapter, skb, 1 == val);
1751 atl1_tx_queue(adapter, count, &param);
1752 netdev->trans_start = jiffies;
1753 spin_unlock_irqrestore(&adapter->lock, flags);
1754 atl1_update_mailbox(adapter);
1755 return NETDEV_TX_OK;
1756}
1757
1758/*
1759 * atl1_intr - Interrupt Handler
1760 * @irq: interrupt number
1761 * @data: pointer to a network interface device structure
1762 * @pt_regs: CPU registers structure
1763 */
1764static irqreturn_t atl1_intr(int irq, void *data)
1765{
1766 struct atl1_adapter *adapter = netdev_priv(data);
1767 u32 status;
1768 u8 update_rx;
1769 int max_ints = 10;
1770
1771 status = adapter->cmb.cmb->int_stats;
1772 if (!status)
1773 return IRQ_NONE;
1774
1775 update_rx = 0;
1776
1777 do {
1778 /* clear CMB interrupt status at once */
1779 adapter->cmb.cmb->int_stats = 0;
1780
1781 if (status & ISR_GPHY) /* clear phy status */
1782 atl1_clear_phy_int(adapter);
1783
1784 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
1785 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
1786
1787 /* check if SMB intr */
1788 if (status & ISR_SMB)
1789 atl1_inc_smb(adapter);
1790
1791 /* check if PCIE PHY Link down */
1792 if (status & ISR_PHY_LINKDOWN) {
1793 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1794 "pcie phy link down %x\n", status);
1795 if (netif_running(adapter->netdev)) { /* reset MAC */
1796 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
1797 schedule_work(&adapter->pcie_dma_to_rst_task);
1798 return IRQ_HANDLED;
1799 }
1800 }
1801
1802 /* check if DMA read/write error ? */
1803 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1804 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1805 "pcie DMA r/w error (status = 0x%x)\n",
1806 status);
1807 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
1808 schedule_work(&adapter->pcie_dma_to_rst_task);
1809 return IRQ_HANDLED;
1810 }
1811
1812 /* link event */
1813 if (status & ISR_GPHY) {
1814 adapter->soft_stats.tx_carrier_errors++;
1815 atl1_check_for_link(adapter);
1816 }
1817
1818 /* transmit event */
1819 if (status & ISR_CMB_TX)
1820 atl1_intr_tx(adapter);
1821
1822 /* rx exception */
1823 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
1824 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
1825 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
1826 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
1827 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
1828 ISR_HOST_RRD_OV))
1829 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1830 "rx exception, ISR = 0x%x\n", status);
1831 atl1_intr_rx(adapter);
1832 }
1833
1834 if (--max_ints < 0)
1835 break;
1836
1837 } while ((status = adapter->cmb.cmb->int_stats));
1838
1839 /* re-enable Interrupt */
1840 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
1841 return IRQ_HANDLED;
1842}
1843
1844/*
1845 * atl1_watchdog - Timer Call-back
1846 * @data: pointer to netdev cast into an unsigned long
1847 */
1848static void atl1_watchdog(unsigned long data)
1849{
1850 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
1851
1852 /* Reset the timer */
1853 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1854}
1855
1856/*
1857 * atl1_phy_config - Timer Call-back
1858 * @data: pointer to netdev cast into an unsigned long
1859 */
1860static void atl1_phy_config(unsigned long data)
1861{
1862 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
1863 struct atl1_hw *hw = &adapter->hw;
1864 unsigned long flags;
1865
1866 spin_lock_irqsave(&adapter->lock, flags);
1867 adapter->phy_timer_pending = false;
1868 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1869 atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg);
1870 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
1871 spin_unlock_irqrestore(&adapter->lock, flags);
1872}
1873
1874/*
1875 * atl1_tx_timeout - Respond to a Tx Hang
1876 * @netdev: network interface device structure
1877 */
1878static void atl1_tx_timeout(struct net_device *netdev)
1879{
1880 struct atl1_adapter *adapter = netdev_priv(netdev);
1881 /* Do the reset outside of interrupt context */
1882 schedule_work(&adapter->tx_timeout_task);
1883}
1884
1885/*
1886 * Orphaned vendor comment left intact here:
1887 * <vendor comment>
1888 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
1889 * will assert. We do soft reset <0x1400=1> according
1890 * with the SPEC. BUT, it seemes that PCIE or DMA
1891 * state-machine will not be reset. DMAR_TO_INT will
1892 * assert again and again.
1893 * </vendor comment>
1894 */
1895static void atl1_tx_timeout_task(struct work_struct *work)
1896{
1897 struct atl1_adapter *adapter =
1898 container_of(work, struct atl1_adapter, tx_timeout_task);
1899 struct net_device *netdev = adapter->netdev;
1900
1901 netif_device_detach(netdev);
1902 atl1_down(adapter);
1903 atl1_up(adapter);
1904 netif_device_attach(netdev);
1905}
1906
1907/*
1908 * atl1_link_chg_task - deal with link change event Out of interrupt context
1909 */
1910static void atl1_link_chg_task(struct work_struct *work)
1911{
1912 struct atl1_adapter *adapter =
1913 container_of(work, struct atl1_adapter, link_chg_task);
1914 unsigned long flags;
1915
1916 spin_lock_irqsave(&adapter->lock, flags);
1917 atl1_check_link(adapter);
1918 spin_unlock_irqrestore(&adapter->lock, flags);
1919}
1920
1921static void atl1_vlan_rx_register(struct net_device *netdev,
1922 struct vlan_group *grp)
1923{
1924 struct atl1_adapter *adapter = netdev_priv(netdev);
1925 unsigned long flags;
1926 u32 ctrl;
1927
1928 spin_lock_irqsave(&adapter->lock, flags);
1929 /* atl1_irq_disable(adapter); */
1930 adapter->vlgrp = grp;
1931
1932 if (grp) {
1933 /* enable VLAN tag insert/strip */
1934 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1935 ctrl |= MAC_CTRL_RMV_VLAN;
1936 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1937 } else {
1938 /* disable VLAN tag insert/strip */
1939 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
1940 ctrl &= ~MAC_CTRL_RMV_VLAN;
1941 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
1942 }
1943
1944 /* atl1_irq_enable(adapter); */
1945 spin_unlock_irqrestore(&adapter->lock, flags);
1946}
1947
1948static void atl1_restore_vlan(struct atl1_adapter *adapter)
1949{
1950 atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1951}
1952
1953int atl1_reset(struct atl1_adapter *adapter)
1954{
1955 int ret;
1956
1957 ret = atl1_reset_hw(&adapter->hw);
1958 if (ret != ATL1_SUCCESS)
1959 return ret;
1960 return atl1_init_hw(&adapter->hw);
1961}
1962
1963s32 atl1_up(struct atl1_adapter *adapter)
1964{
1965 struct net_device *netdev = adapter->netdev;
1966 int err;
1967 int irq_flags = IRQF_SAMPLE_RANDOM;
1968
1969 /* hardware has been reset, we need to reload some things */
1970 atl1_set_multi(netdev);
1971 atl1_init_ring_ptrs(adapter);
1972 atl1_restore_vlan(adapter);
1973 err = atl1_alloc_rx_buffers(adapter);
1974 if (unlikely(!err)) /* no RX BUFFER allocated */
1975 return -ENOMEM;
1976
1977 if (unlikely(atl1_configure(adapter))) {
1978 err = -EIO;
1979 goto err_up;
1980 }
1981
1982 err = pci_enable_msi(adapter->pdev);
1983 if (err) {
1984 dev_info(&adapter->pdev->dev,
1985 "Unable to enable MSI: %d\n", err);
1986 irq_flags |= IRQF_SHARED;
1987 }
1988
1989 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
1990 netdev->name, netdev);
1991 if (unlikely(err))
1992 goto err_up;
1993
1994 mod_timer(&adapter->watchdog_timer, jiffies);
1995 atl1_irq_enable(adapter);
1996 atl1_check_link(adapter);
1997 return 0;
1998
1999err_up:
2000 pci_disable_msi(adapter->pdev);
2001 /* free rx_buffers */
2002 atl1_clean_rx_ring(adapter);
2003 return err;
2004}
2005
2006void atl1_down(struct atl1_adapter *adapter)
2007{
2008 struct net_device *netdev = adapter->netdev;
2009
2010 del_timer_sync(&adapter->watchdog_timer);
2011 del_timer_sync(&adapter->phy_config_timer);
2012 adapter->phy_timer_pending = false;
2013
2014 atl1_irq_disable(adapter);
2015 free_irq(adapter->pdev->irq, netdev);
2016 pci_disable_msi(adapter->pdev);
2017 atl1_reset_hw(&adapter->hw);
2018 adapter->cmb.cmb->int_stats = 0;
2019
2020 adapter->link_speed = SPEED_0;
2021 adapter->link_duplex = -1;
2022 netif_carrier_off(netdev);
2023 netif_stop_queue(netdev);
2024
2025 atl1_clean_tx_ring(adapter);
2026 atl1_clean_rx_ring(adapter);
2027}
2028
2029/*
2030 * atl1_open - Called when a network interface is made active
2031 * @netdev: network interface device structure
2032 *
2033 * Returns 0 on success, negative value on failure
2034 *
2035 * The open entry point is called when a network interface is made
2036 * active by the system (IFF_UP). At this point all resources needed
2037 * for transmit and receive operations are allocated, the interrupt
2038 * handler is registered with the OS, the watchdog timer is started,
2039 * and the stack is notified that the interface is ready.
2040 */
2041static int atl1_open(struct net_device *netdev)
2042{
2043 struct atl1_adapter *adapter = netdev_priv(netdev);
2044 int err;
2045
2046 /* allocate transmit descriptors */
2047 err = atl1_setup_ring_resources(adapter);
2048 if (err)
2049 return err;
2050
2051 err = atl1_up(adapter);
2052 if (err)
2053 goto err_up;
2054
2055 return 0;
2056
2057err_up:
2058 atl1_reset(adapter);
2059 return err;
2060}
2061
2062/*
2063 * atl1_close - Disables a network interface
2064 * @netdev: network interface device structure
2065 *
2066 * Returns 0, this is not allowed to fail
2067 *
2068 * The close entry point is called when an interface is de-activated
2069 * by the OS. The hardware is still under the drivers control, but
2070 * needs to be disabled. A global MAC reset is issued to stop the
2071 * hardware, and all transmit and receive resources are freed.
2072 */
2073static int atl1_close(struct net_device *netdev)
2074{
2075 struct atl1_adapter *adapter = netdev_priv(netdev);
2076 atl1_down(adapter);
2077 atl1_free_ring_resources(adapter);
2078 return 0;
2079}
2080
2081#ifdef CONFIG_PM
2082static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2083{
2084 struct net_device *netdev = pci_get_drvdata(pdev);
2085 struct atl1_adapter *adapter = netdev_priv(netdev);
2086 struct atl1_hw *hw = &adapter->hw;
2087 u32 ctrl = 0;
2088 u32 wufc = adapter->wol;
2089
2090 netif_device_detach(netdev);
2091 if (netif_running(netdev))
2092 atl1_down(adapter);
2093
2094 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2095 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2096 if (ctrl & BMSR_LSTATUS)
2097 wufc &= ~ATL1_WUFC_LNKC;
2098
2099 /* reduce speed to 10/100M */
2100 if (wufc) {
2101 atl1_phy_enter_power_saving(hw);
2102 /* if resume, let driver to re- setup link */
2103 hw->phy_configured = false;
2104 atl1_set_mac_addr(hw);
2105 atl1_set_multi(netdev);
2106
2107 ctrl = 0;
2108 /* turn on magic packet wol */
2109 if (wufc & ATL1_WUFC_MAG)
2110 ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2111
2112 /* turn on Link change WOL */
2113 if (wufc & ATL1_WUFC_LNKC)
2114 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2115 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2116
2117 /* turn on all-multi mode if wake on multicast is enabled */
2118 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
2119 ctrl &= ~MAC_CTRL_DBG;
2120 ctrl &= ~MAC_CTRL_PROMIS_EN;
2121 if (wufc & ATL1_WUFC_MC)
2122 ctrl |= MAC_CTRL_MC_ALL_EN;
2123 else
2124 ctrl &= ~MAC_CTRL_MC_ALL_EN;
2125
2126 /* turn on broadcast mode if wake on-BC is enabled */
2127 if (wufc & ATL1_WUFC_BC)
2128 ctrl |= MAC_CTRL_BC_EN;
2129 else
2130 ctrl &= ~MAC_CTRL_BC_EN;
2131
2132 /* enable RX */
2133 ctrl |= MAC_CTRL_RX_EN;
2134 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2135 pci_enable_wake(pdev, PCI_D3hot, 1);
2136 pci_enable_wake(pdev, PCI_D3cold, 1);
2137 } else {
2138 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2139 pci_enable_wake(pdev, PCI_D3hot, 0);
2140 pci_enable_wake(pdev, PCI_D3cold, 0);
2141 }
2142
2143 pci_save_state(pdev);
2144 pci_disable_device(pdev);
2145
2146 pci_set_power_state(pdev, PCI_D3hot);
2147
2148 return 0;
2149}
2150
2151static int atl1_resume(struct pci_dev *pdev)
2152{
2153 struct net_device *netdev = pci_get_drvdata(pdev);
2154 struct atl1_adapter *adapter = netdev_priv(netdev);
2155 u32 ret_val;
2156
2157 pci_set_power_state(pdev, 0);
2158 pci_restore_state(pdev);
2159
2160 ret_val = pci_enable_device(pdev);
2161 pci_enable_wake(pdev, PCI_D3hot, 0);
2162 pci_enable_wake(pdev, PCI_D3cold, 0);
2163
2164 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2165 atl1_reset(adapter);
2166
2167 if (netif_running(netdev))
2168 atl1_up(adapter);
2169 netif_device_attach(netdev);
2170
2171 atl1_via_workaround(adapter);
2172
2173 return 0;
2174}
2175#else
2176#define atl1_suspend NULL
2177#define atl1_resume NULL
2178#endif
2179
2180#ifdef CONFIG_NET_POLL_CONTROLLER
2181static void atl1_poll_controller(struct net_device *netdev)
2182{
2183 disable_irq(netdev->irq);
2184 atl1_intr(netdev->irq, netdev);
2185 enable_irq(netdev->irq);
2186}
2187#endif
2188
2189/*
2190 * atl1_probe - Device Initialization Routine
2191 * @pdev: PCI device information struct
2192 * @ent: entry in atl1_pci_tbl
2193 *
2194 * Returns 0 on success, negative on failure
2195 *
2196 * atl1_probe initializes an adapter identified by a pci_dev structure.
2197 * The OS initialization, configuring of the adapter private structure,
2198 * and a hardware reset occur.
2199 */
2200static int __devinit atl1_probe(struct pci_dev *pdev,
2201 const struct pci_device_id *ent)
2202{
2203 struct net_device *netdev;
2204 struct atl1_adapter *adapter;
2205 static int cards_found = 0;
2206 int err;
2207
2208 err = pci_enable_device(pdev);
2209 if (err)
2210 return err;
2211
2212 /*
2213 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2214 * shared register for the high 32 bits, so only a single, aligned,
2215 * 4 GB physical address range can be used at a time.
2216 *
2217 * Supporting 64-bit DMA on this hardware is more trouble than it's
2218 * worth. It is far easier to limit to 32-bit DMA than update
2219 * various kernel subsystems to support the mechanics required by a
2220 * fixed-high-32-bit system.
2221 */
2222 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2223 if (err) {
2224 dev_err(&pdev->dev, "no usable DMA configuration\n");
2225 goto err_dma;
2226 }
2227 /* Mark all PCI regions associated with PCI device
2228 * pdev as being reserved by owner atl1_driver_name
2229 */
2230 err = pci_request_regions(pdev, atl1_driver_name);
2231 if (err)
2232 goto err_request_regions;
2233
2234 /* Enables bus-mastering on the device and calls
2235 * pcibios_set_master to do the needed arch specific settings
2236 */
2237 pci_set_master(pdev);
2238
2239 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2240 if (!netdev) {
2241 err = -ENOMEM;
2242 goto err_alloc_etherdev;
2243 }
2244 SET_NETDEV_DEV(netdev, &pdev->dev);
2245
2246 pci_set_drvdata(pdev, netdev);
2247 adapter = netdev_priv(netdev);
2248 adapter->netdev = netdev;
2249 adapter->pdev = pdev;
2250 adapter->hw.back = adapter;
2251
2252 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2253 if (!adapter->hw.hw_addr) {
2254 err = -EIO;
2255 goto err_pci_iomap;
2256 }
2257 /* get device revision number */
2258 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2259 (REG_MASTER_CTRL + 2));
2260 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
2261
2262 /* set default ring resource counts */
2263 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2264 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2265
2266 adapter->mii.dev = netdev;
2267 adapter->mii.mdio_read = mdio_read;
2268 adapter->mii.mdio_write = mdio_write;
2269 adapter->mii.phy_id_mask = 0x1f;
2270 adapter->mii.reg_num_mask = 0x1f;
2271
2272 netdev->open = &atl1_open;
2273 netdev->stop = &atl1_close;
2274 netdev->hard_start_xmit = &atl1_xmit_frame;
2275 netdev->get_stats = &atl1_get_stats;
2276 netdev->set_multicast_list = &atl1_set_multi;
2277 netdev->set_mac_address = &atl1_set_mac;
2278 netdev->change_mtu = &atl1_change_mtu;
2279 netdev->do_ioctl = &atl1_ioctl;
2280 netdev->tx_timeout = &atl1_tx_timeout;
2281 netdev->watchdog_timeo = 5 * HZ;
2282#ifdef CONFIG_NET_POLL_CONTROLLER
2283 netdev->poll_controller = atl1_poll_controller;
2284#endif
2285 netdev->vlan_rx_register = atl1_vlan_rx_register;
2286
2287 netdev->ethtool_ops = &atl1_ethtool_ops;
2288 adapter->bd_number = cards_found;
2289
2290 /* setup the private structure */
2291 err = atl1_sw_init(adapter);
2292 if (err)
2293 goto err_common;
2294
2295 netdev->features = NETIF_F_HW_CSUM;
2296 netdev->features |= NETIF_F_SG;
2297 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2298
2299 /*
2300 * FIXME - Until tso performance gets fixed, disable the feature.
2301 * Enable it with ethtool -K if desired.
2302 */
2303 /* netdev->features |= NETIF_F_TSO; */
2304
2305 netdev->features |= NETIF_F_LLTX;
2306
2307 /*
2308 * patch for some L1 of old version,
2309 * the final version of L1 may not need these
2310 * patches
2311 */
2312 /* atl1_pcie_patch(adapter); */
2313
2314 /* really reset GPHY core */
2315 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2316
2317 /*
2318 * reset the controller to
2319 * put the device in a known good starting state
2320 */
2321 if (atl1_reset_hw(&adapter->hw)) {
2322 err = -EIO;
2323 goto err_common;
2324 }
2325
2326 /* copy the MAC address out of the EEPROM */
2327 atl1_read_mac_addr(&adapter->hw);
2328 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2329
2330 if (!is_valid_ether_addr(netdev->dev_addr)) {
2331 err = -EIO;
2332 goto err_common;
2333 }
2334
2335 atl1_check_options(adapter);
2336
2337 /* pre-init the MAC, and setup link */
2338 err = atl1_init_hw(&adapter->hw);
2339 if (err) {
2340 err = -EIO;
2341 goto err_common;
2342 }
2343
2344 atl1_pcie_patch(adapter);
2345 /* assume we have no link for now */
2346 netif_carrier_off(netdev);
2347 netif_stop_queue(netdev);
2348
2349 init_timer(&adapter->watchdog_timer);
2350 adapter->watchdog_timer.function = &atl1_watchdog;
2351 adapter->watchdog_timer.data = (unsigned long)adapter;
2352
2353 init_timer(&adapter->phy_config_timer);
2354 adapter->phy_config_timer.function = &atl1_phy_config;
2355 adapter->phy_config_timer.data = (unsigned long)adapter;
2356 adapter->phy_timer_pending = false;
2357
2358 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
2359
2360 INIT_WORK(&adapter->link_chg_task, atl1_link_chg_task);
2361
2362 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
2363
2364 err = register_netdev(netdev);
2365 if (err)
2366 goto err_common;
2367
2368 cards_found++;
2369 atl1_via_workaround(adapter);
2370 return 0;
2371
2372err_common:
2373 pci_iounmap(pdev, adapter->hw.hw_addr);
2374err_pci_iomap:
2375 free_netdev(netdev);
2376err_alloc_etherdev:
2377 pci_release_regions(pdev);
2378err_dma:
2379err_request_regions:
2380 pci_disable_device(pdev);
2381 return err;
2382}
2383
2384/*
2385 * atl1_remove - Device Removal Routine
2386 * @pdev: PCI device information struct
2387 *
2388 * atl1_remove is called by the PCI subsystem to alert the driver
2389 * that it should release a PCI device. The could be caused by a
2390 * Hot-Plug event, or because the driver is going to be removed from
2391 * memory.
2392 */
2393static void __devexit atl1_remove(struct pci_dev *pdev)
2394{
2395 struct net_device *netdev = pci_get_drvdata(pdev);
2396 struct atl1_adapter *adapter;
2397 /* Device not available. Return. */
2398 if (!netdev)
2399 return;
2400
2401 adapter = netdev_priv(netdev);
2402
2403 /* Some atl1 boards lack persistent storage for their MAC, and get it
2404 * from the BIOS during POST. If we've been messing with the MAC
2405 * address, we need to save the permanent one.
2406 */
2407 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
2408 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
2409 ETH_ALEN);
2410 atl1_set_mac_addr(&adapter->hw);
2411 }
2412
2413 iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
2414 unregister_netdev(netdev);
2415 pci_iounmap(pdev, adapter->hw.hw_addr);
2416 pci_release_regions(pdev);
2417 free_netdev(netdev);
2418 pci_disable_device(pdev);
2419}
2420
2421static struct pci_driver atl1_driver = {
2422 .name = atl1_driver_name,
2423 .id_table = atl1_pci_tbl,
2424 .probe = atl1_probe,
2425 .remove = __devexit_p(atl1_remove),
2426 .suspend = atl1_suspend,
2427 .resume = atl1_resume
2428};
2429
2430/*
2431 * atl1_exit_module - Driver Exit Cleanup Routine
2432 *
2433 * atl1_exit_module is called just before the driver is removed
2434 * from memory.
2435 */
2436static void __exit atl1_exit_module(void)
2437{
2438 pci_unregister_driver(&atl1_driver);
2439}
2440
2441/*
2442 * atl1_init_module - Driver Registration Routine
2443 *
2444 * atl1_init_module is the first routine called when the driver is
2445 * loaded. All it does is register with the PCI subsystem.
2446 */
2447static int __init atl1_init_module(void)
2448{
2449 return pci_register_driver(&atl1_driver);
2450}
2451
2452module_init(atl1_init_module);
2453module_exit(atl1_exit_module);
diff --git a/drivers/net/atl1/atl1_param.c b/drivers/net/atl1/atl1_param.c
deleted file mode 100644
index 4246bb9bd50e..000000000000
--- a/drivers/net/atl1/atl1_param.c
+++ /dev/null
@@ -1,203 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include "atl1.h"
28
29/*
30 * This is the only thing that needs to be changed to adjust the
31 * maximum number of ports that the driver can manage.
32 */
33#define ATL1_MAX_NIC 4
34
35#define OPTION_UNSET -1
36#define OPTION_DISABLED 0
37#define OPTION_ENABLED 1
38
39#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
40
41/*
42 * Interrupt Moderate Timer in units of 2 us
43 *
44 * Valid Range: 10-65535
45 *
46 * Default Value: 100 (200us)
47 */
48static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
49static int num_int_mod_timer = 0;
50module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
51MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
52
53/*
54 * flash_vendor
55 *
56 * Valid Range: 0-2
57 *
58 * 0 - Atmel
59 * 1 - SST
60 * 2 - ST
61 *
62 * Default Value: 0
63 */
64static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
65static int num_flash_vendor = 0;
66module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
67MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
68
69#define DEFAULT_INT_MOD_CNT 100 /* 200us */
70#define MAX_INT_MOD_CNT 65000
71#define MIN_INT_MOD_CNT 50
72
73#define FLASH_VENDOR_DEFAULT 0
74#define FLASH_VENDOR_MIN 0
75#define FLASH_VENDOR_MAX 2
76
77struct atl1_option {
78 enum { enable_option, range_option, list_option } type;
79 char *name;
80 char *err;
81 int def;
82 union {
83 struct { /* range_option info */
84 int min;
85 int max;
86 } r;
87 struct { /* list_option info */
88 int nr;
89 struct atl1_opt_list {
90 int i;
91 char *str;
92 } *p;
93 } l;
94 } arg;
95};
96
97static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, struct pci_dev *pdev)
98{
99 if (*value == OPTION_UNSET) {
100 *value = opt->def;
101 return 0;
102 }
103
104 switch (opt->type) {
105 case enable_option:
106 switch (*value) {
107 case OPTION_ENABLED:
108 dev_info(&pdev->dev, "%s enabled\n", opt->name);
109 return 0;
110 case OPTION_DISABLED:
111 dev_info(&pdev->dev, "%s disabled\n", opt->name);
112 return 0;
113 }
114 break;
115 case range_option:
116 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
117 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
118 *value);
119 return 0;
120 }
121 break;
122 case list_option:{
123 int i;
124 struct atl1_opt_list *ent;
125
126 for (i = 0; i < opt->arg.l.nr; i++) {
127 ent = &opt->arg.l.p[i];
128 if (*value == ent->i) {
129 if (ent->str[0] != '\0')
130 dev_info(&pdev->dev, "%s\n",
131 ent->str);
132 return 0;
133 }
134 }
135 }
136 break;
137
138 default:
139 break;
140 }
141
142 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
143 opt->name, *value, opt->err);
144 *value = opt->def;
145 return -1;
146}
147
148/*
149 * atl1_check_options - Range Checking for Command Line Parameters
150 * @adapter: board private structure
151 *
152 * This routine checks all command line parameters for valid user
153 * input. If an invalid value is given, or if no user specified
154 * value exists, a default value is used. The final value is stored
155 * in a variable in the adapter structure.
156 */
157void __devinit atl1_check_options(struct atl1_adapter *adapter)
158{
159 struct pci_dev *pdev = adapter->pdev;
160 int bd = adapter->bd_number;
161 if (bd >= ATL1_MAX_NIC) {
162 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
163 dev_notice(&pdev->dev, "using defaults for all values\n");
164 }
165 { /* Interrupt Moderate Timer */
166 struct atl1_option opt = {
167 .type = range_option,
168 .name = "Interrupt Moderator Timer",
169 .err = "using default of "
170 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
171 .def = DEFAULT_INT_MOD_CNT,
172 .arg = {.r =
173 {.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
174 };
175 int val;
176 if (num_int_mod_timer > bd) {
177 val = int_mod_timer[bd];
178 atl1_validate_option(&val, &opt, pdev);
179 adapter->imt = (u16) val;
180 } else
181 adapter->imt = (u16) (opt.def);
182 }
183
184 { /* Flash Vendor */
185 struct atl1_option opt = {
186 .type = range_option,
187 .name = "SPI Flash Vendor",
188 .err = "using default of "
189 __MODULE_STRING(FLASH_VENDOR_DEFAULT),
190 .def = DEFAULT_INT_MOD_CNT,
191 .arg = {.r =
192 {.min = FLASH_VENDOR_MIN,.max =
193 FLASH_VENDOR_MAX}}
194 };
195 int val;
196 if (num_flash_vendor > bd) {
197 val = flash_vendor[bd];
198 atl1_validate_option(&val, &opt, pdev);
199 adapter->hw.flash_vendor = (u8) val;
200 } else
201 adapter->hw.flash_vendor = (u8) (opt.def);
202 }
203}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 03:02:12 -0500