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authorJay Cliburn <jacliburn@bellsouth.net>2007-02-08 10:42:37 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-08 10:42:37 -0500
commitf3cc28c797604fa1cda4aef3f250f465de54a0ca (patch)
tree457722c6be1715307563a12b266bdf7910e8bb7f /drivers/net/atl1/atl1_hw.c
parentc4184f117af7441fb83bc413d2214d92920e0289 (diff)
Add Attansic L1 ethernet driver.
This driver is a modified version of the Attansic reference driver for the L1 ethernet adapter. Attansic has granted permission for its inclusion in the mainline kernel. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/atl1/atl1_hw.c')
-rw-r--r--drivers/net/atl1/atl1_hw.c718
1 files changed, 718 insertions, 0 deletions
diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atl1/atl1_hw.c
new file mode 100644
index 000000000000..08b2d785469d
--- /dev/null
+++ b/drivers/net/atl1/atl1_hw.c
@@ -0,0 +1,718 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 u32 icr;
42 int i;
43
44 /*
45 * Clear Interrupt mask to stop board from generating
46 * interrupts & Clear any pending interrupt events
47 */
48 /*
49 * iowrite32(0, hw->hw_addr + REG_IMR);
50 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
51 */
52
53 /*
54 * Issue Soft Reset to the MAC. This will reset the chip's
55 * transmit, receive, DMA. It will not effect
56 * the current PCI configuration. The global reset bit is self-
57 * clearing, and should clear within a microsecond.
58 */
59 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
60 ioread32(hw->hw_addr + REG_MASTER_CTRL);
61
62 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
63 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
64
65 msleep(1); /* delay about 1ms */
66
67 /* Wait at least 10ms for All module to be Idle */
68 for (i = 0; i < 10; i++) {
69 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
70 if (!icr)
71 break;
72 msleep(1); /* delay 1 ms */
73 cpu_relax(); /* FIXME: is this still the right way to do this? */
74 }
75
76 if (icr) {
77 printk (KERN_DEBUG "icr = %x\n", icr);
78 return icr;
79 }
80
81 return ATL1_SUCCESS;
82}
83
84/* function about EEPROM
85 *
86 * check_eeprom_exist
87 * return 0 if eeprom exist
88 */
89static int atl1_check_eeprom_exist(struct atl1_hw *hw)
90{
91 u32 value;
92 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
93 if (value & SPI_FLASH_CTRL_EN_VPD) {
94 value &= ~SPI_FLASH_CTRL_EN_VPD;
95 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
96 }
97
98 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
99 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
100}
101
102static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
103{
104 int i;
105 u32 control;
106
107 if (offset & 3)
108 return false; /* address do not align */
109
110 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
111 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
112 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
113 ioread32(hw->hw_addr + REG_VPD_CAP);
114
115 for (i = 0; i < 10; i++) {
116 msleep(2);
117 control = ioread32(hw->hw_addr + REG_VPD_CAP);
118 if (control & VPD_CAP_VPD_FLAG)
119 break;
120 }
121 if (control & VPD_CAP_VPD_FLAG) {
122 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
123 return true;
124 }
125 return false; /* timeout */
126}
127
128/*
129 * Reads the value from a PHY register
130 * hw - Struct containing variables accessed by shared code
131 * reg_addr - address of the PHY register to read
132 */
133s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
134{
135 u32 val;
136 int i;
137
138 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
139 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
140 MDIO_CLK_SEL_SHIFT;
141 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
142 ioread32(hw->hw_addr + REG_MDIO_CTRL);
143
144 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
145 udelay(2);
146 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
147 if (!(val & (MDIO_START | MDIO_BUSY)))
148 break;
149 }
150 if (!(val & (MDIO_START | MDIO_BUSY))) {
151 *phy_data = (u16) val;
152 return ATL1_SUCCESS;
153 }
154 return ATL1_ERR_PHY;
155}
156
157#define CUSTOM_SPI_CS_SETUP 2
158#define CUSTOM_SPI_CLK_HI 2
159#define CUSTOM_SPI_CLK_LO 2
160#define CUSTOM_SPI_CS_HOLD 2
161#define CUSTOM_SPI_CS_HI 3
162
163static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
164{
165 int i;
166 u32 value;
167
168 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
169 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
170
171 value = SPI_FLASH_CTRL_WAIT_READY |
172 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
173 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
174 SPI_FLASH_CTRL_CLK_HI_MASK) <<
175 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
176 SPI_FLASH_CTRL_CLK_LO_MASK) <<
177 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
178 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
179 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
180 SPI_FLASH_CTRL_CS_HI_MASK) <<
181 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
182 SPI_FLASH_CTRL_INS_SHIFT;
183
184 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
185
186 value |= SPI_FLASH_CTRL_START;
187 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
188 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
189
190 for (i = 0; i < 10; i++) {
191 msleep(1); /* 1ms */
192 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
193 if (!(value & SPI_FLASH_CTRL_START))
194 break;
195 }
196
197 if (value & SPI_FLASH_CTRL_START)
198 return false;
199
200 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
201
202 return true;
203}
204
205/*
206 * get_permanent_address
207 * return 0 if get valid mac address,
208 */
209static int atl1_get_permanent_address(struct atl1_hw *hw)
210{
211 u32 addr[2];
212 u32 i, control;
213 u16 reg;
214 u8 eth_addr[ETH_ALEN];
215 bool key_valid;
216
217 if (is_valid_ether_addr(hw->perm_mac_addr))
218 return 0;
219
220 /* init */
221 addr[0] = addr[1] = 0;
222
223 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
224 reg = 0;
225 key_valid = false;
226 /* Read out all EEPROM content */
227 i = 0;
228 while (1) {
229 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
230 if (key_valid) {
231 if (reg == REG_MAC_STA_ADDR)
232 addr[0] = control;
233 else if (reg == (REG_MAC_STA_ADDR + 4))
234 addr[1] = control;
235 key_valid = false;
236 } else if ((control & 0xff) == 0x5A) {
237 key_valid = true;
238 reg = (u16) (control >> 16);
239 } else
240 break; /* assume data end while encount an invalid KEYWORD */
241 } else
242 break; /* read error */
243 i += 4;
244 }
245
246/*
247 * The following 2 lines are the Attansic originals. Saving for posterity.
248 * *(u32 *) & eth_addr[2] = LONGSWAP(addr[0]);
249 * *(u16 *) & eth_addr[0] = SHORTSWAP(*(u16 *) & addr[1]);
250 */
251 *(u32 *) & eth_addr[2] = swab32(addr[0]);
252 *(u16 *) & eth_addr[0] = swab16(*(u16 *) & addr[1]);
253
254 if (is_valid_ether_addr(eth_addr)) {
255 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
256 return 0;
257 }
258 return 1;
259 }
260
261 /* see if SPI FLAGS exist ? */
262 addr[0] = addr[1] = 0;
263 reg = 0;
264 key_valid = false;
265 i = 0;
266 while (1) {
267 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
268 if (key_valid) {
269 if (reg == REG_MAC_STA_ADDR)
270 addr[0] = control;
271 else if (reg == (REG_MAC_STA_ADDR + 4))
272 addr[1] = control;
273 key_valid = false;
274 } else if ((control & 0xff) == 0x5A) {
275 key_valid = true;
276 reg = (u16) (control >> 16);
277 } else
278 break; /* data end */
279 } else
280 break; /* read error */
281 i += 4;
282 }
283
284/*
285 * The following 2 lines are the Attansic originals. Saving for posterity.
286 * *(u32 *) & eth_addr[2] = LONGSWAP(addr[0]);
287 * *(u16 *) & eth_addr[0] = SHORTSWAP(*(u16 *) & addr[1]);
288 */
289 *(u32 *) & eth_addr[2] = swab32(addr[0]);
290 *(u16 *) & eth_addr[0] = swab16(*(u16 *) & addr[1]);
291 if (is_valid_ether_addr(eth_addr)) {
292 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
293 return 0;
294 }
295 return 1;
296}
297
298/*
299 * Reads the adapter's MAC address from the EEPROM
300 * hw - Struct containing variables accessed by shared code
301 */
302s32 atl1_read_mac_addr(struct atl1_hw *hw)
303{
304 u16 i;
305
306 if (atl1_get_permanent_address(hw))
307 random_ether_addr(hw->perm_mac_addr);
308
309 for (i = 0; i < ETH_ALEN; i++)
310 hw->mac_addr[i] = hw->perm_mac_addr[i];
311 return ATL1_SUCCESS;
312}
313
314/*
315 * Hashes an address to determine its location in the multicast table
316 * hw - Struct containing variables accessed by shared code
317 * mc_addr - the multicast address to hash
318 *
319 * atl1_hash_mc_addr
320 * purpose
321 * set hash value for a multicast address
322 * hash calcu processing :
323 * 1. calcu 32bit CRC for multicast address
324 * 2. reverse crc with MSB to LSB
325 */
326u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
327{
328 u32 crc32, value = 0;
329 int i;
330
331 crc32 = ether_crc_le(6, mc_addr);
332 crc32 = ~crc32;
333 for (i = 0; i < 32; i++)
334 value |= (((crc32 >> i) & 1) << (31 - i));
335
336 return value;
337}
338
339/*
340 * Sets the bit in the multicast table corresponding to the hash value.
341 * hw - Struct containing variables accessed by shared code
342 * hash_value - Multicast address hash value
343 */
344void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
345{
346 u32 hash_bit, hash_reg;
347 u32 mta;
348
349 /*
350 * The HASH Table is a register array of 2 32-bit registers.
351 * It is treated like an array of 64 bits. We want to set
352 * bit BitArray[hash_value]. So we figure out what register
353 * the bit is in, read it, OR in the new bit, then write
354 * back the new value. The register is determined by the
355 * upper 7 bits of the hash value and the bit within that
356 * register are determined by the lower 5 bits of the value.
357 */
358 hash_reg = (hash_value >> 31) & 0x1;
359 hash_bit = (hash_value >> 26) & 0x1F;
360 mta = ioread32((hw + REG_RX_HASH_TABLE) + (hash_reg << 2));
361 mta |= (1 << hash_bit);
362 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
363}
364
365/*
366 * Writes a value to a PHY register
367 * hw - Struct containing variables accessed by shared code
368 * reg_addr - address of the PHY register to write
369 * data - data to write to the PHY
370 */
371s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
372{
373 int i;
374 u32 val;
375
376 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
377 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
378 MDIO_SUP_PREAMBLE |
379 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
380 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
381 ioread32(hw->hw_addr + REG_MDIO_CTRL);
382
383 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
384 udelay(2);
385 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
386 if (!(val & (MDIO_START | MDIO_BUSY)))
387 break;
388 }
389
390 if (!(val & (MDIO_START | MDIO_BUSY)))
391 return ATL1_SUCCESS;
392
393 return ATL1_ERR_PHY;
394}
395
396/*
397 * Make L001's PHY out of Power Saving State (bug)
398 * hw - Struct containing variables accessed by shared code
399 * when power on, L001's PHY always on Power saving State
400 * (Gigabit Link forbidden)
401 */
402static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
403{
404 s32 ret;
405 ret = atl1_write_phy_reg(hw, 29, 0x0029);
406 if (ret)
407 return ret;
408 return atl1_write_phy_reg(hw, 30, 0);
409}
410
411/*
412 *TODO: do something or get rid of this
413 */
414s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
415{
416/* s32 ret_val;
417 * u16 phy_data;
418 */
419
420/*
421 ret_val = atl1_write_phy_reg(hw, ...);
422 ret_val = atl1_write_phy_reg(hw, ...);
423 ....
424*/
425 return ATL1_SUCCESS;
426}
427
428/*
429 * Resets the PHY and make all config validate
430 * hw - Struct containing variables accessed by shared code
431 *
432 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
433 */
434static s32 atl1_phy_reset(struct atl1_hw *hw)
435{
436 s32 ret_val;
437 u16 phy_data;
438
439 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
440 hw->media_type == MEDIA_TYPE_1000M_FULL)
441 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
442 else {
443 switch (hw->media_type) {
444 case MEDIA_TYPE_100M_FULL:
445 phy_data =
446 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
447 MII_CR_RESET;
448 break;
449 case MEDIA_TYPE_100M_HALF:
450 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
451 break;
452 case MEDIA_TYPE_10M_FULL:
453 phy_data =
454 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
455 break;
456 default: /* MEDIA_TYPE_10M_HALF: */
457 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
458 break;
459 }
460 }
461
462 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
463 if (ret_val) {
464 u32 val;
465 int i;
466 /* pcie serdes link may be down! */
467 printk(KERN_DEBUG "%s: autoneg caused pcie phy link down\n",
468 atl1_driver_name);
469
470 for (i = 0; i < 25; i++) {
471 msleep(1);
472 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
473 if (!(val & (MDIO_START | MDIO_BUSY)))
474 break;
475 }
476
477 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
478 printk(KERN_WARNING
479 "%s: pcie link down at least for 25ms\n",
480 atl1_driver_name);
481 return ret_val;
482 }
483 }
484 return ATL1_SUCCESS;
485}
486
487/*
488 * Configures PHY autoneg and flow control advertisement settings
489 * hw - Struct containing variables accessed by shared code
490 */
491s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
492{
493 s32 ret_val;
494 s16 mii_autoneg_adv_reg;
495 s16 mii_1000t_ctrl_reg;
496
497 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
498 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
499
500 /* Read the MII 1000Base-T Control Register (Address 9). */
501 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
502
503 /*
504 * First we clear all the 10/100 mb speed bits in the Auto-Neg
505 * Advertisement Register (Address 4) and the 1000 mb speed bits in
506 * the 1000Base-T Control Register (Address 9).
507 */
508 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
509 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
510
511 /*
512 * Need to parse media_type and set up
513 * the appropriate PHY registers.
514 */
515 switch (hw->media_type) {
516 case MEDIA_TYPE_AUTO_SENSOR:
517 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
518 MII_AR_10T_FD_CAPS |
519 MII_AR_100TX_HD_CAPS |
520 MII_AR_100TX_FD_CAPS);
521 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
522 break;
523
524 case MEDIA_TYPE_1000M_FULL:
525 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
526 break;
527
528 case MEDIA_TYPE_100M_FULL:
529 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
530 break;
531
532 case MEDIA_TYPE_100M_HALF:
533 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
534 break;
535
536 case MEDIA_TYPE_10M_FULL:
537 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
538 break;
539
540 default:
541 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
542 break;
543 }
544
545 /* flow control fixed to enable all */
546 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
547
548 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
549 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
550
551 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
552 if (ret_val)
553 return ret_val;
554
555 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
556 if (ret_val)
557 return ret_val;
558
559 return ATL1_SUCCESS;
560}
561
562/*
563 * Configures link settings.
564 * hw - Struct containing variables accessed by shared code
565 * Assumes the hardware has previously been reset and the
566 * transmitter and receiver are not enabled.
567 */
568static s32 atl1_setup_link(struct atl1_hw *hw)
569{
570 s32 ret_val;
571
572 /*
573 * Options:
574 * PHY will advertise value(s) parsed from
575 * autoneg_advertised and fc
576 * no matter what autoneg is , We will not wait link result.
577 */
578 ret_val = atl1_phy_setup_autoneg_adv(hw);
579 if (ret_val) {
580 printk(KERN_DEBUG "%s: error setting up autonegotiation\n",
581 atl1_driver_name);
582 return ret_val;
583 }
584 /* SW.Reset , En-Auto-Neg if needed */
585 ret_val = atl1_phy_reset(hw);
586 if (ret_val) {
587 printk(KERN_DEBUG "%s: error resetting the phy\n",
588 atl1_driver_name);
589 return ret_val;
590 }
591 hw->phy_configured = true;
592 return ret_val;
593}
594
595static struct atl1_spi_flash_dev flash_table[] = {
596/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
597 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
598 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
599 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
600};
601
602static void atl1_init_flash_opcode(struct atl1_hw *hw)
603{
604 if (hw->flash_vendor >= sizeof(flash_table) / sizeof(flash_table[0]))
605 hw->flash_vendor = 0; /* ATMEL */
606
607 /* Init OP table */
608 iowrite8(flash_table[hw->flash_vendor].cmd_program,
609 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
610 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
611 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
612 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
615 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
616 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
617 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
618 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
619 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
620 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_read,
623 hw->hw_addr + REG_SPI_FLASH_OP_READ);
624}
625
626/*
627 * Performs basic configuration of the adapter.
628 * hw - Struct containing variables accessed by shared code
629 * Assumes that the controller has previously been reset and is in a
630 * post-reset uninitialized state. Initializes multicast table,
631 * and Calls routines to setup link
632 * Leaves the transmit and receive units disabled and uninitialized.
633 */
634s32 atl1_init_hw(struct atl1_hw *hw)
635{
636 u32 ret_val = 0;
637
638 /* Zero out the Multicast HASH table */
639 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
640 /* clear the old settings from the multicast hash table */
641 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
642
643 atl1_init_flash_opcode(hw);
644
645 if (!hw->phy_configured) {
646 /* enable GPHY LinkChange Interrrupt */
647 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
648 if (ret_val)
649 return ret_val;
650 /* make PHY out of power-saving state */
651 ret_val = atl1_phy_leave_power_saving(hw);
652 if (ret_val)
653 return ret_val;
654 /* Call a subroutine to configure the link */
655 ret_val = atl1_setup_link(hw);
656 }
657 return ret_val;
658}
659
660/*
661 * Detects the current speed and duplex settings of the hardware.
662 * hw - Struct containing variables accessed by shared code
663 * speed - Speed of the connection
664 * duplex - Duplex setting of the connection
665 */
666s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
667{
668 s32 ret_val;
669 u16 phy_data;
670
671 /* ; --- Read PHY Specific Status Register (17) */
672 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
673 if (ret_val)
674 return ret_val;
675
676 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
677 return ATL1_ERR_PHY_RES;
678
679 switch (phy_data & MII_AT001_PSSR_SPEED) {
680 case MII_AT001_PSSR_1000MBS:
681 *speed = SPEED_1000;
682 break;
683 case MII_AT001_PSSR_100MBS:
684 *speed = SPEED_100;
685 break;
686 case MII_AT001_PSSR_10MBS:
687 *speed = SPEED_10;
688 break;
689 default:
690 printk(KERN_DEBUG "%s: error getting speed\n",
691 atl1_driver_name);
692 return ATL1_ERR_PHY_SPEED;
693 break;
694 }
695 if (phy_data & MII_AT001_PSSR_DPLX)
696 *duplex = FULL_DUPLEX;
697 else
698 *duplex = HALF_DUPLEX;
699
700 return ATL1_SUCCESS;
701}
702
703void atl1_set_mac_addr(struct atl1_hw *hw)
704{
705 u32 value;
706 /*
707 * 00-0B-6A-F6-00-DC
708 * 0: 6AF600DC 1: 000B
709 * low dword
710 */
711 value = (((u32) hw->mac_addr[2]) << 24) |
712 (((u32) hw->mac_addr[3]) << 16) |
713 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
714 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
715 /* high dword */
716 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
717 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
718}