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authorJeff Garzik <jeff@garzik.org>2006-09-13 13:24:59 -0400
committerJeff Garzik <jeff@garzik.org>2006-09-13 13:24:59 -0400
commit6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch)
treedf0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/amd8111e.h
parent7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff)
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/amd8111e.h')
-rw-r--r--drivers/net/amd8111e.h102
1 files changed, 51 insertions, 51 deletions
diff --git a/drivers/net/amd8111e.h b/drivers/net/amd8111e.h
index cfe3a4298822..7727d328f65e 100644
--- a/drivers/net/amd8111e.h
+++ b/drivers/net/amd8111e.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Advanced Micro Devices Inc. AMD8111E Linux Network Driver 2 * Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2003 Advanced Micro Devices 3 * Copyright (C) 2003 Advanced Micro Devices
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -14,7 +14,7 @@
14 * 14 *
15 * You should have received a copy of the GNU General Public License 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
18 * USA 18 * USA
19 19
20Module Name: 20Module Name:
@@ -22,11 +22,11 @@ Module Name:
22 amd8111e.h 22 amd8111e.h
23 23
24Abstract: 24Abstract:
25 25
26 AMD8111 based 10/100 Ethernet Controller driver definitions. 26 AMD8111 based 10/100 Ethernet Controller driver definitions.
27 27
28Environment: 28Environment:
29 29
30 Kernel Mode 30 Kernel Mode
31 31
32Revision History: 32Revision History:
@@ -40,7 +40,7 @@ Revision History:
40 40
41/* Command style register access 41/* Command style register access
42 42
43Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register. 43Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
44 44
45eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered. 45eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
46 46
@@ -122,8 +122,8 @@ typedef enum {
122 ASF_INIT_DONE = (1 << 1), 122 ASF_INIT_DONE = (1 << 1),
123 ASF_INIT_PRESENT = (1 << 0), 123 ASF_INIT_PRESENT = (1 << 0),
124 124
125}STAT_ASF_BITS; 125}STAT_ASF_BITS;
126 126
127typedef enum { 127typedef enum {
128 128
129 MIB_CMD_ACTIVE = (1 << 15 ), 129 MIB_CMD_ACTIVE = (1 << 15 ),
@@ -135,7 +135,7 @@ typedef enum {
135 135
136 136
137typedef enum { 137typedef enum {
138 138
139 PMAT_DET = (1 << 12), 139 PMAT_DET = (1 << 12),
140 MP_DET = (1 << 11), 140 MP_DET = (1 << 11),
141 LC_DET = (1 << 10), 141 LC_DET = (1 << 10),
@@ -157,7 +157,7 @@ typedef enum {
157typedef enum { 157typedef enum {
158 158
159 INTR = (1 << 31), 159 INTR = (1 << 31),
160 PCSINT = (1 << 28), 160 PCSINT = (1 << 28),
161 LCINT = (1 << 27), 161 LCINT = (1 << 27),
162 APINT5 = (1 << 26), 162 APINT5 = (1 << 26),
163 APINT4 = (1 << 25), 163 APINT4 = (1 << 25),
@@ -221,7 +221,7 @@ typedef enum {
221 221
222 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */ 222 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
223 223
224}INTEN0_BITS; 224}INTEN0_BITS;
225 225
226typedef enum { 226typedef enum {
227 /* VAL2 */ 227 /* VAL2 */
@@ -240,7 +240,7 @@ typedef enum {
240 INTREN = (1 << 1), 240 INTREN = (1 << 1),
241 RUN = (1 << 0), 241 RUN = (1 << 0),
242 242
243 CMD0_CLEAR = 0x000F0F7F, /* Command style register */ 243 CMD0_CLEAR = 0x000F0F7F, /* Command style register */
244 244
245}CMD0_BITS; 245}CMD0_BITS;
246 246
@@ -279,20 +279,20 @@ typedef enum {
279 ASF_INIT_DONE_ALIAS = (1 << 29), 279 ASF_INIT_DONE_ALIAS = (1 << 29),
280 /* VAL2 */ 280 /* VAL2 */
281 JUMBO = (1 << 21), 281 JUMBO = (1 << 21),
282 VSIZE = (1 << 20), 282 VSIZE = (1 << 20),
283 VLONLY = (1 << 19), 283 VLONLY = (1 << 19),
284 VL_TAG_DEL = (1 << 18), 284 VL_TAG_DEL = (1 << 18),
285 /* VAL1 */ 285 /* VAL1 */
286 EN_PMGR = (1 << 14), 286 EN_PMGR = (1 << 14),
287 INTLEVEL = (1 << 13), 287 INTLEVEL = (1 << 13),
288 FORCE_FULL_DUPLEX = (1 << 12), 288 FORCE_FULL_DUPLEX = (1 << 12),
289 FORCE_LINK_STATUS = (1 << 11), 289 FORCE_LINK_STATUS = (1 << 11),
290 APEP = (1 << 10), 290 APEP = (1 << 10),
291 MPPLBA = (1 << 9), 291 MPPLBA = (1 << 9),
292 /* VAL0 */ 292 /* VAL0 */
293 RESET_PHY_PULSE = (1 << 2), 293 RESET_PHY_PULSE = (1 << 2),
294 RESET_PHY = (1 << 1), 294 RESET_PHY = (1 << 1),
295 PHY_RST_POL = (1 << 0), 295 PHY_RST_POL = (1 << 0),
296 296
297}CMD3_BITS; 297}CMD3_BITS;
298 298
@@ -314,7 +314,7 @@ typedef enum {
314 314
315 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */ 315 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
316 XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */ 316 XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */
317 XMTSP_128 = (1 << 9), /* 9 */ 317 XMTSP_128 = (1 << 9), /* 9 */
318 XMTSP_64 = (1 << 8), 318 XMTSP_64 = (1 << 8),
319 CACHE_ALIGN = (1 << 4), 319 CACHE_ALIGN = (1 << 4),
320 BURST_LIMIT_MASK = (0xF << 0 ), 320 BURST_LIMIT_MASK = (0xF << 0 ),
@@ -445,7 +445,7 @@ typedef enum {
445 DLY_INT_B_T1 = (1 << 25), 445 DLY_INT_B_T1 = (1 << 25),
446 DLY_INT_B_T0 = ( 1 << 24), 446 DLY_INT_B_T0 = ( 1 << 24),
447 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */ 447 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
448 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)| 448 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
449 (1 << 9) | (1 << 10), /* 10:0 */ 449 (1 << 9) | (1 << 10), /* 10:0 */
450}DLY_INT_B_BITS; 450}DLY_INT_B_BITS;
451 451
@@ -569,20 +569,20 @@ typedef enum {
569#define MAX_UNITS 8 /* Maximum number of devices possible */ 569#define MAX_UNITS 8 /* Maximum number of devices possible */
570 570
571#define NUM_TX_BUFFERS 32 /* Number of transmit buffers */ 571#define NUM_TX_BUFFERS 32 /* Number of transmit buffers */
572#define NUM_RX_BUFFERS 32 /* Number of receive buffers */ 572#define NUM_RX_BUFFERS 32 /* Number of receive buffers */
573 573
574#define TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */ 574#define TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */
575#define RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */ 575#define RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */
576 576
577#define NUM_TX_RING_DR 32 577#define NUM_TX_RING_DR 32
578#define NUM_RX_RING_DR 32 578#define NUM_RX_RING_DR 32
579 579
580#define TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */ 580#define TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */
581#define RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */ 581#define RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */
582 582
583#define MAX_FILTER_SIZE 64 /* Maximum multicast address */ 583#define MAX_FILTER_SIZE 64 /* Maximum multicast address */
584#define AMD8111E_MIN_MTU 60 584#define AMD8111E_MIN_MTU 60
585#define AMD8111E_MAX_MTU 9000 585#define AMD8111E_MAX_MTU 9000
586 586
587#define PKT_BUFF_SZ 1536 587#define PKT_BUFF_SZ 1536
588#define MIN_PKT_LEN 60 588#define MIN_PKT_LEN 60
@@ -591,7 +591,7 @@ typedef enum {
591#define AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */ 591#define AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */
592#define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */ 592#define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */
593#define DELAY_TIMER_CONV 50 /* msec to 10 usec conversion. 593#define DELAY_TIMER_CONV 50 /* msec to 10 usec conversion.
594 Only 500 usec resolution */ 594 Only 500 usec resolution */
595#define OPTION_VLAN_ENABLE 0x0001 595#define OPTION_VLAN_ENABLE 0x0001
596#define OPTION_JUMBO_ENABLE 0x0002 596#define OPTION_JUMBO_ENABLE 0x0002
597#define OPTION_MULTICAST_ENABLE 0x0004 597#define OPTION_MULTICAST_ENABLE 0x0004
@@ -611,12 +611,12 @@ typedef enum {
611#define MIN_IPG 96 611#define MIN_IPG 96
612#define MAX_IPG 255 612#define MAX_IPG 255
613#define IPG_STEP 16 613#define IPG_STEP 16
614#define CSTATE 1 614#define CSTATE 1
615#define SSTATE 2 615#define SSTATE 2
616 616
617/* Assume contoller gets data 10 times the maximum processing time */ 617/* Assume contoller gets data 10 times the maximum processing time */
618#define REPEAT_CNT 10; 618#define REPEAT_CNT 10;
619 619
620/* amd8111e decriptor flag definitions */ 620/* amd8111e decriptor flag definitions */
621typedef enum { 621typedef enum {
622 622
@@ -649,7 +649,7 @@ typedef enum {
649#define TCC_MASK 0x0003 649#define TCC_MASK 0x0003
650 650
651/* driver ioctl parameters */ 651/* driver ioctl parameters */
652#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32) 652#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
653 653
654/* crc generator constants */ 654/* crc generator constants */
655#define CRC32 0xedb88320 655#define CRC32 0xedb88320
@@ -670,15 +670,15 @@ struct amd8111e_tx_dr{
670 u32 buff_phy_addr; 670 u32 buff_phy_addr;
671 671
672 u32 reserved; 672 u32 reserved;
673}; 673};
674 674
675struct amd8111e_rx_dr{ 675struct amd8111e_rx_dr{
676 676
677 u32 reserved; 677 u32 reserved;
678 678
679 u16 msg_count; /* Received message len */ 679 u16 msg_count; /* Received message len */
680 680
681 u16 tag_ctrl_info; 681 u16 tag_ctrl_info;
682 682
683 u16 buff_count; /* Len of the buffer pointed by descriptor. */ 683 u16 buff_count; /* Len of the buffer pointed by descriptor. */
684 684
@@ -692,7 +692,7 @@ struct amd8111e_link_config{
692#define SPEED_INVALID 0xffff 692#define SPEED_INVALID 0xffff
693#define DUPLEX_INVALID 0xff 693#define DUPLEX_INVALID 0xff
694#define AUTONEG_INVALID 0xff 694#define AUTONEG_INVALID 0xff
695 695
696 unsigned long orig_phy_option; 696 unsigned long orig_phy_option;
697 u16 speed; 697 u16 speed;
698 u8 duplex; 698 u8 duplex;
@@ -709,7 +709,7 @@ enum coal_type{
709 709
710}; 710};
711 711
712enum coal_mode{ 712enum coal_mode{
713 RX_INTR_COAL, 713 RX_INTR_COAL,
714 TX_INTR_COAL, 714 TX_INTR_COAL,
715 DISABLE_COAL, 715 DISABLE_COAL,
@@ -727,7 +727,7 @@ struct amd8111e_coalesce_conf{
727 unsigned long rx_bytes; 727 unsigned long rx_bytes;
728 unsigned long rx_prev_bytes; 728 unsigned long rx_prev_bytes;
729 unsigned int rx_coal_type; 729 unsigned int rx_coal_type;
730 730
731 unsigned int tx_timeout; 731 unsigned int tx_timeout;
732 unsigned int tx_event_count; 732 unsigned int tx_event_count;
733 unsigned long tx_packets; 733 unsigned long tx_packets;
@@ -738,7 +738,7 @@ struct amd8111e_coalesce_conf{
738 738
739}; 739};
740struct ipg_info{ 740struct ipg_info{
741 741
742 unsigned int ipg_state; 742 unsigned int ipg_state;
743 unsigned int ipg; 743 unsigned int ipg;
744 unsigned int current_ipg; 744 unsigned int current_ipg;
@@ -750,7 +750,7 @@ struct ipg_info{
750}; 750};
751 751
752struct amd8111e_priv{ 752struct amd8111e_priv{
753 753
754 struct amd8111e_tx_dr* tx_ring; 754 struct amd8111e_tx_dr* tx_ring;
755 struct amd8111e_rx_dr* rx_ring; 755 struct amd8111e_rx_dr* rx_ring;
756 dma_addr_t tx_ring_dma_addr; /* tx descriptor ring base address */ 756 dma_addr_t tx_ring_dma_addr; /* tx descriptor ring base address */
@@ -766,7 +766,7 @@ struct amd8111e_priv{
766 dma_addr_t rx_dma_addr[NUM_RX_BUFFERS]; 766 dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
767 /* Reg memory mapped address */ 767 /* Reg memory mapped address */
768 void __iomem *mmio; 768 void __iomem *mmio;
769 769
770 spinlock_t lock; /* Guard lock */ 770 spinlock_t lock; /* Guard lock */
771 unsigned long rx_idx, tx_idx; /* The next free ring entry */ 771 unsigned long rx_idx, tx_idx; /* The next free ring entry */
772 unsigned long tx_complete_idx; 772 unsigned long tx_complete_idx;
@@ -778,7 +778,7 @@ struct amd8111e_priv{
778 unsigned long ext_phy_option; 778 unsigned long ext_phy_option;
779 int ext_phy_addr; 779 int ext_phy_addr;
780 u32 ext_phy_id; 780 u32 ext_phy_id;
781 781
782 struct amd8111e_link_config link_config; 782 struct amd8111e_link_config link_config;
783 int pm_cap; 783 int pm_cap;
784 784
@@ -787,22 +787,22 @@ struct amd8111e_priv{
787 struct mii_if_info mii_if; 787 struct mii_if_info mii_if;
788#if AMD8111E_VLAN_TAG_USED 788#if AMD8111E_VLAN_TAG_USED
789 struct vlan_group *vlgrp; 789 struct vlan_group *vlgrp;
790#endif 790#endif
791 char opened; 791 char opened;
792 struct net_device_stats stats; 792 struct net_device_stats stats;
793 unsigned int drv_rx_errors; 793 unsigned int drv_rx_errors;
794 struct dev_mc_list* mc_list; 794 struct dev_mc_list* mc_list;
795 struct amd8111e_coalesce_conf coal_conf; 795 struct amd8111e_coalesce_conf coal_conf;
796 796
797 struct ipg_info ipg_data; 797 struct ipg_info ipg_data;
798 798
799}; 799};
800 800
801/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register. 801/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
802BUG? */ 802BUG? */
803#define amd8111e_writeq(_UlData,_memMap) \ 803#define amd8111e_writeq(_UlData,_memMap) \
804 writel(*(u32*)(&_UlData), _memMap); \ 804 writel(*(u32*)(&_UlData), _memMap); \
805 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4) 805 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
806 806
807/* maps the external speed options to internal value */ 807/* maps the external speed options to internal value */
808typedef enum { 808typedef enum {