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authorDavid S. Miller <davem@davemloft.net>2009-08-12 20:44:53 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-12 20:44:53 -0400
commitaa11d958d1a6572eda08214d7c6a735804fe48a5 (patch)
treed025b05270ad1e010660d17eeadc6ac3c1abbd7d /drivers/net/3c59x.c
parent07f6642ee9418e962e54cbc07471cfe2e559c568 (diff)
parent9799218ae36910af50f002a5db1802d576fffb43 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: arch/microblaze/include/asm/socket.h
Diffstat (limited to 'drivers/net/3c59x.c')
-rw-r--r--drivers/net/3c59x.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index 202048450eed..beb040264dbd 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -235,6 +235,7 @@ enum vortex_chips {
235 CH_3C900B_FL, 235 CH_3C900B_FL,
236 CH_3C905_1, 236 CH_3C905_1,
237 CH_3C905_2, 237 CH_3C905_2,
238 CH_3C905B_TX,
238 CH_3C905B_1, 239 CH_3C905B_1,
239 240
240 CH_3C905B_2, 241 CH_3C905B_2,
@@ -307,6 +308,8 @@ static struct vortex_chip_info {
307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
308 {"3c905 Boomerang 100baseT4", 309 {"3c905 Boomerang 100baseT4",
309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
310 {"3c905B Cyclone 100baseTx", 313 {"3c905B Cyclone 100baseTx",
311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
312 315
@@ -389,6 +392,7 @@ static struct pci_device_id vortex_pci_tbl[] = {
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL }, 392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 }, 393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 }, 394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 }, 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393 397
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 }, 398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
@@ -2721,13 +2725,15 @@ dump_tx_ring(struct net_device *dev)
2721 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); 2725 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2722 issue_and_wait(dev, DownStall); 2726 issue_and_wait(dev, DownStall);
2723 for (i = 0; i < TX_RING_SIZE; i++) { 2727 for (i = 0; i < TX_RING_SIZE; i++) {
2724 pr_err(" %d: @%p length %8.8x status %8.8x\n", i, 2728 unsigned int length;
2725 &vp->tx_ring[i], 2729
2726#if DO_ZEROCOPY 2730#if DO_ZEROCOPY
2727 le32_to_cpu(vp->tx_ring[i].frag[0].length), 2731 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2728#else 2732#else
2729 le32_to_cpu(vp->tx_ring[i].length), 2733 length = le32_to_cpu(vp->tx_ring[i].length);
2730#endif 2734#endif
2735 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2736 i, &vp->tx_ring[i], length,
2731 le32_to_cpu(vp->tx_ring[i].status)); 2737 le32_to_cpu(vp->tx_ring[i].status));
2732 } 2738 }
2733 if (!stalled) 2739 if (!stalled)