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authorBen Hutchings <ben@decadent.org.uk>2010-06-23 09:54:31 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-29 02:19:18 -0400
commita095cfc40ec7ebe63e9532383c5b5c2a27b14075 (patch)
tree283359a3658ad91b122cd0674bf90b6f9dc0e3d2 /drivers/net/3c59x.c
parentd2ef8590343f1f236f5f7f070fb4cd3f5c3ffb69 (diff)
3c59x: Specify window explicitly for access to windowed registers
Currently much of the code assumes that a specific window has been selected, while a few functions save and restore the window. This makes it impossible to introduce fine-grained locking. Make those assumptions explicit by introducing wrapper functions to set the window and read/write a register. Use these everywhere except vortex_interrupt(), vortex_start_xmit() and vortex_rx(). These set the window just once, or not at all in the case of vortex_rx() as it should always be called from vortex_interrupt(). Cache the current window in struct vortex_private to avoid unnecessary hardware writes. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Tested-by: Arne Nordmark <nordmark@mech.kth.se> [against 2.6.32] Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/3c59x.c')
-rw-r--r--drivers/net/3c59x.c288
1 files changed, 140 insertions, 148 deletions
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index d75803e6e527..beddef98ad92 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -435,7 +435,6 @@ MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
435 First the windows. There are eight register windows, with the command 435 First the windows. There are eight register windows, with the command
436 and status registers available in each. 436 and status registers available in each.
437 */ 437 */
438#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
439#define EL3_CMD 0x0e 438#define EL3_CMD 0x0e
440#define EL3_STATUS 0x0e 439#define EL3_STATUS 0x0e
441 440
@@ -647,8 +646,35 @@ struct vortex_private {
647 u16 io_size; /* Size of PCI region (for release_region) */ 646 u16 io_size; /* Size of PCI region (for release_region) */
648 spinlock_t lock; /* Serialise access to device & its vortex_private */ 647 spinlock_t lock; /* Serialise access to device & its vortex_private */
649 struct mii_if_info mii; /* MII lib hooks/info */ 648 struct mii_if_info mii; /* MII lib hooks/info */
649 int window; /* Register window */
650}; 650};
651 651
652static void window_set(struct vortex_private *vp, int window)
653{
654 if (window != vp->window) {
655 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
656 vp->window = window;
657 }
658}
659
660#define DEFINE_WINDOW_IO(size) \
661static u ## size \
662window_read ## size(struct vortex_private *vp, int window, int addr) \
663{ \
664 window_set(vp, window); \
665 return ioread ## size(vp->ioaddr + addr); \
666} \
667static void \
668window_write ## size(struct vortex_private *vp, u ## size value, \
669 int window, int addr) \
670{ \
671 window_set(vp, window); \
672 iowrite ## size(value, vp->ioaddr + addr); \
673}
674DEFINE_WINDOW_IO(8)
675DEFINE_WINDOW_IO(16)
676DEFINE_WINDOW_IO(32)
677
652#ifdef CONFIG_PCI 678#ifdef CONFIG_PCI
653#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL) 679#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
654#else 680#else
@@ -711,7 +737,7 @@ static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
711static int vortex_up(struct net_device *dev); 737static int vortex_up(struct net_device *dev);
712static void vortex_down(struct net_device *dev, int final); 738static void vortex_down(struct net_device *dev, int final);
713static int vortex_open(struct net_device *dev); 739static int vortex_open(struct net_device *dev);
714static void mdio_sync(void __iomem *ioaddr, int bits); 740static void mdio_sync(struct vortex_private *vp, int bits);
715static int mdio_read(struct net_device *dev, int phy_id, int location); 741static int mdio_read(struct net_device *dev, int phy_id, int location);
716static void mdio_write(struct net_device *vp, int phy_id, int location, int value); 742static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
717static void vortex_timer(unsigned long arg); 743static void vortex_timer(unsigned long arg);
@@ -1119,6 +1145,7 @@ static int __devinit vortex_probe1(struct device *gendev,
1119 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0; 1145 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1120 vp->io_size = vci->io_size; 1146 vp->io_size = vci->io_size;
1121 vp->card_idx = card_idx; 1147 vp->card_idx = card_idx;
1148 vp->window = -1;
1122 1149
1123 /* module list only for Compaq device */ 1150 /* module list only for Compaq device */
1124 if (gendev == NULL) { 1151 if (gendev == NULL) {
@@ -1205,7 +1232,6 @@ static int __devinit vortex_probe1(struct device *gendev,
1205 vp->mii.force_media = vp->full_duplex; 1232 vp->mii.force_media = vp->full_duplex;
1206 vp->options = option; 1233 vp->options = option;
1207 /* Read the station address from the EEPROM. */ 1234 /* Read the station address from the EEPROM. */
1208 EL3WINDOW(0);
1209 { 1235 {
1210 int base; 1236 int base;
1211 1237
@@ -1218,14 +1244,15 @@ static int __devinit vortex_probe1(struct device *gendev,
1218 1244
1219 for (i = 0; i < 0x40; i++) { 1245 for (i = 0; i < 0x40; i++) {
1220 int timer; 1246 int timer;
1221 iowrite16(base + i, ioaddr + Wn0EepromCmd); 1247 window_write16(vp, base + i, 0, Wn0EepromCmd);
1222 /* Pause for at least 162 us. for the read to take place. */ 1248 /* Pause for at least 162 us. for the read to take place. */
1223 for (timer = 10; timer >= 0; timer--) { 1249 for (timer = 10; timer >= 0; timer--) {
1224 udelay(162); 1250 udelay(162);
1225 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0) 1251 if ((window_read16(vp, 0, Wn0EepromCmd) &
1252 0x8000) == 0)
1226 break; 1253 break;
1227 } 1254 }
1228 eeprom[i] = ioread16(ioaddr + Wn0EepromData); 1255 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1229 } 1256 }
1230 } 1257 }
1231 for (i = 0; i < 0x18; i++) 1258 for (i = 0; i < 0x18; i++)
@@ -1250,9 +1277,8 @@ static int __devinit vortex_probe1(struct device *gendev,
1250 pr_err("*** EEPROM MAC address is invalid.\n"); 1277 pr_err("*** EEPROM MAC address is invalid.\n");
1251 goto free_ring; /* With every pack */ 1278 goto free_ring; /* With every pack */
1252 } 1279 }
1253 EL3WINDOW(2);
1254 for (i = 0; i < 6; i++) 1280 for (i = 0; i < 6; i++)
1255 iowrite8(dev->dev_addr[i], ioaddr + i); 1281 window_write8(vp, dev->dev_addr[i], 2, i);
1256 1282
1257 if (print_info) 1283 if (print_info)
1258 pr_cont(", IRQ %d\n", dev->irq); 1284 pr_cont(", IRQ %d\n", dev->irq);
@@ -1261,8 +1287,7 @@ static int __devinit vortex_probe1(struct device *gendev,
1261 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n", 1287 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1262 dev->irq); 1288 dev->irq);
1263 1289
1264 EL3WINDOW(4); 1290 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1265 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1266 if (print_info) { 1291 if (print_info) {
1267 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n", 1292 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1268 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14], 1293 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
@@ -1285,17 +1310,15 @@ static int __devinit vortex_probe1(struct device *gendev,
1285 (unsigned long long)pci_resource_start(pdev, 2), 1310 (unsigned long long)pci_resource_start(pdev, 2),
1286 vp->cb_fn_base); 1311 vp->cb_fn_base);
1287 } 1312 }
1288 EL3WINDOW(2);
1289 1313
1290 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010; 1314 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1291 if (vp->drv_flags & INVERT_LED_PWR) 1315 if (vp->drv_flags & INVERT_LED_PWR)
1292 n |= 0x10; 1316 n |= 0x10;
1293 if (vp->drv_flags & INVERT_MII_PWR) 1317 if (vp->drv_flags & INVERT_MII_PWR)
1294 n |= 0x4000; 1318 n |= 0x4000;
1295 iowrite16(n, ioaddr + Wn2_ResetOptions); 1319 window_write16(vp, n, 2, Wn2_ResetOptions);
1296 if (vp->drv_flags & WNO_XCVR_PWR) { 1320 if (vp->drv_flags & WNO_XCVR_PWR) {
1297 EL3WINDOW(0); 1321 window_write16(vp, 0x0800, 0, 0);
1298 iowrite16(0x0800, ioaddr);
1299 } 1322 }
1300 } 1323 }
1301 1324
@@ -1313,14 +1336,13 @@ static int __devinit vortex_probe1(struct device *gendev,
1313 { 1336 {
1314 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; 1337 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1315 unsigned int config; 1338 unsigned int config;
1316 EL3WINDOW(3); 1339 vp->available_media = window_read16(vp, 3, Wn3_Options);
1317 vp->available_media = ioread16(ioaddr + Wn3_Options);
1318 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ 1340 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1319 vp->available_media = 0x40; 1341 vp->available_media = 0x40;
1320 config = ioread32(ioaddr + Wn3_Config); 1342 config = window_read32(vp, 3, Wn3_Config);
1321 if (print_info) { 1343 if (print_info) {
1322 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n", 1344 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1323 config, ioread16(ioaddr + Wn3_Options)); 1345 config, window_read16(vp, 3, Wn3_Options));
1324 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", 1346 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1325 8 << RAM_SIZE(config), 1347 8 << RAM_SIZE(config),
1326 RAM_WIDTH(config) ? "word" : "byte", 1348 RAM_WIDTH(config) ? "word" : "byte",
@@ -1346,7 +1368,6 @@ static int __devinit vortex_probe1(struct device *gendev,
1346 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) || 1368 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1347 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { 1369 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1348 int phy, phy_idx = 0; 1370 int phy, phy_idx = 0;
1349 EL3WINDOW(4);
1350 mii_preamble_required++; 1371 mii_preamble_required++;
1351 if (vp->drv_flags & EXTRA_PREAMBLE) 1372 if (vp->drv_flags & EXTRA_PREAMBLE)
1352 mii_preamble_required++; 1373 mii_preamble_required++;
@@ -1478,18 +1499,17 @@ static void
1478vortex_set_duplex(struct net_device *dev) 1499vortex_set_duplex(struct net_device *dev)
1479{ 1500{
1480 struct vortex_private *vp = netdev_priv(dev); 1501 struct vortex_private *vp = netdev_priv(dev);
1481 void __iomem *ioaddr = vp->ioaddr;
1482 1502
1483 pr_info("%s: setting %s-duplex.\n", 1503 pr_info("%s: setting %s-duplex.\n",
1484 dev->name, (vp->full_duplex) ? "full" : "half"); 1504 dev->name, (vp->full_duplex) ? "full" : "half");
1485 1505
1486 EL3WINDOW(3);
1487 /* Set the full-duplex bit. */ 1506 /* Set the full-duplex bit. */
1488 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | 1507 window_write16(vp,
1489 (vp->large_frames ? 0x40 : 0) | 1508 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1490 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 1509 (vp->large_frames ? 0x40 : 0) |
1491 0x100 : 0), 1510 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1492 ioaddr + Wn3_MAC_Ctrl); 1511 0x100 : 0),
1512 3, Wn3_MAC_Ctrl);
1493} 1513}
1494 1514
1495static void vortex_check_media(struct net_device *dev, unsigned int init) 1515static void vortex_check_media(struct net_device *dev, unsigned int init)
@@ -1529,8 +1549,7 @@ vortex_up(struct net_device *dev)
1529 } 1549 }
1530 1550
1531 /* Before initializing select the active media port. */ 1551 /* Before initializing select the active media port. */
1532 EL3WINDOW(3); 1552 config = window_read32(vp, 3, Wn3_Config);
1533 config = ioread32(ioaddr + Wn3_Config);
1534 1553
1535 if (vp->media_override != 7) { 1554 if (vp->media_override != 7) {
1536 pr_info("%s: Media override to transceiver %d (%s).\n", 1555 pr_info("%s: Media override to transceiver %d (%s).\n",
@@ -1577,10 +1596,9 @@ vortex_up(struct net_device *dev)
1577 config = BFINS(config, dev->if_port, 20, 4); 1596 config = BFINS(config, dev->if_port, 20, 4);
1578 if (vortex_debug > 6) 1597 if (vortex_debug > 6)
1579 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config); 1598 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1580 iowrite32(config, ioaddr + Wn3_Config); 1599 window_write32(vp, config, 3, Wn3_Config);
1581 1600
1582 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { 1601 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1583 EL3WINDOW(4);
1584 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR); 1602 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1585 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA); 1603 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1586 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0); 1604 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
@@ -1601,51 +1619,46 @@ vortex_up(struct net_device *dev)
1601 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD); 1619 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1602 1620
1603 if (vortex_debug > 1) { 1621 if (vortex_debug > 1) {
1604 EL3WINDOW(4);
1605 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n", 1622 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1606 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media)); 1623 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1607 } 1624 }
1608 1625
1609 /* Set the station address and mask in window 2 each time opened. */ 1626 /* Set the station address and mask in window 2 each time opened. */
1610 EL3WINDOW(2);
1611 for (i = 0; i < 6; i++) 1627 for (i = 0; i < 6; i++)
1612 iowrite8(dev->dev_addr[i], ioaddr + i); 1628 window_write8(vp, dev->dev_addr[i], 2, i);
1613 for (; i < 12; i+=2) 1629 for (; i < 12; i+=2)
1614 iowrite16(0, ioaddr + i); 1630 window_write16(vp, 0, 2, i);
1615 1631
1616 if (vp->cb_fn_base) { 1632 if (vp->cb_fn_base) {
1617 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010; 1633 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1618 if (vp->drv_flags & INVERT_LED_PWR) 1634 if (vp->drv_flags & INVERT_LED_PWR)
1619 n |= 0x10; 1635 n |= 0x10;
1620 if (vp->drv_flags & INVERT_MII_PWR) 1636 if (vp->drv_flags & INVERT_MII_PWR)
1621 n |= 0x4000; 1637 n |= 0x4000;
1622 iowrite16(n, ioaddr + Wn2_ResetOptions); 1638 window_write16(vp, n, 2, Wn2_ResetOptions);
1623 } 1639 }
1624 1640
1625 if (dev->if_port == XCVR_10base2) 1641 if (dev->if_port == XCVR_10base2)
1626 /* Start the thinnet transceiver. We should really wait 50ms...*/ 1642 /* Start the thinnet transceiver. We should really wait 50ms...*/
1627 iowrite16(StartCoax, ioaddr + EL3_CMD); 1643 iowrite16(StartCoax, ioaddr + EL3_CMD);
1628 if (dev->if_port != XCVR_NWAY) { 1644 if (dev->if_port != XCVR_NWAY) {
1629 EL3WINDOW(4); 1645 window_write16(vp,
1630 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) | 1646 (window_read16(vp, 4, Wn4_Media) &
1631 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); 1647 ~(Media_10TP|Media_SQE)) |
1648 media_tbl[dev->if_port].media_bits,
1649 4, Wn4_Media);
1632 } 1650 }
1633 1651
1634 /* Switch to the stats window, and clear all stats by reading. */ 1652 /* Switch to the stats window, and clear all stats by reading. */
1635 iowrite16(StatsDisable, ioaddr + EL3_CMD); 1653 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1636 EL3WINDOW(6);
1637 for (i = 0; i < 10; i++) 1654 for (i = 0; i < 10; i++)
1638 ioread8(ioaddr + i); 1655 window_read8(vp, 6, i);
1639 ioread16(ioaddr + 10); 1656 window_read16(vp, 6, 10);
1640 ioread16(ioaddr + 12); 1657 window_read16(vp, 6, 12);
1641 /* New: On the Vortex we must also clear the BadSSD counter. */ 1658 /* New: On the Vortex we must also clear the BadSSD counter. */
1642 EL3WINDOW(4); 1659 window_read8(vp, 4, 12);
1643 ioread8(ioaddr + 12);
1644 /* ..and on the Boomerang we enable the extra statistics bits. */ 1660 /* ..and on the Boomerang we enable the extra statistics bits. */
1645 iowrite16(0x0040, ioaddr + Wn4_NetDiag); 1661 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1646
1647 /* Switch to register set 7 for normal use. */
1648 EL3WINDOW(7);
1649 1662
1650 if (vp->full_bus_master_rx) { /* Boomerang bus master. */ 1663 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1651 vp->cur_rx = vp->dirty_rx = 0; 1664 vp->cur_rx = vp->dirty_rx = 0;
@@ -1763,7 +1776,7 @@ vortex_timer(unsigned long data)
1763 void __iomem *ioaddr = vp->ioaddr; 1776 void __iomem *ioaddr = vp->ioaddr;
1764 int next_tick = 60*HZ; 1777 int next_tick = 60*HZ;
1765 int ok = 0; 1778 int ok = 0;
1766 int media_status, old_window; 1779 int media_status;
1767 1780
1768 if (vortex_debug > 2) { 1781 if (vortex_debug > 2) {
1769 pr_debug("%s: Media selection timer tick happened, %s.\n", 1782 pr_debug("%s: Media selection timer tick happened, %s.\n",
@@ -1772,9 +1785,7 @@ vortex_timer(unsigned long data)
1772 } 1785 }
1773 1786
1774 disable_irq_lockdep(dev->irq); 1787 disable_irq_lockdep(dev->irq);
1775 old_window = ioread16(ioaddr + EL3_CMD) >> 13; 1788 media_status = window_read16(vp, 4, Wn4_Media);
1776 EL3WINDOW(4);
1777 media_status = ioread16(ioaddr + Wn4_Media);
1778 switch (dev->if_port) { 1789 switch (dev->if_port) {
1779 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: 1790 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1780 if (media_status & Media_LnkBeat) { 1791 if (media_status & Media_LnkBeat) {
@@ -1830,13 +1841,14 @@ vortex_timer(unsigned long data)
1830 dev->name, media_tbl[dev->if_port].name); 1841 dev->name, media_tbl[dev->if_port].name);
1831 next_tick = media_tbl[dev->if_port].wait; 1842 next_tick = media_tbl[dev->if_port].wait;
1832 } 1843 }
1833 iowrite16((media_status & ~(Media_10TP|Media_SQE)) | 1844 window_write16(vp,
1834 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); 1845 (media_status & ~(Media_10TP|Media_SQE)) |
1846 media_tbl[dev->if_port].media_bits,
1847 4, Wn4_Media);
1835 1848
1836 EL3WINDOW(3); 1849 config = window_read32(vp, 3, Wn3_Config);
1837 config = ioread32(ioaddr + Wn3_Config);
1838 config = BFINS(config, dev->if_port, 20, 4); 1850 config = BFINS(config, dev->if_port, 20, 4);
1839 iowrite32(config, ioaddr + Wn3_Config); 1851 window_write32(vp, config, 3, Wn3_Config);
1840 1852
1841 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, 1853 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1842 ioaddr + EL3_CMD); 1854 ioaddr + EL3_CMD);
@@ -1850,7 +1862,6 @@ leave_media_alone:
1850 pr_debug("%s: Media selection timer finished, %s.\n", 1862 pr_debug("%s: Media selection timer finished, %s.\n",
1851 dev->name, media_tbl[dev->if_port].name); 1863 dev->name, media_tbl[dev->if_port].name);
1852 1864
1853 EL3WINDOW(old_window);
1854 enable_irq_lockdep(dev->irq); 1865 enable_irq_lockdep(dev->irq);
1855 mod_timer(&vp->timer, RUN_AT(next_tick)); 1866 mod_timer(&vp->timer, RUN_AT(next_tick));
1856 if (vp->deferred) 1867 if (vp->deferred)
@@ -1865,12 +1876,11 @@ static void vortex_tx_timeout(struct net_device *dev)
1865 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n", 1876 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1866 dev->name, ioread8(ioaddr + TxStatus), 1877 dev->name, ioread8(ioaddr + TxStatus),
1867 ioread16(ioaddr + EL3_STATUS)); 1878 ioread16(ioaddr + EL3_STATUS));
1868 EL3WINDOW(4);
1869 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n", 1879 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1870 ioread16(ioaddr + Wn4_NetDiag), 1880 window_read16(vp, 4, Wn4_NetDiag),
1871 ioread16(ioaddr + Wn4_Media), 1881 window_read16(vp, 4, Wn4_Media),
1872 ioread32(ioaddr + PktStatus), 1882 ioread32(ioaddr + PktStatus),
1873 ioread16(ioaddr + Wn4_FIFODiag)); 1883 window_read16(vp, 4, Wn4_FIFODiag));
1874 /* Slight code bloat to be user friendly. */ 1884 /* Slight code bloat to be user friendly. */
1875 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88) 1885 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1876 pr_err("%s: Transmitter encountered 16 collisions --" 1886 pr_err("%s: Transmitter encountered 16 collisions --"
@@ -1917,9 +1927,6 @@ static void vortex_tx_timeout(struct net_device *dev)
1917 /* Issue Tx Enable */ 1927 /* Issue Tx Enable */
1918 iowrite16(TxEnable, ioaddr + EL3_CMD); 1928 iowrite16(TxEnable, ioaddr + EL3_CMD);
1919 dev->trans_start = jiffies; /* prevent tx timeout */ 1929 dev->trans_start = jiffies; /* prevent tx timeout */
1920
1921 /* Switch to register set 7 for normal use. */
1922 EL3WINDOW(7);
1923} 1930}
1924 1931
1925/* 1932/*
@@ -1980,10 +1987,10 @@ vortex_error(struct net_device *dev, int status)
1980 ioread16(ioaddr + EL3_STATUS) & StatsFull) { 1987 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1981 pr_warning("%s: Updating statistics failed, disabling " 1988 pr_warning("%s: Updating statistics failed, disabling "
1982 "stats as an interrupt source.\n", dev->name); 1989 "stats as an interrupt source.\n", dev->name);
1983 EL3WINDOW(5); 1990 iowrite16(SetIntrEnb |
1984 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD); 1991 (window_read16(vp, 5, 10) & ~StatsFull),
1992 ioaddr + EL3_CMD);
1985 vp->intr_enable &= ~StatsFull; 1993 vp->intr_enable &= ~StatsFull;
1986 EL3WINDOW(7);
1987 DoneDidThat++; 1994 DoneDidThat++;
1988 } 1995 }
1989 } 1996 }
@@ -1993,8 +2000,7 @@ vortex_error(struct net_device *dev, int status)
1993 } 2000 }
1994 if (status & HostError) { 2001 if (status & HostError) {
1995 u16 fifo_diag; 2002 u16 fifo_diag;
1996 EL3WINDOW(4); 2003 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
1997 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1998 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n", 2004 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1999 dev->name, fifo_diag); 2005 dev->name, fifo_diag);
2000 /* Adapter failure requires Tx/Rx reset and reinit. */ 2006 /* Adapter failure requires Tx/Rx reset and reinit. */
@@ -2043,8 +2049,10 @@ vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2043 if (vp->bus_master) { 2049 if (vp->bus_master) {
2044 /* Set the bus-master controller to transfer the packet. */ 2050 /* Set the bus-master controller to transfer the packet. */
2045 int len = (skb->len + 3) & ~3; 2051 int len = (skb->len + 3) & ~3;
2046 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE), 2052 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2047 ioaddr + Wn7_MasterAddr); 2053 PCI_DMA_TODEVICE);
2054 window_set(vp, 7);
2055 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2048 iowrite16(len, ioaddr + Wn7_MasterLen); 2056 iowrite16(len, ioaddr + Wn7_MasterLen);
2049 vp->tx_skb = skb; 2057 vp->tx_skb = skb;
2050 iowrite16(StartDMADown, ioaddr + EL3_CMD); 2058 iowrite16(StartDMADown, ioaddr + EL3_CMD);
@@ -2217,6 +2225,8 @@ vortex_interrupt(int irq, void *dev_id)
2217 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n", 2225 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2218 dev->name, status, ioread8(ioaddr + Timer)); 2226 dev->name, status, ioread8(ioaddr + Timer));
2219 2227
2228 window_set(vp, 7);
2229
2220 do { 2230 do {
2221 if (vortex_debug > 5) 2231 if (vortex_debug > 5)
2222 pr_debug("%s: In interrupt loop, status %4.4x.\n", 2232 pr_debug("%s: In interrupt loop, status %4.4x.\n",
@@ -2760,54 +2770,46 @@ static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2760static void update_stats(void __iomem *ioaddr, struct net_device *dev) 2770static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2761{ 2771{
2762 struct vortex_private *vp = netdev_priv(dev); 2772 struct vortex_private *vp = netdev_priv(dev);
2763 int old_window = ioread16(ioaddr + EL3_CMD);
2764 2773
2765 if (old_window == 0xffff) /* Chip suspended or ejected. */
2766 return;
2767 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */ 2774 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2768 /* Switch to the stats window, and read everything. */ 2775 /* Switch to the stats window, and read everything. */
2769 EL3WINDOW(6); 2776 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2770 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0); 2777 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2771 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1); 2778 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2772 dev->stats.tx_window_errors += ioread8(ioaddr + 4); 2779 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2773 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5); 2780 dev->stats.tx_packets += window_read8(vp, 6, 6);
2774 dev->stats.tx_packets += ioread8(ioaddr + 6); 2781 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2775 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4; 2782 0x30) << 4;
2776 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */ 2783 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2777 /* Don't bother with register 9, an extension of registers 6&7. 2784 /* Don't bother with register 9, an extension of registers 6&7.
2778 If we do use the 6&7 values the atomic update assumption above 2785 If we do use the 6&7 values the atomic update assumption above
2779 is invalid. */ 2786 is invalid. */
2780 dev->stats.rx_bytes += ioread16(ioaddr + 10); 2787 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2781 dev->stats.tx_bytes += ioread16(ioaddr + 12); 2788 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2782 /* Extra stats for get_ethtool_stats() */ 2789 /* Extra stats for get_ethtool_stats() */
2783 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2); 2790 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2784 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3); 2791 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2785 vp->xstats.tx_deferred += ioread8(ioaddr + 8); 2792 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2786 EL3WINDOW(4); 2793 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2787 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2788 2794
2789 dev->stats.collisions = vp->xstats.tx_multiple_collisions 2795 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2790 + vp->xstats.tx_single_collisions 2796 + vp->xstats.tx_single_collisions
2791 + vp->xstats.tx_max_collisions; 2797 + vp->xstats.tx_max_collisions;
2792 2798
2793 { 2799 {
2794 u8 up = ioread8(ioaddr + 13); 2800 u8 up = window_read8(vp, 4, 13);
2795 dev->stats.rx_bytes += (up & 0x0f) << 16; 2801 dev->stats.rx_bytes += (up & 0x0f) << 16;
2796 dev->stats.tx_bytes += (up & 0xf0) << 12; 2802 dev->stats.tx_bytes += (up & 0xf0) << 12;
2797 } 2803 }
2798
2799 EL3WINDOW(old_window >> 13);
2800} 2804}
2801 2805
2802static int vortex_nway_reset(struct net_device *dev) 2806static int vortex_nway_reset(struct net_device *dev)
2803{ 2807{
2804 struct vortex_private *vp = netdev_priv(dev); 2808 struct vortex_private *vp = netdev_priv(dev);
2805 void __iomem *ioaddr = vp->ioaddr;
2806 unsigned long flags; 2809 unsigned long flags;
2807 int rc; 2810 int rc;
2808 2811
2809 spin_lock_irqsave(&vp->lock, flags); 2812 spin_lock_irqsave(&vp->lock, flags);
2810 EL3WINDOW(4);
2811 rc = mii_nway_restart(&vp->mii); 2813 rc = mii_nway_restart(&vp->mii);
2812 spin_unlock_irqrestore(&vp->lock, flags); 2814 spin_unlock_irqrestore(&vp->lock, flags);
2813 return rc; 2815 return rc;
@@ -2816,12 +2818,10 @@ static int vortex_nway_reset(struct net_device *dev)
2816static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2818static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2817{ 2819{
2818 struct vortex_private *vp = netdev_priv(dev); 2820 struct vortex_private *vp = netdev_priv(dev);
2819 void __iomem *ioaddr = vp->ioaddr;
2820 unsigned long flags; 2821 unsigned long flags;
2821 int rc; 2822 int rc;
2822 2823
2823 spin_lock_irqsave(&vp->lock, flags); 2824 spin_lock_irqsave(&vp->lock, flags);
2824 EL3WINDOW(4);
2825 rc = mii_ethtool_gset(&vp->mii, cmd); 2825 rc = mii_ethtool_gset(&vp->mii, cmd);
2826 spin_unlock_irqrestore(&vp->lock, flags); 2826 spin_unlock_irqrestore(&vp->lock, flags);
2827 return rc; 2827 return rc;
@@ -2830,12 +2830,10 @@ static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2830static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2830static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2831{ 2831{
2832 struct vortex_private *vp = netdev_priv(dev); 2832 struct vortex_private *vp = netdev_priv(dev);
2833 void __iomem *ioaddr = vp->ioaddr;
2834 unsigned long flags; 2833 unsigned long flags;
2835 int rc; 2834 int rc;
2836 2835
2837 spin_lock_irqsave(&vp->lock, flags); 2836 spin_lock_irqsave(&vp->lock, flags);
2838 EL3WINDOW(4);
2839 rc = mii_ethtool_sset(&vp->mii, cmd); 2837 rc = mii_ethtool_sset(&vp->mii, cmd);
2840 spin_unlock_irqrestore(&vp->lock, flags); 2838 spin_unlock_irqrestore(&vp->lock, flags);
2841 return rc; 2839 return rc;
@@ -2930,7 +2928,6 @@ static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2930{ 2928{
2931 int err; 2929 int err;
2932 struct vortex_private *vp = netdev_priv(dev); 2930 struct vortex_private *vp = netdev_priv(dev);
2933 void __iomem *ioaddr = vp->ioaddr;
2934 unsigned long flags; 2931 unsigned long flags;
2935 pci_power_t state = 0; 2932 pci_power_t state = 0;
2936 2933
@@ -2942,7 +2939,6 @@ static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2942 if(state != 0) 2939 if(state != 0)
2943 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); 2940 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2944 spin_lock_irqsave(&vp->lock, flags); 2941 spin_lock_irqsave(&vp->lock, flags);
2945 EL3WINDOW(4);
2946 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL); 2942 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2947 spin_unlock_irqrestore(&vp->lock, flags); 2943 spin_unlock_irqrestore(&vp->lock, flags);
2948 if(state != 0) 2944 if(state != 0)
@@ -2985,8 +2981,6 @@ static void set_rx_mode(struct net_device *dev)
2985static void set_8021q_mode(struct net_device *dev, int enable) 2981static void set_8021q_mode(struct net_device *dev, int enable)
2986{ 2982{
2987 struct vortex_private *vp = netdev_priv(dev); 2983 struct vortex_private *vp = netdev_priv(dev);
2988 void __iomem *ioaddr = vp->ioaddr;
2989 int old_window = ioread16(ioaddr + EL3_CMD);
2990 int mac_ctrl; 2984 int mac_ctrl;
2991 2985
2992 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) { 2986 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
@@ -2997,28 +2991,23 @@ static void set_8021q_mode(struct net_device *dev, int enable)
2997 if (enable) 2991 if (enable)
2998 max_pkt_size += 4; /* 802.1Q VLAN tag */ 2992 max_pkt_size += 4; /* 802.1Q VLAN tag */
2999 2993
3000 EL3WINDOW(3); 2994 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3001 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3002 2995
3003 /* set VlanEtherType to let the hardware checksumming 2996 /* set VlanEtherType to let the hardware checksumming
3004 treat tagged frames correctly */ 2997 treat tagged frames correctly */
3005 EL3WINDOW(7); 2998 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3006 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3007 } else { 2999 } else {
3008 /* on older cards we have to enable large frames */ 3000 /* on older cards we have to enable large frames */
3009 3001
3010 vp->large_frames = dev->mtu > 1500 || enable; 3002 vp->large_frames = dev->mtu > 1500 || enable;
3011 3003
3012 EL3WINDOW(3); 3004 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3013 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
3014 if (vp->large_frames) 3005 if (vp->large_frames)
3015 mac_ctrl |= 0x40; 3006 mac_ctrl |= 0x40;
3016 else 3007 else
3017 mac_ctrl &= ~0x40; 3008 mac_ctrl &= ~0x40;
3018 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl); 3009 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3019 } 3010 }
3020
3021 EL3WINDOW(old_window);
3022} 3011}
3023#else 3012#else
3024 3013
@@ -3037,7 +3026,10 @@ static void set_8021q_mode(struct net_device *dev, int enable)
3037/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 3026/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3038 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 3027 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3039 "overclocking" issues. */ 3028 "overclocking" issues. */
3040#define mdio_delay() ioread32(mdio_addr) 3029static void mdio_delay(struct vortex_private *vp)
3030{
3031 window_read32(vp, 4, Wn4_PhysicalMgmt);
3032}
3041 3033
3042#define MDIO_SHIFT_CLK 0x01 3034#define MDIO_SHIFT_CLK 0x01
3043#define MDIO_DIR_WRITE 0x04 3035#define MDIO_DIR_WRITE 0x04
@@ -3048,16 +3040,15 @@ static void set_8021q_mode(struct net_device *dev, int enable)
3048 3040
3049/* Generate the preamble required for initial synchronization and 3041/* Generate the preamble required for initial synchronization and
3050 a few older transceivers. */ 3042 a few older transceivers. */
3051static void mdio_sync(void __iomem *ioaddr, int bits) 3043static void mdio_sync(struct vortex_private *vp, int bits)
3052{ 3044{
3053 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3054
3055 /* Establish sync by sending at least 32 logic ones. */ 3045 /* Establish sync by sending at least 32 logic ones. */
3056 while (-- bits >= 0) { 3046 while (-- bits >= 0) {
3057 iowrite16(MDIO_DATA_WRITE1, mdio_addr); 3047 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3058 mdio_delay(); 3048 mdio_delay(vp);
3059 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); 3049 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3060 mdio_delay(); 3050 4, Wn4_PhysicalMgmt);
3051 mdio_delay(vp);
3061 } 3052 }
3062} 3053}
3063 3054
@@ -3065,29 +3056,31 @@ static int mdio_read(struct net_device *dev, int phy_id, int location)
3065{ 3056{
3066 int i; 3057 int i;
3067 struct vortex_private *vp = netdev_priv(dev); 3058 struct vortex_private *vp = netdev_priv(dev);
3068 void __iomem *ioaddr = vp->ioaddr;
3069 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; 3059 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3070 unsigned int retval = 0; 3060 unsigned int retval = 0;
3071 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3072 3061
3073 if (mii_preamble_required) 3062 if (mii_preamble_required)
3074 mdio_sync(ioaddr, 32); 3063 mdio_sync(vp, 32);
3075 3064
3076 /* Shift the read command bits out. */ 3065 /* Shift the read command bits out. */
3077 for (i = 14; i >= 0; i--) { 3066 for (i = 14; i >= 0; i--) {
3078 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; 3067 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3079 iowrite16(dataval, mdio_addr); 3068 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3080 mdio_delay(); 3069 mdio_delay(vp);
3081 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr); 3070 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3082 mdio_delay(); 3071 4, Wn4_PhysicalMgmt);
3072 mdio_delay(vp);
3083 } 3073 }
3084 /* Read the two transition, 16 data, and wire-idle bits. */ 3074 /* Read the two transition, 16 data, and wire-idle bits. */
3085 for (i = 19; i > 0; i--) { 3075 for (i = 19; i > 0; i--) {
3086 iowrite16(MDIO_ENB_IN, mdio_addr); 3076 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3087 mdio_delay(); 3077 mdio_delay(vp);
3088 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); 3078 retval = (retval << 1) |
3089 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); 3079 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3090 mdio_delay(); 3080 MDIO_DATA_READ) ? 1 : 0);
3081 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3082 4, Wn4_PhysicalMgmt);
3083 mdio_delay(vp);
3091 } 3084 }
3092 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; 3085 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3093} 3086}
@@ -3095,28 +3088,28 @@ static int mdio_read(struct net_device *dev, int phy_id, int location)
3095static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 3088static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3096{ 3089{
3097 struct vortex_private *vp = netdev_priv(dev); 3090 struct vortex_private *vp = netdev_priv(dev);
3098 void __iomem *ioaddr = vp->ioaddr;
3099 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; 3091 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3100 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3101 int i; 3092 int i;
3102 3093
3103 if (mii_preamble_required) 3094 if (mii_preamble_required)
3104 mdio_sync(ioaddr, 32); 3095 mdio_sync(vp, 32);
3105 3096
3106 /* Shift the command bits out. */ 3097 /* Shift the command bits out. */
3107 for (i = 31; i >= 0; i--) { 3098 for (i = 31; i >= 0; i--) {
3108 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; 3099 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3109 iowrite16(dataval, mdio_addr); 3100 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3110 mdio_delay(); 3101 mdio_delay(vp);
3111 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr); 3102 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3112 mdio_delay(); 3103 4, Wn4_PhysicalMgmt);
3104 mdio_delay(vp);
3113 } 3105 }
3114 /* Leave the interface idle. */ 3106 /* Leave the interface idle. */
3115 for (i = 1; i >= 0; i--) { 3107 for (i = 1; i >= 0; i--) {
3116 iowrite16(MDIO_ENB_IN, mdio_addr); 3108 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3117 mdio_delay(); 3109 mdio_delay(vp);
3118 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); 3110 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3119 mdio_delay(); 3111 4, Wn4_PhysicalMgmt);
3112 mdio_delay(vp);
3120 } 3113 }
3121} 3114}
3122 3115
@@ -3131,8 +3124,7 @@ static void acpi_set_WOL(struct net_device *dev)
3131 3124
3132 if (vp->enable_wol) { 3125 if (vp->enable_wol) {
3133 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ 3126 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3134 EL3WINDOW(7); 3127 window_write16(vp, 2, 7, 0x0c);
3135 iowrite16(2, ioaddr + 0x0c);
3136 /* The RxFilter must accept the WOL frames. */ 3128 /* The RxFilter must accept the WOL frames. */
3137 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD); 3129 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3138 iowrite16(RxEnable, ioaddr + EL3_CMD); 3130 iowrite16(RxEnable, ioaddr + EL3_CMD);