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authorAaron Sierra <asierra@xes-inc.com>2014-08-26 19:18:33 -0400
committerBrian Norris <computersforpeace@gmail.com>2014-11-05 17:45:53 -0500
commit096916610f415e07cfe71d71a391011c617be5ed (patch)
tree0e2c9596200462aff4a267607a134ba16f308d95 /drivers/mtd
parentabb1cd00e6b7434e866f1f817b4994e1c7f1f16d (diff)
fsl_ifc: Support all 8 IFC chip selects
Freescale's QorIQ T Series processors support 8 IFC chip selects within a memory map backward compatible with previous P Series processors which supported only 4 chip selects. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 2338124dd05f..4d40fdb24187 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -31,7 +31,6 @@
31#include <linux/mtd/nand_ecc.h> 31#include <linux/mtd/nand_ecc.h>
32#include <linux/fsl_ifc.h> 32#include <linux/fsl_ifc.h>
33 33
34#define FSL_IFC_V1_1_0 0x01010000
35#define ERR_BYTE 0xFF /* Value returned for read 34#define ERR_BYTE 0xFF /* Value returned for read
36 bytes when read failed */ 35 bytes when read failed */
37#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait 36#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
@@ -877,7 +876,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
877 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; 876 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
878 struct nand_chip *chip = &priv->chip; 877 struct nand_chip *chip = &priv->chip;
879 struct nand_ecclayout *layout; 878 struct nand_ecclayout *layout;
880 u32 csor, ver; 879 u32 csor;
881 880
882 /* Fill in fsl_ifc_mtd structure */ 881 /* Fill in fsl_ifc_mtd structure */
883 priv->mtd.priv = chip; 882 priv->mtd.priv = chip;
@@ -984,8 +983,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
984 chip->ecc.mode = NAND_ECC_SOFT; 983 chip->ecc.mode = NAND_ECC_SOFT;
985 } 984 }
986 985
987 ver = ioread32be(&ifc->ifc_rev); 986 if (ctrl->version == FSL_IFC_VERSION_1_1_0)
988 if (ver == FSL_IFC_V1_1_0)
989 fsl_ifc_sram_init(priv); 987 fsl_ifc_sram_init(priv);
990 988
991 return 0; 989 return 0;
@@ -1045,12 +1043,12 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
1045 } 1043 }
1046 1044
1047 /* find which chip select it is connected to */ 1045 /* find which chip select it is connected to */
1048 for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) { 1046 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1049 if (match_bank(ifc, bank, res.start)) 1047 if (match_bank(ifc, bank, res.start))
1050 break; 1048 break;
1051 } 1049 }
1052 1050
1053 if (bank >= FSL_IFC_BANK_COUNT) { 1051 if (bank >= fsl_ifc_ctrl_dev->banks) {
1054 dev_err(&dev->dev, "%s: address did not match any chip selects\n", 1052 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1055 __func__); 1053 __func__);
1056 return -ENODEV; 1054 return -ENODEV;