diff options
author | Enrico Scholz <enrico.scholz@sigma-chemnitz.de> | 2008-08-29 06:59:51 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-09-01 16:38:34 -0400 |
commit | c8c17c888d936c58ceb28b084a6272d67e10ea28 (patch) | |
tree | 6aaf879d3ef5f35c287ac0b78d521ad432712519 /drivers/mtd | |
parent | 7dad482ed0648a40e403d1ed44e0ea92248632f1 (diff) |
[MTD] [NAND] pxa3xx_nand: moved some helper variables out from platform data
This patch moves some attributes out from the platform data into the
dynamically created nand device. This results into a cleaner interface
and allows to use constant pxa3xx_nand_flash definitions.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/nand/pxa3xx_nand.c | 43 |
1 files changed, 25 insertions, 18 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index af174054656e..bc37f551edf5 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c | |||
@@ -119,7 +119,7 @@ struct pxa3xx_nand_info { | |||
119 | struct nand_chip nand_chip; | 119 | struct nand_chip nand_chip; |
120 | 120 | ||
121 | struct platform_device *pdev; | 121 | struct platform_device *pdev; |
122 | struct pxa3xx_nand_flash *flash_info; | 122 | const struct pxa3xx_nand_flash *flash_info; |
123 | 123 | ||
124 | struct clk *clk; | 124 | struct clk *clk; |
125 | void __iomem *mmio_base; | 125 | void __iomem *mmio_base; |
@@ -158,6 +158,13 @@ struct pxa3xx_nand_info { | |||
158 | uint32_t ndcb0; | 158 | uint32_t ndcb0; |
159 | uint32_t ndcb1; | 159 | uint32_t ndcb1; |
160 | uint32_t ndcb2; | 160 | uint32_t ndcb2; |
161 | |||
162 | /* calculated from pxa3xx_nand_flash data */ | ||
163 | size_t oob_size; | ||
164 | size_t read_id_bytes; | ||
165 | |||
166 | unsigned int col_addr_cycles; | ||
167 | unsigned int row_addr_cycles; | ||
161 | }; | 168 | }; |
162 | 169 | ||
163 | static int use_dma = 1; | 170 | static int use_dma = 1; |
@@ -335,7 +342,7 @@ static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event) | |||
335 | static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info, | 342 | static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info, |
336 | uint16_t cmd, int column, int page_addr) | 343 | uint16_t cmd, int column, int page_addr) |
337 | { | 344 | { |
338 | struct pxa3xx_nand_flash *f = info->flash_info; | 345 | const struct pxa3xx_nand_flash *f = info->flash_info; |
339 | const struct pxa3xx_nand_cmdset *cmdset = f->cmdset; | 346 | const struct pxa3xx_nand_cmdset *cmdset = f->cmdset; |
340 | 347 | ||
341 | /* calculate data size */ | 348 | /* calculate data size */ |
@@ -354,14 +361,14 @@ static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info, | |||
354 | info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0); | 361 | info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0); |
355 | info->ndcb1 = 0; | 362 | info->ndcb1 = 0; |
356 | info->ndcb2 = 0; | 363 | info->ndcb2 = 0; |
357 | info->ndcb0 |= NDCB0_ADDR_CYC(f->row_addr_cycles + f->col_addr_cycles); | 364 | info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles); |
358 | 365 | ||
359 | if (f->col_addr_cycles == 2) { | 366 | if (info->col_addr_cycles == 2) { |
360 | /* large block, 2 cycles for column address | 367 | /* large block, 2 cycles for column address |
361 | * row address starts from 3rd cycle | 368 | * row address starts from 3rd cycle |
362 | */ | 369 | */ |
363 | info->ndcb1 |= (page_addr << 16) | (column & 0xffff); | 370 | info->ndcb1 |= (page_addr << 16) | (column & 0xffff); |
364 | if (f->row_addr_cycles == 3) | 371 | if (info->row_addr_cycles == 3) |
365 | info->ndcb2 = (page_addr >> 16) & 0xff; | 372 | info->ndcb2 = (page_addr >> 16) & 0xff; |
366 | } else | 373 | } else |
367 | /* small block, 1 cycles for column address | 374 | /* small block, 1 cycles for column address |
@@ -622,7 +629,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |||
622 | int column, int page_addr) | 629 | int column, int page_addr) |
623 | { | 630 | { |
624 | struct pxa3xx_nand_info *info = mtd->priv; | 631 | struct pxa3xx_nand_info *info = mtd->priv; |
625 | struct pxa3xx_nand_flash *flash_info = info->flash_info; | 632 | const struct pxa3xx_nand_flash *flash_info = info->flash_info; |
626 | const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset; | 633 | const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset; |
627 | int ret; | 634 | int ret; |
628 | 635 | ||
@@ -701,7 +708,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |||
701 | info->use_dma = 0; /* force PIO read */ | 708 | info->use_dma = 0; /* force PIO read */ |
702 | info->buf_start = 0; | 709 | info->buf_start = 0; |
703 | info->buf_count = (command == NAND_CMD_READID) ? | 710 | info->buf_count = (command == NAND_CMD_READID) ? |
704 | flash_info->read_id_bytes : 1; | 711 | info->read_id_bytes : 1; |
705 | 712 | ||
706 | if (prepare_other_cmd(info, (command == NAND_CMD_READID) ? | 713 | if (prepare_other_cmd(info, (command == NAND_CMD_READID) ? |
707 | cmdset->read_id : cmdset->read_status)) | 714 | cmdset->read_id : cmdset->read_status)) |
@@ -842,7 +849,7 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd, | |||
842 | 849 | ||
843 | static int __readid(struct pxa3xx_nand_info *info, uint32_t *id) | 850 | static int __readid(struct pxa3xx_nand_info *info, uint32_t *id) |
844 | { | 851 | { |
845 | struct pxa3xx_nand_flash *f = info->flash_info; | 852 | const struct pxa3xx_nand_flash *f = info->flash_info; |
846 | const struct pxa3xx_nand_cmdset *cmdset = f->cmdset; | 853 | const struct pxa3xx_nand_cmdset *cmdset = f->cmdset; |
847 | uint32_t ndcr; | 854 | uint32_t ndcr; |
848 | uint8_t id_buff[8]; | 855 | uint8_t id_buff[8]; |
@@ -872,7 +879,7 @@ fail_timeout: | |||
872 | } | 879 | } |
873 | 880 | ||
874 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, | 881 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
875 | struct pxa3xx_nand_flash *f) | 882 | const struct pxa3xx_nand_flash *f) |
876 | { | 883 | { |
877 | struct platform_device *pdev = info->pdev; | 884 | struct platform_device *pdev = info->pdev; |
878 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | 885 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; |
@@ -885,25 +892,25 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, | |||
885 | return -EINVAL; | 892 | return -EINVAL; |
886 | 893 | ||
887 | /* calculate flash information */ | 894 | /* calculate flash information */ |
888 | f->oob_size = (f->page_size == 2048) ? 64 : 16; | 895 | info->oob_size = (f->page_size == 2048) ? 64 : 16; |
889 | f->read_id_bytes = (f->page_size == 2048) ? 4 : 2; | 896 | info->read_id_bytes = (f->page_size == 2048) ? 4 : 2; |
890 | 897 | ||
891 | /* calculate addressing information */ | 898 | /* calculate addressing information */ |
892 | f->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; | 899 | info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
893 | 900 | ||
894 | if (f->num_blocks * f->page_per_block > 65536) | 901 | if (f->num_blocks * f->page_per_block > 65536) |
895 | f->row_addr_cycles = 3; | 902 | info->row_addr_cycles = 3; |
896 | else | 903 | else |
897 | f->row_addr_cycles = 2; | 904 | info->row_addr_cycles = 2; |
898 | 905 | ||
899 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | 906 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; |
900 | ndcr |= (f->col_addr_cycles == 2) ? NDCR_RA_START : 0; | 907 | ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
901 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; | 908 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
902 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | 909 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; |
903 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | 910 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; |
904 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | 911 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; |
905 | 912 | ||
906 | ndcr |= NDCR_RD_ID_CNT(f->read_id_bytes); | 913 | ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes); |
907 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ | 914 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
908 | 915 | ||
909 | info->reg_ndcr = ndcr; | 916 | info->reg_ndcr = ndcr; |
@@ -916,7 +923,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, | |||
916 | static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info, | 923 | static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info, |
917 | const struct pxa3xx_nand_platform_data *pdata) | 924 | const struct pxa3xx_nand_platform_data *pdata) |
918 | { | 925 | { |
919 | struct pxa3xx_nand_flash *f; | 926 | const struct pxa3xx_nand_flash *f; |
920 | uint32_t id; | 927 | uint32_t id; |
921 | int i; | 928 | int i; |
922 | 929 | ||
@@ -1011,7 +1018,7 @@ static struct nand_ecclayout hw_largepage_ecclayout = { | |||
1011 | static void pxa3xx_nand_init_mtd(struct mtd_info *mtd, | 1018 | static void pxa3xx_nand_init_mtd(struct mtd_info *mtd, |
1012 | struct pxa3xx_nand_info *info) | 1019 | struct pxa3xx_nand_info *info) |
1013 | { | 1020 | { |
1014 | struct pxa3xx_nand_flash *f = info->flash_info; | 1021 | const struct pxa3xx_nand_flash *f = info->flash_info; |
1015 | struct nand_chip *this = &info->nand_chip; | 1022 | struct nand_chip *this = &info->nand_chip; |
1016 | 1023 | ||
1017 | this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0; | 1024 | this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0; |