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authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-06-27 15:04:04 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-11 13:12:01 -0400
commit452db2724351ff3d9416a183a7955e00ab4e6ab4 (patch)
treebdd310ead274e7cb02e0564c898f97b4e391a20a /drivers/mtd
parentbd5a43822b438f297f4088f1cfd3514e32e56328 (diff)
[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
For large page chips, nand_bbt is looking into OOB area, and checking for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be reserved for bbt means. But ELBC driver is specifying ecclayout so that oobfree area starts at offset 1, so only one byte left for the bbt purposes. This causes problems with any OOB users, namely JFFS2: after first mount JFFS2 will fill all OOBs with "erased marker", so OOBs will contain: OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff And on the next boot, NAND core will rescan for bad blocks, then will see "0xff 0x19" pattern, and will mark all blocks as bad ones. To fix the issue we should implement our own bad block pattern: just one byte at OOB start. Though, this will work only for x8 chips. For x16 chips two bytes must be checked. Since ELBC driver does not support x16 NANDs (yet), we're safe for now. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 1b06d29dd06b..99dc2be620a6 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -116,6 +116,20 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
116 .oobavail = 48, 116 .oobavail = 48,
117}; 117};
118 118
119/*
120 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
121 * 1, so we have to adjust bad block pattern. This pattern should be used for
122 * x8 chips only. So far hardware does not support x16 chips anyway.
123 */
124static u8 scan_ff_pattern[] = { 0xff, };
125
126static struct nand_bbt_descr largepage_memorybased = {
127 .options = 0,
128 .offs = 0,
129 .len = 1,
130 .pattern = scan_ff_pattern,
131};
132
119/*=================================*/ 133/*=================================*/
120 134
121/* 135/*
@@ -687,6 +701,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
687 chip->ecc.layout = (priv->fmr & FMR_ECCM) ? 701 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
688 &fsl_elbc_oob_lp_eccm1 : 702 &fsl_elbc_oob_lp_eccm1 :
689 &fsl_elbc_oob_lp_eccm0; 703 &fsl_elbc_oob_lp_eccm0;
704 chip->badblock_pattern = &largepage_memorybased;
690 mtd->ecclayout = chip->ecc.layout; 705 mtd->ecclayout = chip->ecc.layout;
691 mtd->oobavail = chip->ecc.layout->oobavail; 706 mtd->oobavail = chip->ecc.layout->oobavail;
692 } 707 }