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authorPekon Gupta <pekon@ti.com>2013-10-24 08:50:19 -0400
committerBrian Norris <computersforpeace@gmail.com>2013-11-07 02:33:08 -0500
commit633deb58e1ecc81486505fe9d3dc2aa3cfbca719 (patch)
tree65d7843841d50b291cf5fffed415ed9048769a78 /drivers/mtd
parentc66d039197e42af8867e5d0d9b904daf0fb9e6bc (diff)
mtd: nand: omap: cleanup: replace local references with generic framework names
This patch updates following in omap_nand_probe() and omap_nand_remove() - replaces "info->nand" with "nand_chip" (struct nand_chip *nand_chip) - replaces "info->mtd" with "mtd" (struct mtd_info *mtd) - white-space and formatting cleanup Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/omap2.c112
1 files changed, 57 insertions, 55 deletions
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 8d521aa001c8..5596368a3574 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1824,10 +1824,12 @@ static int omap_nand_probe(struct platform_device *pdev)
1824{ 1824{
1825 struct omap_nand_info *info; 1825 struct omap_nand_info *info;
1826 struct omap_nand_platform_data *pdata; 1826 struct omap_nand_platform_data *pdata;
1827 struct mtd_info *mtd;
1828 struct nand_chip *nand_chip;
1827 int err; 1829 int err;
1828 int i, offset; 1830 int i, offset;
1829 dma_cap_mask_t mask; 1831 dma_cap_mask_t mask;
1830 unsigned sig; 1832 unsigned sig;
1831 struct resource *res; 1833 struct resource *res;
1832 struct mtd_part_parser_data ppdata = {}; 1834 struct mtd_part_parser_data ppdata = {};
1833 1835
@@ -1846,17 +1848,16 @@ static int omap_nand_probe(struct platform_device *pdev)
1846 spin_lock_init(&info->controller.lock); 1848 spin_lock_init(&info->controller.lock);
1847 init_waitqueue_head(&info->controller.wq); 1849 init_waitqueue_head(&info->controller.wq);
1848 1850
1849 info->pdev = pdev; 1851 info->pdev = pdev;
1850
1851 info->gpmc_cs = pdata->cs; 1852 info->gpmc_cs = pdata->cs;
1852 info->reg = pdata->reg; 1853 info->reg = pdata->reg;
1853 1854 mtd = &info->mtd;
1854 info->mtd.priv = &info->nand; 1855 mtd->priv = &info->nand;
1855 info->mtd.name = dev_name(&pdev->dev); 1856 mtd->name = dev_name(&pdev->dev);
1856 info->mtd.owner = THIS_MODULE; 1857 mtd->owner = THIS_MODULE;
1857 1858 nand_chip = &info->nand;
1858 info->nand.options = pdata->devsize; 1859 nand_chip->options = pdata->devsize;
1859 info->nand.options |= NAND_SKIP_BBTSCAN; 1860 nand_chip->options |= NAND_SKIP_BBTSCAN;
1860#ifdef CONFIG_MTD_NAND_OMAP_BCH 1861#ifdef CONFIG_MTD_NAND_OMAP_BCH
1861 info->of_node = pdata->of_node; 1862 info->of_node = pdata->of_node;
1862#endif 1863#endif
@@ -1877,16 +1878,16 @@ static int omap_nand_probe(struct platform_device *pdev)
1877 goto out_free_info; 1878 goto out_free_info;
1878 } 1879 }
1879 1880
1880 info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); 1881 nand_chip->IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
1881 if (!info->nand.IO_ADDR_R) { 1882 if (!nand_chip->IO_ADDR_R) {
1882 err = -ENOMEM; 1883 err = -ENOMEM;
1883 goto out_release_mem_region; 1884 goto out_release_mem_region;
1884 } 1885 }
1885 1886
1886 info->nand.controller = &info->controller; 1887 nand_chip->controller = &info->controller;
1887 1888
1888 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; 1889 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1889 info->nand.cmd_ctrl = omap_hwcontrol; 1890 nand_chip->cmd_ctrl = omap_hwcontrol;
1890 1891
1891 /* 1892 /*
1892 * If RDY/BSY line is connected to OMAP then use the omap ready 1893 * If RDY/BSY line is connected to OMAP then use the omap ready
@@ -1896,26 +1897,26 @@ static int omap_nand_probe(struct platform_device *pdev)
1896 * device and read status register until you get a failure or success 1897 * device and read status register until you get a failure or success
1897 */ 1898 */
1898 if (pdata->dev_ready) { 1899 if (pdata->dev_ready) {
1899 info->nand.dev_ready = omap_dev_ready; 1900 nand_chip->dev_ready = omap_dev_ready;
1900 info->nand.chip_delay = 0; 1901 nand_chip->chip_delay = 0;
1901 } else { 1902 } else {
1902 info->nand.waitfunc = omap_wait; 1903 nand_chip->waitfunc = omap_wait;
1903 info->nand.chip_delay = 50; 1904 nand_chip->chip_delay = 50;
1904 } 1905 }
1905 1906
1906 switch (pdata->xfer_type) { 1907 switch (pdata->xfer_type) {
1907 case NAND_OMAP_PREFETCH_POLLED: 1908 case NAND_OMAP_PREFETCH_POLLED:
1908 info->nand.read_buf = omap_read_buf_pref; 1909 nand_chip->read_buf = omap_read_buf_pref;
1909 info->nand.write_buf = omap_write_buf_pref; 1910 nand_chip->write_buf = omap_write_buf_pref;
1910 break; 1911 break;
1911 1912
1912 case NAND_OMAP_POLLED: 1913 case NAND_OMAP_POLLED:
1913 if (info->nand.options & NAND_BUSWIDTH_16) { 1914 if (nand_chip->options & NAND_BUSWIDTH_16) {
1914 info->nand.read_buf = omap_read_buf16; 1915 nand_chip->read_buf = omap_read_buf16;
1915 info->nand.write_buf = omap_write_buf16; 1916 nand_chip->write_buf = omap_write_buf16;
1916 } else { 1917 } else {
1917 info->nand.read_buf = omap_read_buf8; 1918 nand_chip->read_buf = omap_read_buf8;
1918 info->nand.write_buf = omap_write_buf8; 1919 nand_chip->write_buf = omap_write_buf8;
1919 } 1920 }
1920 break; 1921 break;
1921 1922
@@ -1944,8 +1945,8 @@ static int omap_nand_probe(struct platform_device *pdev)
1944 err); 1945 err);
1945 goto out_release_mem_region; 1946 goto out_release_mem_region;
1946 } 1947 }
1947 info->nand.read_buf = omap_read_buf_dma_pref; 1948 nand_chip->read_buf = omap_read_buf_dma_pref;
1948 info->nand.write_buf = omap_write_buf_dma_pref; 1949 nand_chip->write_buf = omap_write_buf_dma_pref;
1949 } 1950 }
1950 break; 1951 break;
1951 1952
@@ -1980,8 +1981,8 @@ static int omap_nand_probe(struct platform_device *pdev)
1980 goto out_release_mem_region; 1981 goto out_release_mem_region;
1981 } 1982 }
1982 1983
1983 info->nand.read_buf = omap_read_buf_irq_pref; 1984 nand_chip->read_buf = omap_read_buf_irq_pref;
1984 info->nand.write_buf = omap_write_buf_irq_pref; 1985 nand_chip->write_buf = omap_write_buf_irq_pref;
1985 1986
1986 break; 1987 break;
1987 1988
@@ -1994,16 +1995,16 @@ static int omap_nand_probe(struct platform_device *pdev)
1994 1995
1995 /* select the ecc type */ 1996 /* select the ecc type */
1996 if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) { 1997 if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
1997 info->nand.ecc.bytes = 3; 1998 nand_chip->ecc.bytes = 3;
1998 info->nand.ecc.size = 512; 1999 nand_chip->ecc.size = 512;
1999 info->nand.ecc.strength = 1; 2000 nand_chip->ecc.strength = 1;
2000 info->nand.ecc.calculate = omap_calculate_ecc; 2001 nand_chip->ecc.calculate = omap_calculate_ecc;
2001 info->nand.ecc.hwctl = omap_enable_hwecc; 2002 nand_chip->ecc.hwctl = omap_enable_hwecc;
2002 info->nand.ecc.correct = omap_correct_data; 2003 nand_chip->ecc.correct = omap_correct_data;
2003 info->nand.ecc.mode = NAND_ECC_HW; 2004 nand_chip->ecc.mode = NAND_ECC_HW;
2004 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || 2005 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
2005 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { 2006 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
2006 err = omap3_init_bch(&info->mtd, pdata->ecc_opt); 2007 err = omap3_init_bch(mtd, pdata->ecc_opt);
2007 if (err) { 2008 if (err) {
2008 err = -EINVAL; 2009 err = -EINVAL;
2009 goto out_release_mem_region; 2010 goto out_release_mem_region;
@@ -2013,9 +2014,9 @@ static int omap_nand_probe(struct platform_device *pdev)
2013 /* DIP switches on some boards change between 8 and 16 bit 2014 /* DIP switches on some boards change between 8 and 16 bit
2014 * bus widths for flash. Try the other width if the first try fails. 2015 * bus widths for flash. Try the other width if the first try fails.
2015 */ 2016 */
2016 if (nand_scan_ident(&info->mtd, 1, NULL)) { 2017 if (nand_scan_ident(mtd, 1, NULL)) {
2017 info->nand.options ^= NAND_BUSWIDTH_16; 2018 nand_chip->options ^= NAND_BUSWIDTH_16;
2018 if (nand_scan_ident(&info->mtd, 1, NULL)) { 2019 if (nand_scan_ident(mtd, 1, NULL)) {
2019 err = -ENXIO; 2020 err = -ENXIO;
2020 goto out_release_mem_region; 2021 goto out_release_mem_region;
2021 } 2022 }
@@ -2024,25 +2025,25 @@ static int omap_nand_probe(struct platform_device *pdev)
2024 /* rom code layout */ 2025 /* rom code layout */
2025 if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) { 2026 if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
2026 2027
2027 if (info->nand.options & NAND_BUSWIDTH_16) 2028 if (nand_chip->options & NAND_BUSWIDTH_16) {
2028 offset = 2; 2029 offset = 2;
2029 else { 2030 } else {
2030 offset = 1; 2031 offset = 1;
2031 info->nand.badblock_pattern = &bb_descrip_flashbased; 2032 nand_chip->badblock_pattern = &bb_descrip_flashbased;
2032 } 2033 }
2033 omap_oobinfo.eccbytes = 3 * (info->mtd.writesize / 512); 2034 omap_oobinfo.eccbytes = 3 * (mtd->writesize / 512);
2034 for (i = 0; i < omap_oobinfo.eccbytes; i++) 2035 for (i = 0; i < omap_oobinfo.eccbytes; i++)
2035 omap_oobinfo.eccpos[i] = i+offset; 2036 omap_oobinfo.eccpos[i] = i+offset;
2036 2037
2037 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; 2038 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
2038 omap_oobinfo.oobfree->length = info->mtd.oobsize - 2039 omap_oobinfo.oobfree->length = mtd->oobsize -
2039 (offset + omap_oobinfo.eccbytes); 2040 (offset + omap_oobinfo.eccbytes);
2040 2041
2041 info->nand.ecc.layout = &omap_oobinfo; 2042 nand_chip->ecc.layout = &omap_oobinfo;
2042 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || 2043 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
2043 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { 2044 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
2044 /* build OOB layout for BCH ECC correction */ 2045 /* build OOB layout for BCH ECC correction */
2045 err = omap3_init_bch_tail(&info->mtd); 2046 err = omap3_init_bch_tail(mtd);
2046 if (err) { 2047 if (err) {
2047 err = -EINVAL; 2048 err = -EINVAL;
2048 goto out_release_mem_region; 2049 goto out_release_mem_region;
@@ -2050,16 +2051,16 @@ static int omap_nand_probe(struct platform_device *pdev)
2050 } 2051 }
2051 2052
2052 /* second phase scan */ 2053 /* second phase scan */
2053 if (nand_scan_tail(&info->mtd)) { 2054 if (nand_scan_tail(mtd)) {
2054 err = -ENXIO; 2055 err = -ENXIO;
2055 goto out_release_mem_region; 2056 goto out_release_mem_region;
2056 } 2057 }
2057 2058
2058 ppdata.of_node = pdata->of_node; 2059 ppdata.of_node = pdata->of_node;
2059 mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts, 2060 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2060 pdata->nr_parts); 2061 pdata->nr_parts);
2061 2062
2062 platform_set_drvdata(pdev, &info->mtd); 2063 platform_set_drvdata(pdev, mtd);
2063 2064
2064 return 0; 2065 return 0;
2065 2066
@@ -2080,9 +2081,10 @@ out_free_info:
2080static int omap_nand_remove(struct platform_device *pdev) 2081static int omap_nand_remove(struct platform_device *pdev)
2081{ 2082{
2082 struct mtd_info *mtd = platform_get_drvdata(pdev); 2083 struct mtd_info *mtd = platform_get_drvdata(pdev);
2084 struct nand_chip *nand_chip = mtd->priv;
2083 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 2085 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2084 mtd); 2086 mtd);
2085 omap3_free_bch(&info->mtd); 2087 omap3_free_bch(mtd);
2086 2088
2087 if (info->dma) 2089 if (info->dma)
2088 dma_release_channel(info->dma); 2090 dma_release_channel(info->dma);
@@ -2093,8 +2095,8 @@ static int omap_nand_remove(struct platform_device *pdev)
2093 free_irq(info->gpmc_irq_fifo, info); 2095 free_irq(info->gpmc_irq_fifo, info);
2094 2096
2095 /* Release NAND device, its internal structures and partitions */ 2097 /* Release NAND device, its internal structures and partitions */
2096 nand_release(&info->mtd); 2098 nand_release(mtd);
2097 iounmap(info->nand.IO_ADDR_R); 2099 iounmap(nand_chip->IO_ADDR_R);
2098 release_mem_region(info->phys_base, info->mem_size); 2100 release_mem_region(info->phys_base, info->mem_size);
2099 kfree(info); 2101 kfree(info);
2100 return 0; 2102 return 0;