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authorGuillaume LECERF <glecerf@gmail.com>2010-04-24 11:58:27 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-05-13 20:39:43 -0400
commit5a0563f0ad0c9864b735e9ae23e55f7fa9c73bf5 (patch)
treeae4bf49ea99726a95134a411982391b604a7b97a /drivers/mtd
parent83dcd3bb1139060fedb15235f8614d2bac82e18d (diff)
mtd: cfi_cmdset_0002: add CFI detection for SST 39VF{32, 64}xxB chips
This patch adds support for detecting SST 39VF32xxB and 39VF64xxB chips in CFI mode. Signed-off-by: Guillaume LECERF <glecerf@gmail.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index b7d821d61836..0e21b0982480 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -283,6 +283,17 @@ static void fixup_sst39vf(struct mtd_info *mtd, void *param)
283 cfi->addr_unlock2 = 0x2AAA; 283 cfi->addr_unlock2 = 0x2AAA;
284} 284}
285 285
286static void fixup_sst39vf_rev_b(struct mtd_info *mtd, void *param)
287{
288 struct map_info *map = mtd->priv;
289 struct cfi_private *cfi = map->fldrv_priv;
290
291 fixup_old_sst_eraseregion(mtd);
292
293 cfi->addr_unlock1 = 0x555;
294 cfi->addr_unlock2 = 0x2AA;
295}
296
286static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param) 297static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
287{ 298{
288 struct map_info *map = mtd->priv; 299 struct map_info *map = mtd->priv;
@@ -311,6 +322,10 @@ static struct cfi_fixup cfi_nopri_fixup_table[] = {
311 { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601 322 { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601
312 { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202 323 { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202
313 { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201 324 { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201
325 { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, // SST39VF3202B
326 { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, // SST39VF3201B
327 { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, // SST39VF6402B
328 { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, // SST39VF6401B
314 { 0, 0, NULL, NULL } 329 { 0, 0, NULL, NULL }
315}; 330};
316 331