diff options
author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-09-08 22:01:52 -0400 |
---|---|---|
committer | Brian Norris <computersforpeace@gmail.com> | 2014-09-15 19:31:03 -0400 |
commit | 5637b69d1c489d4585c94a2a1d0a38f4e6b1a705 (patch) | |
tree | 891ee4b49165f6a0c56c2368139c27844da75736 /drivers/mtd | |
parent | 43914a2dcc8f9fc1c25e6bd2650d8e7ad1a9b04a (diff) |
mtd: denali: remove unnecessary variable initializations
All of these variables are initialized to zero and then
set to a different value below.
Zero-initializing is redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/nand/denali.c | 59 |
1 files changed, 27 insertions, 32 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 766af04d1cb3..20823df2c1bf 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -146,7 +146,7 @@ static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |||
146 | /* reads the status of the device */ | 146 | /* reads the status of the device */ |
147 | static void read_status(struct denali_nand_info *denali) | 147 | static void read_status(struct denali_nand_info *denali) |
148 | { | 148 | { |
149 | uint32_t cmd = 0x0; | 149 | uint32_t cmd; |
150 | 150 | ||
151 | /* initialize the data buffer to store status */ | 151 | /* initialize the data buffer to store status */ |
152 | reset_buf(denali); | 152 | reset_buf(denali); |
@@ -161,7 +161,7 @@ static void read_status(struct denali_nand_info *denali) | |||
161 | /* resets a specific device connected to the core */ | 161 | /* resets a specific device connected to the core */ |
162 | static void reset_bank(struct denali_nand_info *denali) | 162 | static void reset_bank(struct denali_nand_info *denali) |
163 | { | 163 | { |
164 | uint32_t irq_status = 0; | 164 | uint32_t irq_status; |
165 | uint32_t irq_mask = INTR_STATUS__RST_COMP | | 165 | uint32_t irq_mask = INTR_STATUS__RST_COMP | |
166 | INTR_STATUS__TIME_OUT; | 166 | INTR_STATUS__TIME_OUT; |
167 | 167 | ||
@@ -581,7 +581,7 @@ static inline bool is_flash_bank_valid(int flash_bank) | |||
581 | 581 | ||
582 | static void denali_irq_init(struct denali_nand_info *denali) | 582 | static void denali_irq_init(struct denali_nand_info *denali) |
583 | { | 583 | { |
584 | uint32_t int_mask = 0; | 584 | uint32_t int_mask; |
585 | int i; | 585 | int i; |
586 | 586 | ||
587 | /* Disable global interrupts */ | 587 | /* Disable global interrupts */ |
@@ -624,7 +624,7 @@ static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |||
624 | static inline void clear_interrupt(struct denali_nand_info *denali, | 624 | static inline void clear_interrupt(struct denali_nand_info *denali, |
625 | uint32_t irq_mask) | 625 | uint32_t irq_mask) |
626 | { | 626 | { |
627 | uint32_t intr_status_reg = 0; | 627 | uint32_t intr_status_reg; |
628 | 628 | ||
629 | intr_status_reg = INTR_STATUS(denali->flash_bank); | 629 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
630 | 630 | ||
@@ -633,7 +633,8 @@ static inline void clear_interrupt(struct denali_nand_info *denali, | |||
633 | 633 | ||
634 | static void clear_interrupts(struct denali_nand_info *denali) | 634 | static void clear_interrupts(struct denali_nand_info *denali) |
635 | { | 635 | { |
636 | uint32_t status = 0x0; | 636 | uint32_t status; |
637 | |||
637 | spin_lock_irq(&denali->irq_lock); | 638 | spin_lock_irq(&denali->irq_lock); |
638 | 639 | ||
639 | status = read_interrupt_status(denali); | 640 | status = read_interrupt_status(denali); |
@@ -645,7 +646,7 @@ static void clear_interrupts(struct denali_nand_info *denali) | |||
645 | 646 | ||
646 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | 647 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) |
647 | { | 648 | { |
648 | uint32_t intr_status_reg = 0; | 649 | uint32_t intr_status_reg; |
649 | 650 | ||
650 | intr_status_reg = INTR_STATUS(denali->flash_bank); | 651 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
651 | 652 | ||
@@ -659,7 +660,7 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |||
659 | static irqreturn_t denali_isr(int irq, void *dev_id) | 660 | static irqreturn_t denali_isr(int irq, void *dev_id) |
660 | { | 661 | { |
661 | struct denali_nand_info *denali = dev_id; | 662 | struct denali_nand_info *denali = dev_id; |
662 | uint32_t irq_status = 0x0; | 663 | uint32_t irq_status; |
663 | irqreturn_t result = IRQ_NONE; | 664 | irqreturn_t result = IRQ_NONE; |
664 | 665 | ||
665 | spin_lock(&denali->irq_lock); | 666 | spin_lock(&denali->irq_lock); |
@@ -693,8 +694,8 @@ static irqreturn_t denali_isr(int irq, void *dev_id) | |||
693 | 694 | ||
694 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | 695 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) |
695 | { | 696 | { |
696 | unsigned long comp_res = 0; | 697 | unsigned long comp_res; |
697 | uint32_t intr_status = 0; | 698 | uint32_t intr_status; |
698 | bool retry = false; | 699 | bool retry = false; |
699 | unsigned long timeout = msecs_to_jiffies(1000); | 700 | unsigned long timeout = msecs_to_jiffies(1000); |
700 | 701 | ||
@@ -736,7 +737,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |||
736 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, | 737 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
737 | bool transfer_spare) | 738 | bool transfer_spare) |
738 | { | 739 | { |
739 | int ecc_en_flag = 0, transfer_spare_flag = 0; | 740 | int ecc_en_flag, transfer_spare_flag; |
740 | 741 | ||
741 | /* set ECC, transfer spare bits if needed */ | 742 | /* set ECC, transfer spare bits if needed */ |
742 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | 743 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; |
@@ -759,8 +760,8 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
759 | int op) | 760 | int op) |
760 | { | 761 | { |
761 | int status = PASS; | 762 | int status = PASS; |
762 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, | 763 | uint32_t page_count = 1; |
763 | irq_mask = 0; | 764 | uint32_t addr, cmd, irq_status, irq_mask; |
764 | 765 | ||
765 | if (op == DENALI_READ) | 766 | if (op == DENALI_READ) |
766 | irq_mask = INTR_STATUS__LOAD_COMP; | 767 | irq_mask = INTR_STATUS__LOAD_COMP; |
@@ -829,7 +830,7 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali, | |||
829 | const uint8_t *buf, | 830 | const uint8_t *buf, |
830 | int len) | 831 | int len) |
831 | { | 832 | { |
832 | uint32_t i = 0, *buf32; | 833 | uint32_t i, *buf32; |
833 | 834 | ||
834 | /* | 835 | /* |
835 | * verify that the len is a multiple of 4. | 836 | * verify that the len is a multiple of 4. |
@@ -849,7 +850,7 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali, | |||
849 | uint8_t *buf, | 850 | uint8_t *buf, |
850 | int len) | 851 | int len) |
851 | { | 852 | { |
852 | uint32_t i = 0, *buf32; | 853 | uint32_t i, *buf32; |
853 | 854 | ||
854 | /* | 855 | /* |
855 | * we assume that len will be a multiple of 4, if not it would be nice | 856 | * we assume that len will be a multiple of 4, if not it would be nice |
@@ -870,7 +871,7 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali, | |||
870 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | 871 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
871 | { | 872 | { |
872 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 873 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
873 | uint32_t irq_status = 0; | 874 | uint32_t irq_status; |
874 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | | 875 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
875 | INTR_STATUS__PROGRAM_FAIL; | 876 | INTR_STATUS__PROGRAM_FAIL; |
876 | int status = 0; | 877 | int status = 0; |
@@ -899,8 +900,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
899 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | 900 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
900 | { | 901 | { |
901 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 902 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
902 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP, | 903 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
903 | irq_status = 0, addr = 0x0, cmd = 0x0; | 904 | uint32_t irq_status, addr, cmd; |
904 | 905 | ||
905 | denali->page = page; | 906 | denali->page = page; |
906 | 907 | ||
@@ -938,7 +939,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
938 | */ | 939 | */ |
939 | static bool is_erased(uint8_t *buf, int len) | 940 | static bool is_erased(uint8_t *buf, int len) |
940 | { | 941 | { |
941 | int i = 0; | 942 | int i; |
942 | for (i = 0; i < len; i++) | 943 | for (i = 0; i < len; i++) |
943 | if (buf[i] != 0xFF) | 944 | if (buf[i] != 0xFF) |
944 | return false; | 945 | return false; |
@@ -961,9 +962,8 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
961 | 962 | ||
962 | if (irq_status & INTR_STATUS__ECC_ERR) { | 963 | if (irq_status & INTR_STATUS__ECC_ERR) { |
963 | /* read the ECC errors. we'll ignore them for now */ | 964 | /* read the ECC errors. we'll ignore them for now */ |
964 | uint32_t err_address = 0, err_correction_info = 0; | 965 | uint32_t err_address, err_correction_info, err_byte, |
965 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; | 966 | err_sector, err_device, err_correction_value; |
966 | uint32_t err_correction_value = 0; | ||
967 | denali_set_intr_modes(denali, false); | 967 | denali_set_intr_modes(denali, false); |
968 | 968 | ||
969 | do { | 969 | do { |
@@ -1026,19 +1026,14 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
1026 | /* programs the controller to either enable/disable DMA transfers */ | 1026 | /* programs the controller to either enable/disable DMA transfers */ |
1027 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) | 1027 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
1028 | { | 1028 | { |
1029 | uint32_t reg_val = 0x0; | 1029 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
1030 | |||
1031 | if (en) | ||
1032 | reg_val = DMA_ENABLE__FLAG; | ||
1033 | |||
1034 | iowrite32(reg_val, denali->flash_reg + DMA_ENABLE); | ||
1035 | ioread32(denali->flash_reg + DMA_ENABLE); | 1030 | ioread32(denali->flash_reg + DMA_ENABLE); |
1036 | } | 1031 | } |
1037 | 1032 | ||
1038 | /* setups the HW to perform the data DMA */ | 1033 | /* setups the HW to perform the data DMA */ |
1039 | static void denali_setup_dma(struct denali_nand_info *denali, int op) | 1034 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
1040 | { | 1035 | { |
1041 | uint32_t mode = 0x0; | 1036 | uint32_t mode; |
1042 | const int page_count = 1; | 1037 | const int page_count = 1; |
1043 | dma_addr_t addr = denali->buf.dma_buf; | 1038 | dma_addr_t addr = denali->buf.dma_buf; |
1044 | 1039 | ||
@@ -1071,7 +1066,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1071 | dma_addr_t addr = denali->buf.dma_buf; | 1066 | dma_addr_t addr = denali->buf.dma_buf; |
1072 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1067 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1073 | 1068 | ||
1074 | uint32_t irq_status = 0; | 1069 | uint32_t irq_status; |
1075 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | | 1070 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1076 | INTR_STATUS__PROGRAM_FAIL; | 1071 | INTR_STATUS__PROGRAM_FAIL; |
1077 | 1072 | ||
@@ -1170,7 +1165,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1170 | dma_addr_t addr = denali->buf.dma_buf; | 1165 | dma_addr_t addr = denali->buf.dma_buf; |
1171 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1166 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1172 | 1167 | ||
1173 | uint32_t irq_status = 0; | 1168 | uint32_t irq_status; |
1174 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | | 1169 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1175 | INTR_STATUS__ECC_ERR; | 1170 | INTR_STATUS__ECC_ERR; |
1176 | bool check_erased_page = false; | 1171 | bool check_erased_page = false; |
@@ -1222,7 +1217,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1222 | dma_addr_t addr = denali->buf.dma_buf; | 1217 | dma_addr_t addr = denali->buf.dma_buf; |
1223 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1218 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1224 | 1219 | ||
1225 | uint32_t irq_status = 0; | 1220 | uint32_t irq_status; |
1226 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; | 1221 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
1227 | 1222 | ||
1228 | if (page != denali->page) { | 1223 | if (page != denali->page) { |
@@ -1286,7 +1281,7 @@ static int denali_erase(struct mtd_info *mtd, int page) | |||
1286 | { | 1281 | { |
1287 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1282 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1288 | 1283 | ||
1289 | uint32_t cmd = 0x0, irq_status = 0; | 1284 | uint32_t cmd, irq_status; |
1290 | 1285 | ||
1291 | clear_interrupts(denali); | 1286 | clear_interrupts(denali); |
1292 | 1287 | ||