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authorJosh Wu <josh.wu@atmel.com>2012-06-29 05:47:55 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-07-06 13:23:25 -0400
commit1c7b874d33b463f7150b1ab4617f000af9b327fd (patch)
tree7041d310f5dde2d745908a89418da814d28e8460 /drivers/mtd
parenta41b51a1f7c15a1b00f30a3ad2d0373ad51b883d (diff)
mtd: at91: atmel_nand: add Programmable Multibit ECC controller support
The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the address and size of PMECC, PMECC error location controllers and ROM. And also needs to pass the correction capability, the sector size and ROM lookup table offsets via dt. This driver has been tested on AT91SAM9X5-EK and AT91SAM9N12-EK with JFFS2, YAFFS2, UBIFS and mtd-utils. Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Tested-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/atmel_nand.c757
-rw-r--r--drivers/mtd/nand/atmel_nand_ecc.h114
2 files changed, 864 insertions, 7 deletions
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index b97ad9f78d39..647275524e09 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1,20 +1,22 @@
1/* 1/*
2 * Copyright (C) 2003 Rick Bronson 2 * Copyright © 2003 Rick Bronson
3 * 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c 4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 * 6 *
7 * Derived from drivers/mtd/spia.c 7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 * 9 *
10 * 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 * 13 *
14 * Derived from Das U-Boot source code 14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) 15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 * 17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
18 * 20 *
19 * This program is free software; you can redistribute it and/or modify 21 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as 22 * it under the terms of the GNU General Public License version 2 as
@@ -98,8 +100,31 @@ struct atmel_nand_host {
98 u8 pmecc_corr_cap; 100 u8 pmecc_corr_cap;
99 u16 pmecc_sector_size; 101 u16 pmecc_sector_size;
100 u32 pmecc_lookup_table_offset; 102 u32 pmecc_lookup_table_offset;
103
104 int pmecc_bytes_per_sector;
105 int pmecc_sector_number;
106 int pmecc_degree; /* Degree of remainders */
107 int pmecc_cw_len; /* Length of codeword */
108
109 void __iomem *pmerrloc_base;
110 void __iomem *pmecc_rom_base;
111
112 /* lookup table for alpha_to and index_of */
113 void __iomem *pmecc_alpha_to;
114 void __iomem *pmecc_index_of;
115
116 /* data for pmecc computation */
117 int16_t *pmecc_partial_syn;
118 int16_t *pmecc_si;
119 int16_t *pmecc_smu; /* Sigma table */
120 int16_t *pmecc_lmu; /* polynomal order */
121 int *pmecc_mu;
122 int *pmecc_dmu;
123 int *pmecc_delta;
101}; 124};
102 125
126static struct nand_ecclayout atmel_pmecc_oobinfo;
127
103static int cpu_has_dma(void) 128static int cpu_has_dma(void)
104{ 129{
105 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); 130 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
@@ -293,6 +318,703 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
293} 318}
294 319
295/* 320/*
321 * Return number of ecc bytes per sector according to sector size and
322 * correction capability
323 *
324 * Following table shows what at91 PMECC supported:
325 * Correction Capability Sector_512_bytes Sector_1024_bytes
326 * ===================== ================ =================
327 * 2-bits 4-bytes 4-bytes
328 * 4-bits 7-bytes 7-bytes
329 * 8-bits 13-bytes 14-bytes
330 * 12-bits 20-bytes 21-bytes
331 * 24-bits 39-bytes 42-bytes
332 */
333static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size)
334{
335 int m = 12 + sector_size / 512;
336 return (m * cap + 7) / 8;
337}
338
339static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout,
340 int oobsize, int ecc_len)
341{
342 int i;
343
344 layout->eccbytes = ecc_len;
345
346 /* ECC will occupy the last ecc_len bytes continuously */
347 for (i = 0; i < ecc_len; i++)
348 layout->eccpos[i] = oobsize - ecc_len + i;
349
350 layout->oobfree[0].offset = 2;
351 layout->oobfree[0].length =
352 oobsize - ecc_len - layout->oobfree[0].offset;
353}
354
355static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
356{
357 int table_size;
358
359 table_size = host->pmecc_sector_size == 512 ?
360 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
361
362 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
363 table_size * sizeof(int16_t);
364}
365
366static void pmecc_data_free(struct atmel_nand_host *host)
367{
368 kfree(host->pmecc_partial_syn);
369 kfree(host->pmecc_si);
370 kfree(host->pmecc_lmu);
371 kfree(host->pmecc_smu);
372 kfree(host->pmecc_mu);
373 kfree(host->pmecc_dmu);
374 kfree(host->pmecc_delta);
375}
376
377static int __devinit pmecc_data_alloc(struct atmel_nand_host *host)
378{
379 const int cap = host->pmecc_corr_cap;
380
381 host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
382 GFP_KERNEL);
383 host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
384 host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
385 host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
386 GFP_KERNEL);
387 host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
388 host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
389 host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
390
391 if (host->pmecc_partial_syn &&
392 host->pmecc_si &&
393 host->pmecc_lmu &&
394 host->pmecc_smu &&
395 host->pmecc_mu &&
396 host->pmecc_dmu &&
397 host->pmecc_delta)
398 return 0;
399
400 /* error happened */
401 pmecc_data_free(host);
402 return -ENOMEM;
403}
404
405static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
406{
407 struct nand_chip *nand_chip = mtd->priv;
408 struct atmel_nand_host *host = nand_chip->priv;
409 int i;
410 uint32_t value;
411
412 /* Fill odd syndromes */
413 for (i = 0; i < host->pmecc_corr_cap; i++) {
414 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
415 if (i & 1)
416 value >>= 16;
417 value &= 0xffff;
418 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
419 }
420}
421
422static void pmecc_substitute(struct mtd_info *mtd)
423{
424 struct nand_chip *nand_chip = mtd->priv;
425 struct atmel_nand_host *host = nand_chip->priv;
426 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
427 int16_t __iomem *index_of = host->pmecc_index_of;
428 int16_t *partial_syn = host->pmecc_partial_syn;
429 const int cap = host->pmecc_corr_cap;
430 int16_t *si;
431 int i, j;
432
433 /* si[] is a table that holds the current syndrome value,
434 * an element of that table belongs to the field
435 */
436 si = host->pmecc_si;
437
438 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
439
440 /* Computation 2t syndromes based on S(x) */
441 /* Odd syndromes */
442 for (i = 1; i < 2 * cap; i += 2) {
443 for (j = 0; j < host->pmecc_degree; j++) {
444 if (partial_syn[i] & ((unsigned short)0x1 << j))
445 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
446 }
447 }
448 /* Even syndrome = (Odd syndrome) ** 2 */
449 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
450 if (si[j] == 0) {
451 si[i] = 0;
452 } else {
453 int16_t tmp;
454
455 tmp = readw_relaxed(index_of + si[j]);
456 tmp = (tmp * 2) % host->pmecc_cw_len;
457 si[i] = readw_relaxed(alpha_to + tmp);
458 }
459 }
460
461 return;
462}
463
464static void pmecc_get_sigma(struct mtd_info *mtd)
465{
466 struct nand_chip *nand_chip = mtd->priv;
467 struct atmel_nand_host *host = nand_chip->priv;
468
469 int16_t *lmu = host->pmecc_lmu;
470 int16_t *si = host->pmecc_si;
471 int *mu = host->pmecc_mu;
472 int *dmu = host->pmecc_dmu; /* Discrepancy */
473 int *delta = host->pmecc_delta; /* Delta order */
474 int cw_len = host->pmecc_cw_len;
475 const int16_t cap = host->pmecc_corr_cap;
476 const int num = 2 * cap + 1;
477 int16_t __iomem *index_of = host->pmecc_index_of;
478 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
479 int i, j, k;
480 uint32_t dmu_0_count, tmp;
481 int16_t *smu = host->pmecc_smu;
482
483 /* index of largest delta */
484 int ro;
485 int largest;
486 int diff;
487
488 dmu_0_count = 0;
489
490 /* First Row */
491
492 /* Mu */
493 mu[0] = -1;
494
495 memset(smu, 0, sizeof(int16_t) * num);
496 smu[0] = 1;
497
498 /* discrepancy set to 1 */
499 dmu[0] = 1;
500 /* polynom order set to 0 */
501 lmu[0] = 0;
502 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
503
504 /* Second Row */
505
506 /* Mu */
507 mu[1] = 0;
508 /* Sigma(x) set to 1 */
509 memset(&smu[num], 0, sizeof(int16_t) * num);
510 smu[num] = 1;
511
512 /* discrepancy set to S1 */
513 dmu[1] = si[1];
514
515 /* polynom order set to 0 */
516 lmu[1] = 0;
517
518 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
519
520 /* Init the Sigma(x) last row */
521 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
522
523 for (i = 1; i <= cap; i++) {
524 mu[i + 1] = i << 1;
525 /* Begin Computing Sigma (Mu+1) and L(mu) */
526 /* check if discrepancy is set to 0 */
527 if (dmu[i] == 0) {
528 dmu_0_count++;
529
530 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
531 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
532 tmp += 2;
533 else
534 tmp += 1;
535
536 if (dmu_0_count == tmp) {
537 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
538 smu[(cap + 1) * num + j] =
539 smu[i * num + j];
540
541 lmu[cap + 1] = lmu[i];
542 return;
543 }
544
545 /* copy polynom */
546 for (j = 0; j <= lmu[i] >> 1; j++)
547 smu[(i + 1) * num + j] = smu[i * num + j];
548
549 /* copy previous polynom order to the next */
550 lmu[i + 1] = lmu[i];
551 } else {
552 ro = 0;
553 largest = -1;
554 /* find largest delta with dmu != 0 */
555 for (j = 0; j < i; j++) {
556 if ((dmu[j]) && (delta[j] > largest)) {
557 largest = delta[j];
558 ro = j;
559 }
560 }
561
562 /* compute difference */
563 diff = (mu[i] - mu[ro]);
564
565 /* Compute degree of the new smu polynomial */
566 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
567 lmu[i + 1] = lmu[i];
568 else
569 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
570
571 /* Init smu[i+1] with 0 */
572 for (k = 0; k < num; k++)
573 smu[(i + 1) * num + k] = 0;
574
575 /* Compute smu[i+1] */
576 for (k = 0; k <= lmu[ro] >> 1; k++) {
577 int16_t a, b, c;
578
579 if (!(smu[ro * num + k] && dmu[i]))
580 continue;
581 a = readw_relaxed(index_of + dmu[i]);
582 b = readw_relaxed(index_of + dmu[ro]);
583 c = readw_relaxed(index_of + smu[ro * num + k]);
584 tmp = a + (cw_len - b) + c;
585 a = readw_relaxed(alpha_to + tmp % cw_len);
586 smu[(i + 1) * num + (k + diff)] = a;
587 }
588
589 for (k = 0; k <= lmu[i] >> 1; k++)
590 smu[(i + 1) * num + k] ^= smu[i * num + k];
591 }
592
593 /* End Computing Sigma (Mu+1) and L(mu) */
594 /* In either case compute delta */
595 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
596
597 /* Do not compute discrepancy for the last iteration */
598 if (i >= cap)
599 continue;
600
601 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
602 tmp = 2 * (i - 1);
603 if (k == 0) {
604 dmu[i + 1] = si[tmp + 3];
605 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
606 int16_t a, b, c;
607 a = readw_relaxed(index_of +
608 smu[(i + 1) * num + k]);
609 b = si[2 * (i - 1) + 3 - k];
610 c = readw_relaxed(index_of + b);
611 tmp = a + c;
612 tmp %= cw_len;
613 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
614 dmu[i + 1];
615 }
616 }
617 }
618
619 return;
620}
621
622static int pmecc_err_location(struct mtd_info *mtd)
623{
624 struct nand_chip *nand_chip = mtd->priv;
625 struct atmel_nand_host *host = nand_chip->priv;
626 unsigned long end_time;
627 const int cap = host->pmecc_corr_cap;
628 const int num = 2 * cap + 1;
629 int sector_size = host->pmecc_sector_size;
630 int err_nbr = 0; /* number of error */
631 int roots_nbr; /* number of roots */
632 int i;
633 uint32_t val;
634 int16_t *smu = host->pmecc_smu;
635
636 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
637
638 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
639 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
640 smu[(cap + 1) * num + i]);
641 err_nbr++;
642 }
643
644 val = (err_nbr - 1) << 16;
645 if (sector_size == 1024)
646 val |= 1;
647
648 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
649 pmerrloc_writel(host->pmerrloc_base, ELEN,
650 sector_size * 8 + host->pmecc_degree * cap);
651
652 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
653 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
654 & PMERRLOC_CALC_DONE)) {
655 if (unlikely(time_after(jiffies, end_time))) {
656 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
657 return -1;
658 }
659 cpu_relax();
660 }
661
662 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
663 & PMERRLOC_ERR_NUM_MASK) >> 8;
664 /* Number of roots == degree of smu hence <= cap */
665 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
666 return err_nbr - 1;
667
668 /* Number of roots does not match the degree of smu
669 * unable to correct error */
670 return -1;
671}
672
673static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
674 int sector_num, int extra_bytes, int err_nbr)
675{
676 struct nand_chip *nand_chip = mtd->priv;
677 struct atmel_nand_host *host = nand_chip->priv;
678 int i = 0;
679 int byte_pos, bit_pos, sector_size, pos;
680 uint32_t tmp;
681 uint8_t err_byte;
682
683 sector_size = host->pmecc_sector_size;
684
685 while (err_nbr) {
686 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
687 byte_pos = tmp / 8;
688 bit_pos = tmp % 8;
689
690 if (byte_pos >= (sector_size + extra_bytes))
691 BUG(); /* should never happen */
692
693 if (byte_pos < sector_size) {
694 err_byte = *(buf + byte_pos);
695 *(buf + byte_pos) ^= (1 << bit_pos);
696
697 pos = sector_num * host->pmecc_sector_size + byte_pos;
698 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
699 pos, bit_pos, err_byte, *(buf + byte_pos));
700 } else {
701 /* Bit flip in OOB area */
702 tmp = sector_num * host->pmecc_bytes_per_sector
703 + (byte_pos - sector_size);
704 err_byte = ecc[tmp];
705 ecc[tmp] ^= (1 << bit_pos);
706
707 pos = tmp + nand_chip->ecc.layout->eccpos[0];
708 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
709 pos, bit_pos, err_byte, ecc[tmp]);
710 }
711
712 i++;
713 err_nbr--;
714 }
715
716 return;
717}
718
719static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
720 u8 *ecc)
721{
722 struct nand_chip *nand_chip = mtd->priv;
723 struct atmel_nand_host *host = nand_chip->priv;
724 int i, err_nbr, eccbytes;
725 uint8_t *buf_pos;
726
727 eccbytes = nand_chip->ecc.bytes;
728 for (i = 0; i < eccbytes; i++)
729 if (ecc[i] != 0xff)
730 goto normal_check;
731 /* Erased page, return OK */
732 return 0;
733
734normal_check:
735 for (i = 0; i < host->pmecc_sector_number; i++) {
736 err_nbr = 0;
737 if (pmecc_stat & 0x1) {
738 buf_pos = buf + i * host->pmecc_sector_size;
739
740 pmecc_gen_syndrome(mtd, i);
741 pmecc_substitute(mtd);
742 pmecc_get_sigma(mtd);
743
744 err_nbr = pmecc_err_location(mtd);
745 if (err_nbr == -1) {
746 dev_err(host->dev, "PMECC: Too many errors\n");
747 mtd->ecc_stats.failed++;
748 return -EIO;
749 } else {
750 pmecc_correct_data(mtd, buf_pos, ecc, i,
751 host->pmecc_bytes_per_sector, err_nbr);
752 mtd->ecc_stats.corrected += err_nbr;
753 }
754 }
755 pmecc_stat >>= 1;
756 }
757
758 return 0;
759}
760
761static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
762 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
763{
764 struct atmel_nand_host *host = chip->priv;
765 int eccsize = chip->ecc.size;
766 uint8_t *oob = chip->oob_poi;
767 uint32_t *eccpos = chip->ecc.layout->eccpos;
768 uint32_t stat;
769 unsigned long end_time;
770
771 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
772 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
773 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
774 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
775
776 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
777 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
778
779 chip->read_buf(mtd, buf, eccsize);
780 chip->read_buf(mtd, oob, mtd->oobsize);
781
782 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
783 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
784 if (unlikely(time_after(jiffies, end_time))) {
785 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
786 return -EIO;
787 }
788 cpu_relax();
789 }
790
791 stat = pmecc_readl_relaxed(host->ecc, ISR);
792 if (stat != 0)
793 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
794 return -EIO;
795
796 return 0;
797}
798
799static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
800 struct nand_chip *chip, const uint8_t *buf, int oob_required)
801{
802 struct atmel_nand_host *host = chip->priv;
803 uint32_t *eccpos = chip->ecc.layout->eccpos;
804 int i, j;
805 unsigned long end_time;
806
807 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
808 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
809
810 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
811 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
812
813 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
814 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
815
816 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
817
818 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
819 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
820 if (unlikely(time_after(jiffies, end_time))) {
821 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
822 return -EIO;
823 }
824 cpu_relax();
825 }
826
827 for (i = 0; i < host->pmecc_sector_number; i++) {
828 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
829 int pos;
830
831 pos = i * host->pmecc_bytes_per_sector + j;
832 chip->oob_poi[eccpos[pos]] =
833 pmecc_readb_ecc_relaxed(host->ecc, i, j);
834 }
835 }
836 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
837
838 return 0;
839}
840
841static void atmel_pmecc_core_init(struct mtd_info *mtd)
842{
843 struct nand_chip *nand_chip = mtd->priv;
844 struct atmel_nand_host *host = nand_chip->priv;
845 uint32_t val = 0;
846 struct nand_ecclayout *ecc_layout;
847
848 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
849 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
850
851 switch (host->pmecc_corr_cap) {
852 case 2:
853 val = PMECC_CFG_BCH_ERR2;
854 break;
855 case 4:
856 val = PMECC_CFG_BCH_ERR4;
857 break;
858 case 8:
859 val = PMECC_CFG_BCH_ERR8;
860 break;
861 case 12:
862 val = PMECC_CFG_BCH_ERR12;
863 break;
864 case 24:
865 val = PMECC_CFG_BCH_ERR24;
866 break;
867 }
868
869 if (host->pmecc_sector_size == 512)
870 val |= PMECC_CFG_SECTOR512;
871 else if (host->pmecc_sector_size == 1024)
872 val |= PMECC_CFG_SECTOR1024;
873
874 switch (host->pmecc_sector_number) {
875 case 1:
876 val |= PMECC_CFG_PAGE_1SECTOR;
877 break;
878 case 2:
879 val |= PMECC_CFG_PAGE_2SECTORS;
880 break;
881 case 4:
882 val |= PMECC_CFG_PAGE_4SECTORS;
883 break;
884 case 8:
885 val |= PMECC_CFG_PAGE_8SECTORS;
886 break;
887 }
888
889 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
890 | PMECC_CFG_AUTO_DISABLE);
891 pmecc_writel(host->ecc, CFG, val);
892
893 ecc_layout = nand_chip->ecc.layout;
894 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
895 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
896 pmecc_writel(host->ecc, EADDR,
897 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
898 /* See datasheet about PMECC Clock Control Register */
899 pmecc_writel(host->ecc, CLK, 2);
900 pmecc_writel(host->ecc, IDR, 0xff);
901 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
902}
903
904static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
905 struct atmel_nand_host *host)
906{
907 struct mtd_info *mtd = &host->mtd;
908 struct nand_chip *nand_chip = &host->nand_chip;
909 struct resource *regs, *regs_pmerr, *regs_rom;
910 int cap, sector_size, err_no;
911
912 cap = host->pmecc_corr_cap;
913 sector_size = host->pmecc_sector_size;
914 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
915 cap, sector_size);
916
917 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
918 if (!regs) {
919 dev_warn(host->dev,
920 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
921 nand_chip->ecc.mode = NAND_ECC_SOFT;
922 return 0;
923 }
924
925 host->ecc = ioremap(regs->start, resource_size(regs));
926 if (host->ecc == NULL) {
927 dev_err(host->dev, "ioremap failed\n");
928 err_no = -EIO;
929 goto err_pmecc_ioremap;
930 }
931
932 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
933 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
934 if (regs_pmerr && regs_rom) {
935 host->pmerrloc_base = ioremap(regs_pmerr->start,
936 resource_size(regs_pmerr));
937 host->pmecc_rom_base = ioremap(regs_rom->start,
938 resource_size(regs_rom));
939 }
940
941 if (!host->pmerrloc_base || !host->pmecc_rom_base) {
942 dev_err(host->dev,
943 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
944 err_no = -EIO;
945 goto err_pmloc_ioremap;
946 }
947
948 /* ECC is calculated for the whole page (1 step) */
949 nand_chip->ecc.size = mtd->writesize;
950
951 /* set ECC page size and oob layout */
952 switch (mtd->writesize) {
953 case 2048:
954 host->pmecc_degree = PMECC_GF_DIMENSION_13;
955 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
956 host->pmecc_sector_number = mtd->writesize / sector_size;
957 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
958 cap, sector_size);
959 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
960 host->pmecc_index_of = host->pmecc_rom_base +
961 host->pmecc_lookup_table_offset;
962
963 nand_chip->ecc.steps = 1;
964 nand_chip->ecc.strength = cap;
965 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
966 host->pmecc_sector_number;
967 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
968 dev_err(host->dev, "No room for ECC bytes\n");
969 err_no = -EINVAL;
970 goto err_no_ecc_room;
971 }
972 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
973 mtd->oobsize,
974 nand_chip->ecc.bytes);
975 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
976 break;
977 case 512:
978 case 1024:
979 case 4096:
980 /* TODO */
981 dev_warn(host->dev,
982 "Unsupported page size for PMECC, use Software ECC\n");
983 default:
984 /* page size not handled by HW ECC */
985 /* switching back to soft ECC */
986 nand_chip->ecc.mode = NAND_ECC_SOFT;
987 return 0;
988 }
989
990 /* Allocate data for PMECC computation */
991 err_no = pmecc_data_alloc(host);
992 if (err_no) {
993 dev_err(host->dev,
994 "Cannot allocate memory for PMECC computation!\n");
995 goto err_pmecc_data_alloc;
996 }
997
998 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
999 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1000
1001 atmel_pmecc_core_init(mtd);
1002
1003 return 0;
1004
1005err_pmecc_data_alloc:
1006err_no_ecc_room:
1007err_pmloc_ioremap:
1008 iounmap(host->ecc);
1009 if (host->pmerrloc_base)
1010 iounmap(host->pmerrloc_base);
1011 if (host->pmecc_rom_base)
1012 iounmap(host->pmecc_rom_base);
1013err_pmecc_ioremap:
1014 return err_no;
1015}
1016
1017/*
296 * Calculate HW ECC 1018 * Calculate HW ECC
297 * 1019 *
298 * function called after a write 1020 * function called after a write
@@ -747,7 +1469,11 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
747 } 1469 }
748 1470
749 if (nand_chip->ecc.mode == NAND_ECC_HW) { 1471 if (nand_chip->ecc.mode == NAND_ECC_HW) {
750 res = atmel_hw_nand_init_params(pdev, host); 1472 if (host->has_pmecc)
1473 res = atmel_pmecc_nand_init_params(pdev, host);
1474 else
1475 res = atmel_hw_nand_init_params(pdev, host);
1476
751 if (res != 0) 1477 if (res != 0)
752 goto err_hw_ecc; 1478 goto err_hw_ecc;
753 } 1479 }
@@ -766,8 +1492,16 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
766 return res; 1492 return res;
767 1493
768err_scan_tail: 1494err_scan_tail:
1495 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1496 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1497 pmecc_data_free(host);
1498 }
769 if (host->ecc) 1499 if (host->ecc)
770 iounmap(host->ecc); 1500 iounmap(host->ecc);
1501 if (host->pmerrloc_base)
1502 iounmap(host->pmerrloc_base);
1503 if (host->pmecc_rom_base)
1504 iounmap(host->pmecc_rom_base);
771err_hw_ecc: 1505err_hw_ecc:
772err_scan_ident: 1506err_scan_ident:
773err_no_card: 1507err_no_card:
@@ -793,8 +1527,19 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
793 1527
794 atmel_nand_disable(host); 1528 atmel_nand_disable(host);
795 1529
1530 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1531 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1532 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1533 PMERRLOC_DISABLE);
1534 pmecc_data_free(host);
1535 }
1536
796 if (host->ecc) 1537 if (host->ecc)
797 iounmap(host->ecc); 1538 iounmap(host->ecc);
1539 if (host->pmecc_rom_base)
1540 iounmap(host->pmecc_rom_base);
1541 if (host->pmerrloc_base)
1542 iounmap(host->pmerrloc_base);
798 1543
799 if (host->dma_chan) 1544 if (host->dma_chan)
800 dma_release_channel(host->dma_chan); 1545 dma_release_channel(host->dma_chan);
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 578c776e1356..8a1e9a686759 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -3,7 +3,7 @@
3 * Based on AT91SAM9260 datasheet revision B. 3 * Based on AT91SAM9260 datasheet revision B.
4 * 4 *
5 * Copyright (C) 2007 Andrew Victor 5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 Atmel Corporation. 6 * Copyright (C) 2007 - 2012 Atmel Corporation.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -36,4 +36,116 @@
36#define ATMEL_ECC_NPR 0x10 /* NParity register */ 36#define ATMEL_ECC_NPR 0x10 /* NParity register */
37#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ 37#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
38 38
39/* PMECC Register Definitions */
40#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */
41#define PMECC_CFG_BCH_ERR2 (0 << 0)
42#define PMECC_CFG_BCH_ERR4 (1 << 0)
43#define PMECC_CFG_BCH_ERR8 (2 << 0)
44#define PMECC_CFG_BCH_ERR12 (3 << 0)
45#define PMECC_CFG_BCH_ERR24 (4 << 0)
46
47#define PMECC_CFG_SECTOR512 (0 << 4)
48#define PMECC_CFG_SECTOR1024 (1 << 4)
49
50#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
51#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
52#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
53#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
54
55#define PMECC_CFG_READ_OP (0 << 12)
56#define PMECC_CFG_WRITE_OP (1 << 12)
57
58#define PMECC_CFG_SPARE_ENABLE (1 << 16)
59#define PMECC_CFG_SPARE_DISABLE (0 << 16)
60
61#define PMECC_CFG_AUTO_ENABLE (1 << 20)
62#define PMECC_CFG_AUTO_DISABLE (0 << 20)
63
64#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */
65#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */
66#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */
67#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */
68#define PMECC_CLK_133MHZ (2 << 0)
69
70#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */
71#define PMECC_CTRL_RST (1 << 0)
72#define PMECC_CTRL_DATA (1 << 1)
73#define PMECC_CTRL_USER (1 << 2)
74#define PMECC_CTRL_ENABLE (1 << 4)
75#define PMECC_CTRL_DISABLE (1 << 5)
76
77#define ATMEL_PMECC_SR 0x018 /* PMECC status register */
78#define PMECC_SR_BUSY (1 << 0)
79#define PMECC_SR_ENABLE (1 << 4)
80
81#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */
82#define PMECC_IER_ENABLE (1 << 0)
83#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */
84#define PMECC_IER_DISABLE (1 << 0)
85#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */
86#define PMECC_IER_MASK (1 << 0)
87#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */
88#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */
89#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */
90
91/* PMERRLOC Register Definitions */
92#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */
93#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
94#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
95#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
96
97#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */
98#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */
99#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */
100#define PMERRLOC_DISABLE (1 << 0)
101
102#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */
103#define PMERRLOC_ELSR_BUSY (1 << 0)
104#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */
105#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */
106#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */
107#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */
108#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
109#define PMERRLOC_CALC_DONE (1 << 0)
110#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */
111#define ATMEL_PMERRLOC_ELx 0x08c /* Error location x */
112
113/* Register access macros for PMECC */
114#define pmecc_readl_relaxed(addr, reg) \
115 readl_relaxed((addr) + ATMEL_PMECC_##reg)
116
117#define pmecc_writel(addr, reg, value) \
118 writel((value), (addr) + ATMEL_PMECC_##reg)
119
120#define pmecc_readb_ecc_relaxed(addr, sector, n) \
121 readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
122
123#define pmecc_readl_rem_relaxed(addr, sector, n) \
124 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
125
126#define pmerrloc_readl_relaxed(addr, reg) \
127 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
128
129#define pmerrloc_writel(addr, reg, value) \
130 writel((value), (addr) + ATMEL_PMERRLOC_##reg)
131
132#define pmerrloc_writel_sigma_relaxed(addr, n, value) \
133 writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
134
135#define pmerrloc_readl_sigma_relaxed(addr, n) \
136 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
137
138#define pmerrloc_readl_el_relaxed(addr, n) \
139 readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
140
141/* Galois field dimension */
142#define PMECC_GF_DIMENSION_13 13
143#define PMECC_GF_DIMENSION_14 14
144
145#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000
146#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000
147
148/* Time out value for reading PMECC status register */
149#define PMECC_MAX_TIMEOUT_MS 100
150
39#endif 151#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 05:47:37 -0500