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authorDavid Woodhouse <dwmw2@infradead.org>2008-04-22 07:34:25 -0400
committerDavid Woodhouse <dwmw2@infradead.org>2008-04-22 07:34:25 -0400
commitf838bad1b3be8ca0c785ee0e0c570dfda74cf377 (patch)
tree5a842a8056a708cfad55a20fa8ab733dd94b0903 /drivers/mtd
parentdd919660aacdf4adfcd279556aa03e595f7f0fc2 (diff)
parent807501475fce0ebe68baedf87f202c3e4ee0d12c (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0001.c10
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c1
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0020.c1
-rw-r--r--drivers/mtd/devices/block2mtd.c1
-rw-r--r--drivers/mtd/maps/physmap.c15
-rw-r--r--drivers/mtd/nand/Kconfig2
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c219
-rw-r--r--drivers/mtd/nand/orion_nand.c2
-rw-r--r--drivers/mtd/nand/rtc_from4.c2
-rw-r--r--drivers/mtd/ubi/build.c4
-rw-r--r--drivers/mtd/ubi/ubi.h10
-rw-r--r--drivers/mtd/ubi/vmt.c4
-rw-r--r--drivers/mtd/ubi/vtbl.c1
13 files changed, 40 insertions, 232 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
index 47794d23a42e..0080452531d6 100644
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
@@ -718,7 +718,7 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long
718 /* Someone else might have been playing with it. */ 718 /* Someone else might have been playing with it. */
719 return -EAGAIN; 719 return -EAGAIN;
720 } 720 }
721 721 /* Fall through */
722 case FL_READY: 722 case FL_READY:
723 case FL_CFI_QUERY: 723 case FL_CFI_QUERY:
724 case FL_JEDEC_QUERY: 724 case FL_JEDEC_QUERY:
@@ -778,14 +778,14 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long
778 chip->state = FL_READY; 778 chip->state = FL_READY;
779 return 0; 779 return 0;
780 780
781 case FL_SHUTDOWN:
782 /* The machine is rebooting now,so no one can get chip anymore */
783 return -EIO;
781 case FL_POINT: 784 case FL_POINT:
782 /* Only if there's no operation suspended... */ 785 /* Only if there's no operation suspended... */
783 if (mode == FL_READY && chip->oldstate == FL_READY) 786 if (mode == FL_READY && chip->oldstate == FL_READY)
784 return 0; 787 return 0;
785 788 /* Fall through */
786 case FL_SHUTDOWN:
787 /* The machine is rebooting now,so no one can get chip anymore */
788 return -EIO;
789 default: 789 default:
790 sleep: 790 sleep:
791 set_current_state(TASK_UNINTERRUPTIBLE); 791 set_current_state(TASK_UNINTERRUPTIBLE);
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index d072e87ce4e2..458d477614d6 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -1763,6 +1763,7 @@ static void cfi_amdstd_sync (struct mtd_info *mtd)
1763 1763
1764 default: 1764 default:
1765 /* Not an idle state */ 1765 /* Not an idle state */
1766 set_current_state(TASK_UNINTERRUPTIBLE);
1766 add_wait_queue(&chip->wq, &wait); 1767 add_wait_queue(&chip->wq, &wait);
1767 1768
1768 spin_unlock(chip->mutex); 1769 spin_unlock(chip->mutex);
diff --git a/drivers/mtd/chips/cfi_cmdset_0020.c b/drivers/mtd/chips/cfi_cmdset_0020.c
index b344ff858b2d..492e2ab27420 100644
--- a/drivers/mtd/chips/cfi_cmdset_0020.c
+++ b/drivers/mtd/chips/cfi_cmdset_0020.c
@@ -1015,6 +1015,7 @@ static void cfi_staa_sync (struct mtd_info *mtd)
1015 1015
1016 default: 1016 default:
1017 /* Not an idle state */ 1017 /* Not an idle state */
1018 set_current_state(TASK_UNINTERRUPTIBLE);
1018 add_wait_queue(&chip->wq, &wait); 1019 add_wait_queue(&chip->wq, &wait);
1019 1020
1020 spin_unlock_bh(chip->mutex); 1021 spin_unlock_bh(chip->mutex);
diff --git a/drivers/mtd/devices/block2mtd.c b/drivers/mtd/devices/block2mtd.c
index eeaaa9dce6ef..ad1880c67518 100644
--- a/drivers/mtd/devices/block2mtd.c
+++ b/drivers/mtd/devices/block2mtd.c
@@ -408,7 +408,6 @@ static int block2mtd_setup2(const char *val)
408 if (token[1]) { 408 if (token[1]) {
409 ret = parse_num(&erase_size, token[1]); 409 ret = parse_num(&erase_size, token[1]);
410 if (ret) { 410 if (ret) {
411 kfree(name);
412 parse_err("illegal erase size"); 411 parse_err("illegal erase size");
413 } 412 }
414 } 413 }
diff --git a/drivers/mtd/maps/physmap.c b/drivers/mtd/maps/physmap.c
index f00e04efbe28..bc4649a17b9d 100644
--- a/drivers/mtd/maps/physmap.c
+++ b/drivers/mtd/maps/physmap.c
@@ -202,9 +202,8 @@ static int physmap_flash_suspend(struct platform_device *dev, pm_message_t state
202 int ret = 0; 202 int ret = 0;
203 int i; 203 int i;
204 204
205 if (info) 205 for (i = 0; i < MAX_RESOURCES && info->mtd[i]; i++)
206 for (i = 0; i < MAX_RESOURCES; i++) 206 ret |= info->mtd[i]->suspend(info->mtd[i]);
207 ret |= info->mtd[i]->suspend(info->mtd[i]);
208 207
209 return ret; 208 return ret;
210} 209}
@@ -214,9 +213,9 @@ static int physmap_flash_resume(struct platform_device *dev)
214 struct physmap_flash_info *info = platform_get_drvdata(dev); 213 struct physmap_flash_info *info = platform_get_drvdata(dev);
215 int i; 214 int i;
216 215
217 if (info) 216 for (i = 0; i < MAX_RESOURCES && info->mtd[i]; i++)
218 for (i = 0; i < MAX_RESOURCES; i++) 217 info->mtd[i]->resume(info->mtd[i]);
219 info->mtd[i]->resume(info->mtd[i]); 218
220 return 0; 219 return 0;
221} 220}
222 221
@@ -225,8 +224,8 @@ static void physmap_flash_shutdown(struct platform_device *dev)
225 struct physmap_flash_info *info = platform_get_drvdata(dev); 224 struct physmap_flash_info *info = platform_get_drvdata(dev);
226 int i; 225 int i;
227 226
228 for (i = 0; i < MAX_RESOURCES; i++) 227 for (i = 0; i < MAX_RESOURCES && info->mtd[i]; i++)
229 if (info && info->mtd[i]->suspend(info->mtd[i]) == 0) 228 if (info->mtd[i]->suspend(info->mtd[i]) == 0)
230 info->mtd[i]->resume(info->mtd[i]); 229 info->mtd[i]->resume(info->mtd[i]);
231} 230}
232#else 231#else
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4a3c6759492b..959fb86cda01 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -314,7 +314,7 @@ config MTD_ALAUDA
314 314
315config MTD_NAND_ORION 315config MTD_NAND_ORION
316 tristate "NAND Flash support for Marvell Orion SoC" 316 tristate "NAND Flash support for Marvell Orion SoC"
317 depends on ARCH_ORION && MTD_NAND 317 depends on PLAT_ORION && MTD_NAND
318 help 318 help
319 This enables the NAND flash controller on Orion machines. 319 This enables the NAND flash controller on Orion machines.
320 320
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index b025dfe0b274..378b7aa63812 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -36,207 +36,12 @@
36#include <linux/mtd/partitions.h> 36#include <linux/mtd/partitions.h>
37 37
38#include <asm/io.h> 38#include <asm/io.h>
39 39#include <asm/fsl_lbc.h>
40 40
41#define MAX_BANKS 8 41#define MAX_BANKS 8
42#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ 42#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ 43#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
44 44
45struct elbc_bank {
46 __be32 br; /**< Base Register */
47#define BR_BA 0xFFFF8000
48#define BR_BA_SHIFT 15
49#define BR_PS 0x00001800
50#define BR_PS_SHIFT 11
51#define BR_PS_8 0x00000800 /* Port Size 8 bit */
52#define BR_PS_16 0x00001000 /* Port Size 16 bit */
53#define BR_PS_32 0x00001800 /* Port Size 32 bit */
54#define BR_DECC 0x00000600
55#define BR_DECC_SHIFT 9
56#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
57#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
58#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
59#define BR_WP 0x00000100
60#define BR_WP_SHIFT 8
61#define BR_MSEL 0x000000E0
62#define BR_MSEL_SHIFT 5
63#define BR_MS_GPCM 0x00000000 /* GPCM */
64#define BR_MS_FCM 0x00000020 /* FCM */
65#define BR_MS_SDRAM 0x00000060 /* SDRAM */
66#define BR_MS_UPMA 0x00000080 /* UPMA */
67#define BR_MS_UPMB 0x000000A0 /* UPMB */
68#define BR_MS_UPMC 0x000000C0 /* UPMC */
69#define BR_V 0x00000001
70#define BR_V_SHIFT 0
71#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
72
73 __be32 or; /**< Base Register */
74#define OR0 0x5004
75#define OR1 0x500C
76#define OR2 0x5014
77#define OR3 0x501C
78#define OR4 0x5024
79#define OR5 0x502C
80#define OR6 0x5034
81#define OR7 0x503C
82
83#define OR_FCM_AM 0xFFFF8000
84#define OR_FCM_AM_SHIFT 15
85#define OR_FCM_BCTLD 0x00001000
86#define OR_FCM_BCTLD_SHIFT 12
87#define OR_FCM_PGS 0x00000400
88#define OR_FCM_PGS_SHIFT 10
89#define OR_FCM_CSCT 0x00000200
90#define OR_FCM_CSCT_SHIFT 9
91#define OR_FCM_CST 0x00000100
92#define OR_FCM_CST_SHIFT 8
93#define OR_FCM_CHT 0x00000080
94#define OR_FCM_CHT_SHIFT 7
95#define OR_FCM_SCY 0x00000070
96#define OR_FCM_SCY_SHIFT 4
97#define OR_FCM_SCY_1 0x00000010
98#define OR_FCM_SCY_2 0x00000020
99#define OR_FCM_SCY_3 0x00000030
100#define OR_FCM_SCY_4 0x00000040
101#define OR_FCM_SCY_5 0x00000050
102#define OR_FCM_SCY_6 0x00000060
103#define OR_FCM_SCY_7 0x00000070
104#define OR_FCM_RST 0x00000008
105#define OR_FCM_RST_SHIFT 3
106#define OR_FCM_TRLX 0x00000004
107#define OR_FCM_TRLX_SHIFT 2
108#define OR_FCM_EHTR 0x00000002
109#define OR_FCM_EHTR_SHIFT 1
110};
111
112struct elbc_regs {
113 struct elbc_bank bank[8];
114 u8 res0[0x28];
115 __be32 mar; /**< UPM Address Register */
116 u8 res1[0x4];
117 __be32 mamr; /**< UPMA Mode Register */
118 __be32 mbmr; /**< UPMB Mode Register */
119 __be32 mcmr; /**< UPMC Mode Register */
120 u8 res2[0x8];
121 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
122 __be32 mdr; /**< UPM Data Register */
123 u8 res3[0x4];
124 __be32 lsor; /**< Special Operation Initiation Register */
125 __be32 lsdmr; /**< SDRAM Mode Register */
126 u8 res4[0x8];
127 __be32 lurt; /**< UPM Refresh Timer */
128 __be32 lsrt; /**< SDRAM Refresh Timer */
129 u8 res5[0x8];
130 __be32 ltesr; /**< Transfer Error Status Register */
131#define LTESR_BM 0x80000000
132#define LTESR_FCT 0x40000000
133#define LTESR_PAR 0x20000000
134#define LTESR_WP 0x04000000
135#define LTESR_ATMW 0x00800000
136#define LTESR_ATMR 0x00400000
137#define LTESR_CS 0x00080000
138#define LTESR_CC 0x00000001
139#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
140 __be32 ltedr; /**< Transfer Error Disable Register */
141 __be32 lteir; /**< Transfer Error Interrupt Register */
142 __be32 lteatr; /**< Transfer Error Attributes Register */
143 __be32 ltear; /**< Transfer Error Address Register */
144 u8 res6[0xC];
145 __be32 lbcr; /**< Configuration Register */
146#define LBCR_LDIS 0x80000000
147#define LBCR_LDIS_SHIFT 31
148#define LBCR_BCTLC 0x00C00000
149#define LBCR_BCTLC_SHIFT 22
150#define LBCR_AHD 0x00200000
151#define LBCR_LPBSE 0x00020000
152#define LBCR_LPBSE_SHIFT 17
153#define LBCR_EPAR 0x00010000
154#define LBCR_EPAR_SHIFT 16
155#define LBCR_BMT 0x0000FF00
156#define LBCR_BMT_SHIFT 8
157#define LBCR_INIT 0x00040000
158 __be32 lcrr; /**< Clock Ratio Register */
159#define LCRR_DBYP 0x80000000
160#define LCRR_DBYP_SHIFT 31
161#define LCRR_BUFCMDC 0x30000000
162#define LCRR_BUFCMDC_SHIFT 28
163#define LCRR_ECL 0x03000000
164#define LCRR_ECL_SHIFT 24
165#define LCRR_EADC 0x00030000
166#define LCRR_EADC_SHIFT 16
167#define LCRR_CLKDIV 0x0000000F
168#define LCRR_CLKDIV_SHIFT 0
169 u8 res7[0x8];
170 __be32 fmr; /**< Flash Mode Register */
171#define FMR_CWTO 0x0000F000
172#define FMR_CWTO_SHIFT 12
173#define FMR_BOOT 0x00000800
174#define FMR_ECCM 0x00000100
175#define FMR_AL 0x00000030
176#define FMR_AL_SHIFT 4
177#define FMR_OP 0x00000003
178#define FMR_OP_SHIFT 0
179 __be32 fir; /**< Flash Instruction Register */
180#define FIR_OP0 0xF0000000
181#define FIR_OP0_SHIFT 28
182#define FIR_OP1 0x0F000000
183#define FIR_OP1_SHIFT 24
184#define FIR_OP2 0x00F00000
185#define FIR_OP2_SHIFT 20
186#define FIR_OP3 0x000F0000
187#define FIR_OP3_SHIFT 16
188#define FIR_OP4 0x0000F000
189#define FIR_OP4_SHIFT 12
190#define FIR_OP5 0x00000F00
191#define FIR_OP5_SHIFT 8
192#define FIR_OP6 0x000000F0
193#define FIR_OP6_SHIFT 4
194#define FIR_OP7 0x0000000F
195#define FIR_OP7_SHIFT 0
196#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
197#define FIR_OP_CA 0x1 /* Issue current column address */
198#define FIR_OP_PA 0x2 /* Issue current block+page address */
199#define FIR_OP_UA 0x3 /* Issue user defined address */
200#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
201#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
202#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
203#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
204#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
205#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
206#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
207#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
208#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
209#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
210#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
211#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
212 __be32 fcr; /**< Flash Command Register */
213#define FCR_CMD0 0xFF000000
214#define FCR_CMD0_SHIFT 24
215#define FCR_CMD1 0x00FF0000
216#define FCR_CMD1_SHIFT 16
217#define FCR_CMD2 0x0000FF00
218#define FCR_CMD2_SHIFT 8
219#define FCR_CMD3 0x000000FF
220#define FCR_CMD3_SHIFT 0
221 __be32 fbar; /**< Flash Block Address Register */
222#define FBAR_BLK 0x00FFFFFF
223 __be32 fpar; /**< Flash Page Address Register */
224#define FPAR_SP_PI 0x00007C00
225#define FPAR_SP_PI_SHIFT 10
226#define FPAR_SP_MS 0x00000200
227#define FPAR_SP_CI 0x000001FF
228#define FPAR_SP_CI_SHIFT 0
229#define FPAR_LP_PI 0x0003F000
230#define FPAR_LP_PI_SHIFT 12
231#define FPAR_LP_MS 0x00000800
232#define FPAR_LP_CI 0x000007FF
233#define FPAR_LP_CI_SHIFT 0
234 __be32 fbcr; /**< Flash Byte Count Register */
235#define FBCR_BC 0x00000FFF
236 u8 res11[0x8];
237 u8 res8[0xF00];
238};
239
240struct fsl_elbc_ctrl; 45struct fsl_elbc_ctrl;
241 46
242/* mtd information per set */ 47/* mtd information per set */
@@ -261,7 +66,7 @@ struct fsl_elbc_ctrl {
261 66
262 /* device info */ 67 /* device info */
263 struct device *dev; 68 struct device *dev;
264 struct elbc_regs __iomem *regs; 69 struct fsl_lbc_regs __iomem *regs;
265 int irq; 70 int irq;
266 wait_queue_head_t irq_wait; 71 wait_queue_head_t irq_wait;
267 unsigned int irq_status; /* status read from LTESR by irq handler */ 72 unsigned int irq_status; /* status read from LTESR by irq handler */
@@ -322,7 +127,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
322 struct nand_chip *chip = mtd->priv; 127 struct nand_chip *chip = mtd->priv;
323 struct fsl_elbc_mtd *priv = chip->priv; 128 struct fsl_elbc_mtd *priv = chip->priv;
324 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 129 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
325 struct elbc_regs __iomem *lbc = ctrl->regs; 130 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
326 int buf_num; 131 int buf_num;
327 132
328 ctrl->page = page_addr; 133 ctrl->page = page_addr;
@@ -363,7 +168,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
363 struct nand_chip *chip = mtd->priv; 168 struct nand_chip *chip = mtd->priv;
364 struct fsl_elbc_mtd *priv = chip->priv; 169 struct fsl_elbc_mtd *priv = chip->priv;
365 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 170 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
366 struct elbc_regs __iomem *lbc = ctrl->regs; 171 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
367 172
368 /* Setup the FMR[OP] to execute without write protection */ 173 /* Setup the FMR[OP] to execute without write protection */
369 out_be32(&lbc->fmr, priv->fmr | 3); 174 out_be32(&lbc->fmr, priv->fmr | 3);
@@ -406,7 +211,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
406{ 211{
407 struct fsl_elbc_mtd *priv = chip->priv; 212 struct fsl_elbc_mtd *priv = chip->priv;
408 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 213 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
409 struct elbc_regs __iomem *lbc = ctrl->regs; 214 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
410 215
411 if (priv->page_size) { 216 if (priv->page_size) {
412 out_be32(&lbc->fir, 217 out_be32(&lbc->fir,
@@ -439,7 +244,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
439 struct nand_chip *chip = mtd->priv; 244 struct nand_chip *chip = mtd->priv;
440 struct fsl_elbc_mtd *priv = chip->priv; 245 struct fsl_elbc_mtd *priv = chip->priv;
441 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 246 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
442 struct elbc_regs __iomem *lbc = ctrl->regs; 247 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
443 248
444 ctrl->use_mdr = 0; 249 ctrl->use_mdr = 0;
445 250
@@ -775,7 +580,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
775{ 580{
776 struct fsl_elbc_mtd *priv = chip->priv; 581 struct fsl_elbc_mtd *priv = chip->priv;
777 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 582 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
778 struct elbc_regs __iomem *lbc = ctrl->regs; 583 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
779 584
780 if (ctrl->status != LTESR_CC) 585 if (ctrl->status != LTESR_CC)
781 return NAND_STATUS_FAIL; 586 return NAND_STATUS_FAIL;
@@ -807,7 +612,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
807 struct nand_chip *chip = mtd->priv; 612 struct nand_chip *chip = mtd->priv;
808 struct fsl_elbc_mtd *priv = chip->priv; 613 struct fsl_elbc_mtd *priv = chip->priv;
809 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 614 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
810 struct elbc_regs __iomem *lbc = ctrl->regs; 615 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
811 unsigned int al; 616 unsigned int al;
812 617
813 /* calculate FMR Address Length field */ 618 /* calculate FMR Address Length field */
@@ -922,7 +727,7 @@ static void fsl_elbc_write_page(struct mtd_info *mtd,
922static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) 727static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
923{ 728{
924 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 729 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
925 struct elbc_regs __iomem *lbc = ctrl->regs; 730 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
926 struct nand_chip *chip = &priv->chip; 731 struct nand_chip *chip = &priv->chip;
927 732
928 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); 733 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
@@ -986,7 +791,7 @@ static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
986static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl, 791static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
987 struct device_node *node) 792 struct device_node *node)
988{ 793{
989 struct elbc_regs __iomem *lbc = ctrl->regs; 794 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
990 struct fsl_elbc_mtd *priv; 795 struct fsl_elbc_mtd *priv;
991 struct resource res; 796 struct resource res;
992#ifdef CONFIG_MTD_PARTITIONS 797#ifdef CONFIG_MTD_PARTITIONS
@@ -1083,7 +888,7 @@ err:
1083 888
1084static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) 889static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
1085{ 890{
1086 struct elbc_regs __iomem *lbc = ctrl->regs; 891 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
1087 892
1088 /* clear event registers */ 893 /* clear event registers */
1089 setbits32(&lbc->ltesr, LTESR_NAND_MASK); 894 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
@@ -1128,7 +933,7 @@ static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
1128static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data) 933static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
1129{ 934{
1130 struct fsl_elbc_ctrl *ctrl = data; 935 struct fsl_elbc_ctrl *ctrl = data;
1131 struct elbc_regs __iomem *lbc = ctrl->regs; 936 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
1132 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK; 937 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
1133 938
1134 if (status) { 939 if (status) {
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 9162cca0182b..ec5ad28b237e 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -18,8 +18,8 @@
18#include <linux/mtd/partitions.h> 18#include <linux/mtd/partitions.h>
19#include <asm/io.h> 19#include <asm/io.h>
20#include <asm/sizes.h> 20#include <asm/sizes.h>
21#include <asm/arch/platform.h>
22#include <asm/arch/hardware.h> 21#include <asm/arch/hardware.h>
22#include <asm/plat-orion/orion_nand.h>
23 23
24#ifdef CONFIG_MTD_CMDLINE_PARTS 24#ifdef CONFIG_MTD_CMDLINE_PARTS
25static const char *part_probes[] = { "cmdlinepart", NULL }; 25static const char *part_probes[] = { "cmdlinepart", NULL };
diff --git a/drivers/mtd/nand/rtc_from4.c b/drivers/mtd/nand/rtc_from4.c
index 9189ec8f243e..0f6ac250f434 100644
--- a/drivers/mtd/nand/rtc_from4.c
+++ b/drivers/mtd/nand/rtc_from4.c
@@ -460,7 +460,7 @@ static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this,
460 er_stat |= 1 << 1; 460 er_stat |= 1 << 1;
461 kfree(buf); 461 kfree(buf);
462 } 462 }
463 463out:
464 rtn = status; 464 rtn = status;
465 if (er_stat == 0) { /* if ECC is available */ 465 if (er_stat == 0) { /* if ECC is available */
466 rtn = (status & ~NAND_STATUS_FAIL); /* clear the error bit */ 466 rtn = (status & ~NAND_STATUS_FAIL); /* clear the error bit */
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 6ac81e35355c..275960462970 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -1000,8 +1000,8 @@ static int __init ubi_init(void)
1000 mutex_unlock(&ubi_devices_mutex); 1000 mutex_unlock(&ubi_devices_mutex);
1001 if (err < 0) { 1001 if (err < 0) {
1002 put_mtd_device(mtd); 1002 put_mtd_device(mtd);
1003 printk(KERN_ERR "UBI error: cannot attach %s\n", 1003 printk(KERN_ERR "UBI error: cannot attach mtd%d\n",
1004 p->name); 1004 mtd->index);
1005 goto out_detach; 1005 goto out_detach;
1006 } 1006 }
1007 } 1007 }
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index 457710615261..a548c1d28fa8 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -217,11 +217,11 @@ struct ubi_volume {
217 void *upd_buf; 217 void *upd_buf;
218 218
219 int *eba_tbl; 219 int *eba_tbl;
220 int checked:1; 220 unsigned int checked:1;
221 int corrupted:1; 221 unsigned int corrupted:1;
222 int upd_marker:1; 222 unsigned int upd_marker:1;
223 int updating:1; 223 unsigned int updating:1;
224 int changing_leb:1; 224 unsigned int changing_leb:1;
225 225
226#ifdef CONFIG_MTD_UBI_GLUEBI 226#ifdef CONFIG_MTD_UBI_GLUEBI
227 /* 227 /*
diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c
index a3ca2257e601..5be58d85c639 100644
--- a/drivers/mtd/ubi/vmt.c
+++ b/drivers/mtd/ubi/vmt.c
@@ -376,7 +376,9 @@ out_sysfs:
376 get_device(&vol->dev); 376 get_device(&vol->dev);
377 volume_sysfs_close(vol); 377 volume_sysfs_close(vol);
378out_gluebi: 378out_gluebi:
379 ubi_destroy_gluebi(vol); 379 if (ubi_destroy_gluebi(vol))
380 dbg_err("cannot destroy gluebi for volume %d:%d",
381 ubi->ubi_num, vol_id);
380out_cdev: 382out_cdev:
381 cdev_del(&vol->cdev); 383 cdev_del(&vol->cdev);
382out_mapping: 384out_mapping:
diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index 56fc3fbce838..af36b12be278 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -519,6 +519,7 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si,
519 if (ubi->autoresize_vol_id != -1) { 519 if (ubi->autoresize_vol_id != -1) {
520 ubi_err("more then one auto-resize volume (%d " 520 ubi_err("more then one auto-resize volume (%d "
521 "and %d)", ubi->autoresize_vol_id, i); 521 "and %d)", ubi->autoresize_vol_id, i);
522 kfree(vol);
522 return -EINVAL; 523 return -EINVAL;
523 } 524 }
524 525
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 06:08:48 -0500