omap2/3/4: Introducing 'gpmc-nand.c' for GPMC specific NAND init

Introducing 'gpmc-nand.c' for GPMC specific NAND init.
For example: GPMC timing parameters and all.
This patch also migrates gpmc related calls from 'nand/omap2.c'
to 'gpmc-nand.c'.

Signed-off-by: Vimal Singh <vimalsingh@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 4 insertions, 31 deletions

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 1bb799f0125c..26aec0080184 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -30,12 +30,8 @@
 
 #define DRIVER_NAME     "omap2-nand"
 
-/* size (4 KiB) for IO mapping */
-#define NAND_IO_SIZE    SZ_4K
-
 #define NAND_WP_OFF     0
 #define NAND_WP_BIT     0x00000010
-#define WR_RD_PIN_MONITORING    0x00600000
 
 #define GPMC_BUF_FULL   0x00000001
 #define GPMC_BUF_EMPTY  0x00000000
@@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         struct omap_nand_info           *info;
         struct omap_nand_platform_data  *pdata;
         int                             err;
-        unsigned long                   val;
-
 
         pdata = pdev->dev.platform_data;
         if (pdata == NULL) {
@@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         info->gpmc_cs           = pdata->cs;
         info->gpmc_baseaddr     = pdata->gpmc_baseaddr;
         info->gpmc_cs_baseaddr  = pdata->gpmc_cs_baseaddr;
+        info->phys_base         = pdata->phys_base;
 
         info->mtd.priv          = &info->nand;
         info->mtd.name          = dev_name(&pdev->dev);
         info->mtd.owner         = THIS_MODULE;
 
-        err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
-        if (err < 0) {
-                dev_err(&pdev->dev, "Cannot request GPMC CS\n");
-                goto out_free_info;
-        }
-
-        /* Enable RD PIN Monitoring Reg */
-        if (pdata->dev_ready) {
-                val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
-                val |= WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
-        }
-
-        val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
-        val &= ~(0xf << 8);
-        val |=  (0xc & 0xf) << 8;
-        gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
+        info->nand.options      |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
+        info->nand.options      |= NAND_SKIP_BBTSCAN;
 
         /* NAND write protect off */
         omap_nand_wp(&info->mtd, NAND_WP_OFF);
@@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
                                 pdev->dev.driver->name)) {
                 err = -EBUSY;
-                goto out_free_cs;
+                goto out_free_info;
         }
 
         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
@@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                 info->nand.chip_delay = 50;
         }
 
-        info->nand.options  |= NAND_SKIP_BBTSCAN;
-        if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
-                                                                == 0x1000)
-                info->nand.options  |= NAND_BUSWIDTH_16;
-
         if (use_prefetch) {
                 /* copy the virtual address of nand base for fifo access */
                 info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
@@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 
 out_release_mem_region:
         release_mem_region(info->phys_base, NAND_IO_SIZE);
-out_free_cs:
-        gpmc_cs_free(info->gpmc_cs);
 out_free_info:
         kfree(info);